1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_CPUTYPE_H 6 #define __ASM_CPUTYPE_H 7 8 #define INVALID_HWID ULONG_MAX 9 10 #define MPIDR_UP_BITMASK (0x1 << 30) 11 #define MPIDR_MT_BITMASK (0x1 << 24) 12 #define MPIDR_HWID_BITMASK UL(0xff00ffffff) 13 14 #define MPIDR_LEVEL_BITS_SHIFT 3 15 #define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT) 16 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) 17 18 #define MPIDR_LEVEL_SHIFT(level) \ 19 (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT) 20 21 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \ 22 ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK) 23 24 #define MIDR_REVISION_MASK 0xf 25 #define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK) 26 #define MIDR_PARTNUM_SHIFT 4 27 #define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT) 28 #define MIDR_PARTNUM(midr) \ 29 (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT) 30 #define MIDR_ARCHITECTURE_SHIFT 16 31 #define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT) 32 #define MIDR_ARCHITECTURE(midr) \ 33 (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT) 34 #define MIDR_VARIANT_SHIFT 20 35 #define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT) 36 #define MIDR_VARIANT(midr) \ 37 (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT) 38 #define MIDR_IMPLEMENTOR_SHIFT 24 39 #define MIDR_IMPLEMENTOR_MASK (0xffU << MIDR_IMPLEMENTOR_SHIFT) 40 #define MIDR_IMPLEMENTOR(midr) \ 41 (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) 42 43 #define MIDR_CPU_MODEL(imp, partnum) \ 44 ((_AT(u32, imp) << MIDR_IMPLEMENTOR_SHIFT) | \ 45 (0xf << MIDR_ARCHITECTURE_SHIFT) | \ 46 ((partnum) << MIDR_PARTNUM_SHIFT)) 47 48 #define MIDR_CPU_VAR_REV(var, rev) \ 49 (((var) << MIDR_VARIANT_SHIFT) | (rev)) 50 51 #define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \ 52 MIDR_ARCHITECTURE_MASK) 53 54 #define ARM_CPU_IMP_ARM 0x41 55 #define ARM_CPU_IMP_APM 0x50 56 #define ARM_CPU_IMP_CAVIUM 0x43 57 #define ARM_CPU_IMP_BRCM 0x42 58 #define ARM_CPU_IMP_QCOM 0x51 59 #define ARM_CPU_IMP_NVIDIA 0x4E 60 #define ARM_CPU_IMP_FUJITSU 0x46 61 #define ARM_CPU_IMP_HISI 0x48 62 #define ARM_CPU_IMP_APPLE 0x61 63 #define ARM_CPU_IMP_AMPERE 0xC0 64 65 #define ARM_CPU_PART_AEM_V8 0xD0F 66 #define ARM_CPU_PART_FOUNDATION 0xD00 67 #define ARM_CPU_PART_CORTEX_A57 0xD07 68 #define ARM_CPU_PART_CORTEX_A72 0xD08 69 #define ARM_CPU_PART_CORTEX_A53 0xD03 70 #define ARM_CPU_PART_CORTEX_A73 0xD09 71 #define ARM_CPU_PART_CORTEX_A75 0xD0A 72 #define ARM_CPU_PART_CORTEX_A35 0xD04 73 #define ARM_CPU_PART_CORTEX_A55 0xD05 74 #define ARM_CPU_PART_CORTEX_A76 0xD0B 75 #define ARM_CPU_PART_NEOVERSE_N1 0xD0C 76 #define ARM_CPU_PART_CORTEX_A77 0xD0D 77 #define ARM_CPU_PART_NEOVERSE_V1 0xD40 78 #define ARM_CPU_PART_CORTEX_A78 0xD41 79 #define ARM_CPU_PART_CORTEX_A78AE 0xD42 80 #define ARM_CPU_PART_CORTEX_X1 0xD44 81 #define ARM_CPU_PART_CORTEX_A510 0xD46 82 #define ARM_CPU_PART_CORTEX_A710 0xD47 83 #define ARM_CPU_PART_CORTEX_A715 0xD4D 84 #define ARM_CPU_PART_CORTEX_X2 0xD48 85 #define ARM_CPU_PART_NEOVERSE_N2 0xD49 86 #define ARM_CPU_PART_CORTEX_A78C 0xD4B 87 88 #define APM_CPU_PART_POTENZA 0x000 89 90 #define CAVIUM_CPU_PART_THUNDERX 0x0A1 91 #define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2 92 #define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3 93 #define CAVIUM_CPU_PART_THUNDERX2 0x0AF 94 /* OcteonTx2 series */ 95 #define CAVIUM_CPU_PART_OCTX2_98XX 0x0B1 96 #define CAVIUM_CPU_PART_OCTX2_96XX 0x0B2 97 #define CAVIUM_CPU_PART_OCTX2_95XX 0x0B3 98 #define CAVIUM_CPU_PART_OCTX2_95XXN 0x0B4 99 #define CAVIUM_CPU_PART_OCTX2_95XXMM 0x0B5 100 #define CAVIUM_CPU_PART_OCTX2_95XXO 0x0B6 101 102 #define BRCM_CPU_PART_BRAHMA_B53 0x100 103 #define BRCM_CPU_PART_VULCAN 0x516 104 105 #define QCOM_CPU_PART_FALKOR_V1 0x800 106 #define QCOM_CPU_PART_FALKOR 0xC00 107 #define QCOM_CPU_PART_KRYO 0x200 108 #define QCOM_CPU_PART_KRYO_2XX_GOLD 0x800 109 #define QCOM_CPU_PART_KRYO_2XX_SILVER 0x801 110 #define QCOM_CPU_PART_KRYO_3XX_SILVER 0x803 111 #define QCOM_CPU_PART_KRYO_4XX_GOLD 0x804 112 #define QCOM_CPU_PART_KRYO_4XX_SILVER 0x805 113 114 #define NVIDIA_CPU_PART_DENVER 0x003 115 #define NVIDIA_CPU_PART_CARMEL 0x004 116 117 #define FUJITSU_CPU_PART_A64FX 0x001 118 119 #define HISI_CPU_PART_TSV110 0xD01 120 121 #define APPLE_CPU_PART_M1_ICESTORM 0x022 122 #define APPLE_CPU_PART_M1_FIRESTORM 0x023 123 #define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024 124 #define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025 125 #define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028 126 #define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029 127 128 #define AMPERE_CPU_PART_AMPERE1 0xAC3 129 130 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) 131 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) 132 #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) 133 #define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) 134 #define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75) 135 #define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35) 136 #define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55) 137 #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76) 138 #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) 139 #define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77) 140 #define MIDR_NEOVERSE_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V1) 141 #define MIDR_CORTEX_A78 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78) 142 #define MIDR_CORTEX_A78AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE) 143 #define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1) 144 #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510) 145 #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) 146 #define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715) 147 #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) 148 #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) 149 #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) 150 #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) 151 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) 152 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) 153 #define MIDR_OCTX2_98XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_98XX) 154 #define MIDR_OCTX2_96XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_96XX) 155 #define MIDR_OCTX2_95XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XX) 156 #define MIDR_OCTX2_95XXN MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXN) 157 #define MIDR_OCTX2_95XXMM MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXMM) 158 #define MIDR_OCTX2_95XXO MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXO) 159 #define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2) 160 #define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53) 161 #define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN) 162 #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1) 163 #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR) 164 #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO) 165 #define MIDR_QCOM_KRYO_2XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_GOLD) 166 #define MIDR_QCOM_KRYO_2XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_SILVER) 167 #define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER) 168 #define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD) 169 #define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER) 170 #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER) 171 #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL) 172 #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX) 173 #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110) 174 #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM) 175 #define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM) 176 #define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO) 177 #define MIDR_APPLE_M1_FIRESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO) 178 #define MIDR_APPLE_M1_ICESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX) 179 #define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX) 180 #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1) 181 182 /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */ 183 #define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX 184 #define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_CPU_VAR_REV(1, 0)) 185 #define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 | TCR_NFD0) 186 187 #ifndef __ASSEMBLY__ 188 189 #include <asm/sysreg.h> 190 191 #define read_cpuid(reg) read_sysreg_s(SYS_ ## reg) 192 193 /* 194 * Represent a range of MIDR values for a given CPU model and a 195 * range of variant/revision values. 196 * 197 * @model - CPU model as defined by MIDR_CPU_MODEL 198 * @rv_min - Minimum value for the revision/variant as defined by 199 * MIDR_CPU_VAR_REV 200 * @rv_max - Maximum value for the variant/revision for the range. 201 */ 202 struct midr_range { 203 u32 model; 204 u32 rv_min; 205 u32 rv_max; 206 }; 207 208 #define MIDR_RANGE(m, v_min, r_min, v_max, r_max) \ 209 { \ 210 .model = m, \ 211 .rv_min = MIDR_CPU_VAR_REV(v_min, r_min), \ 212 .rv_max = MIDR_CPU_VAR_REV(v_max, r_max), \ 213 } 214 215 #define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max) 216 #define MIDR_REV(m, v, r) MIDR_RANGE(m, v, r, v, r) 217 #define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf) 218 219 static inline bool midr_is_cpu_model_range(u32 midr, u32 model, u32 rv_min, 220 u32 rv_max) 221 { 222 u32 _model = midr & MIDR_CPU_MODEL_MASK; 223 u32 rv = midr & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); 224 225 return _model == model && rv >= rv_min && rv <= rv_max; 226 } 227 228 static inline bool is_midr_in_range(u32 midr, struct midr_range const *range) 229 { 230 return midr_is_cpu_model_range(midr, range->model, 231 range->rv_min, range->rv_max); 232 } 233 234 static inline bool 235 is_midr_in_range_list(u32 midr, struct midr_range const *ranges) 236 { 237 while (ranges->model) 238 if (is_midr_in_range(midr, ranges++)) 239 return true; 240 return false; 241 } 242 243 /* 244 * The CPU ID never changes at run time, so we might as well tell the 245 * compiler that it's constant. Use this function to read the CPU ID 246 * rather than directly reading processor_id or read_cpuid() directly. 247 */ 248 static inline u32 __attribute_const__ read_cpuid_id(void) 249 { 250 return read_cpuid(MIDR_EL1); 251 } 252 253 static inline u64 __attribute_const__ read_cpuid_mpidr(void) 254 { 255 return read_cpuid(MPIDR_EL1); 256 } 257 258 static inline unsigned int __attribute_const__ read_cpuid_implementor(void) 259 { 260 return MIDR_IMPLEMENTOR(read_cpuid_id()); 261 } 262 263 static inline unsigned int __attribute_const__ read_cpuid_part_number(void) 264 { 265 return MIDR_PARTNUM(read_cpuid_id()); 266 } 267 268 static inline u32 __attribute_const__ read_cpuid_cachetype(void) 269 { 270 return read_cpuid(CTR_EL0); 271 } 272 #endif /* __ASSEMBLY__ */ 273 274 #endif 275