1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Based on arch/arm/include/asm/ptrace.h 4 * 5 * Copyright (C) 1996-2003 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 #ifndef __ASM_PTRACE_H 9 #define __ASM_PTRACE_H 10 11 #include <asm/cpufeature.h> 12 13 #include <uapi/asm/ptrace.h> 14 15 /* Current Exception Level values, as contained in CurrentEL */ 16 #define CurrentEL_EL1 (1 << 2) 17 #define CurrentEL_EL2 (2 << 2) 18 19 /* 20 * PMR values used to mask/unmask interrupts. 21 * 22 * GIC priority masking works as follows: if an IRQ's priority is a higher value 23 * than the value held in PMR, that IRQ is masked. Lowering the value of PMR 24 * means masking more IRQs (or at least that the same IRQs remain masked). 25 * 26 * To mask interrupts, we clear the most significant bit of PMR. 27 */ 28 #define GIC_PRIO_IRQON 0xf0 29 #define GIC_PRIO_IRQOFF (GIC_PRIO_IRQON & ~0x80) 30 31 /* Additional SPSR bits not exposed in the UABI */ 32 #define PSR_IL_BIT (1 << 20) 33 34 /* AArch32-specific ptrace requests */ 35 #define COMPAT_PTRACE_GETREGS 12 36 #define COMPAT_PTRACE_SETREGS 13 37 #define COMPAT_PTRACE_GET_THREAD_AREA 22 38 #define COMPAT_PTRACE_SET_SYSCALL 23 39 #define COMPAT_PTRACE_GETVFPREGS 27 40 #define COMPAT_PTRACE_SETVFPREGS 28 41 #define COMPAT_PTRACE_GETHBPREGS 29 42 #define COMPAT_PTRACE_SETHBPREGS 30 43 44 /* SPSR_ELx bits for exceptions taken from AArch32 */ 45 #define PSR_AA32_MODE_MASK 0x0000001f 46 #define PSR_AA32_MODE_USR 0x00000010 47 #define PSR_AA32_MODE_FIQ 0x00000011 48 #define PSR_AA32_MODE_IRQ 0x00000012 49 #define PSR_AA32_MODE_SVC 0x00000013 50 #define PSR_AA32_MODE_ABT 0x00000017 51 #define PSR_AA32_MODE_HYP 0x0000001a 52 #define PSR_AA32_MODE_UND 0x0000001b 53 #define PSR_AA32_MODE_SYS 0x0000001f 54 #define PSR_AA32_T_BIT 0x00000020 55 #define PSR_AA32_F_BIT 0x00000040 56 #define PSR_AA32_I_BIT 0x00000080 57 #define PSR_AA32_A_BIT 0x00000100 58 #define PSR_AA32_E_BIT 0x00000200 59 #define PSR_AA32_SSBS_BIT 0x00800000 60 #define PSR_AA32_DIT_BIT 0x01000000 61 #define PSR_AA32_Q_BIT 0x08000000 62 #define PSR_AA32_V_BIT 0x10000000 63 #define PSR_AA32_C_BIT 0x20000000 64 #define PSR_AA32_Z_BIT 0x40000000 65 #define PSR_AA32_N_BIT 0x80000000 66 #define PSR_AA32_IT_MASK 0x0600fc00 /* If-Then execution state mask */ 67 #define PSR_AA32_GE_MASK 0x000f0000 68 69 #ifdef CONFIG_CPU_BIG_ENDIAN 70 #define PSR_AA32_ENDSTATE PSR_AA32_E_BIT 71 #else 72 #define PSR_AA32_ENDSTATE 0 73 #endif 74 75 /* AArch32 CPSR bits, as seen in AArch32 */ 76 #define COMPAT_PSR_DIT_BIT 0x00200000 77 78 /* 79 * These are 'magic' values for PTRACE_PEEKUSR that return info about where a 80 * process is located in memory. 81 */ 82 #define COMPAT_PT_TEXT_ADDR 0x10000 83 #define COMPAT_PT_DATA_ADDR 0x10004 84 #define COMPAT_PT_TEXT_END_ADDR 0x10008 85 86 /* 87 * If pt_regs.syscallno == NO_SYSCALL, then the thread is not executing 88 * a syscall -- i.e., its most recent entry into the kernel from 89 * userspace was not via SVC, or otherwise a tracer cancelled the syscall. 90 * 91 * This must have the value -1, for ABI compatibility with ptrace etc. 92 */ 93 #define NO_SYSCALL (-1) 94 95 #ifndef __ASSEMBLY__ 96 #include <linux/bug.h> 97 #include <linux/types.h> 98 99 /* sizeof(struct user) for AArch32 */ 100 #define COMPAT_USER_SZ 296 101 102 /* Architecturally defined mapping between AArch32 and AArch64 registers */ 103 #define compat_usr(x) regs[(x)] 104 #define compat_fp regs[11] 105 #define compat_sp regs[13] 106 #define compat_lr regs[14] 107 #define compat_sp_hyp regs[15] 108 #define compat_lr_irq regs[16] 109 #define compat_sp_irq regs[17] 110 #define compat_lr_svc regs[18] 111 #define compat_sp_svc regs[19] 112 #define compat_lr_abt regs[20] 113 #define compat_sp_abt regs[21] 114 #define compat_lr_und regs[22] 115 #define compat_sp_und regs[23] 116 #define compat_r8_fiq regs[24] 117 #define compat_r9_fiq regs[25] 118 #define compat_r10_fiq regs[26] 119 #define compat_r11_fiq regs[27] 120 #define compat_r12_fiq regs[28] 121 #define compat_sp_fiq regs[29] 122 #define compat_lr_fiq regs[30] 123 124 static inline unsigned long compat_psr_to_pstate(const unsigned long psr) 125 { 126 unsigned long pstate; 127 128 pstate = psr & ~COMPAT_PSR_DIT_BIT; 129 130 if (psr & COMPAT_PSR_DIT_BIT) 131 pstate |= PSR_AA32_DIT_BIT; 132 133 return pstate; 134 } 135 136 static inline unsigned long pstate_to_compat_psr(const unsigned long pstate) 137 { 138 unsigned long psr; 139 140 psr = pstate & ~PSR_AA32_DIT_BIT; 141 142 if (pstate & PSR_AA32_DIT_BIT) 143 psr |= COMPAT_PSR_DIT_BIT; 144 145 return psr; 146 } 147 148 /* 149 * This struct defines the way the registers are stored on the stack during an 150 * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for 151 * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs. 152 */ 153 struct pt_regs { 154 union { 155 struct user_pt_regs user_regs; 156 struct { 157 u64 regs[31]; 158 u64 sp; 159 u64 pc; 160 u64 pstate; 161 }; 162 }; 163 u64 orig_x0; 164 #ifdef __AARCH64EB__ 165 u32 unused2; 166 s32 syscallno; 167 #else 168 s32 syscallno; 169 u32 unused2; 170 #endif 171 172 u64 orig_addr_limit; 173 /* Only valid when ARM64_HAS_IRQ_PRIO_MASKING is enabled. */ 174 u64 pmr_save; 175 u64 stackframe[2]; 176 }; 177 178 static inline bool in_syscall(struct pt_regs const *regs) 179 { 180 return regs->syscallno != NO_SYSCALL; 181 } 182 183 static inline void forget_syscall(struct pt_regs *regs) 184 { 185 regs->syscallno = NO_SYSCALL; 186 } 187 188 #define MAX_REG_OFFSET offsetof(struct pt_regs, pstate) 189 190 #define arch_has_single_step() (1) 191 192 #ifdef CONFIG_COMPAT 193 #define compat_thumb_mode(regs) \ 194 (((regs)->pstate & PSR_AA32_T_BIT)) 195 #else 196 #define compat_thumb_mode(regs) (0) 197 #endif 198 199 #define user_mode(regs) \ 200 (((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t) 201 202 #define compat_user_mode(regs) \ 203 (((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \ 204 (PSR_MODE32_BIT | PSR_MODE_EL0t)) 205 206 #define processor_mode(regs) \ 207 ((regs)->pstate & PSR_MODE_MASK) 208 209 #define irqs_priority_unmasked(regs) \ 210 (system_uses_irq_prio_masking() ? \ 211 (regs)->pmr_save == GIC_PRIO_IRQON : \ 212 true) 213 214 #define interrupts_enabled(regs) \ 215 (!((regs)->pstate & PSR_I_BIT) && irqs_priority_unmasked(regs)) 216 217 #define fast_interrupts_enabled(regs) \ 218 (!((regs)->pstate & PSR_F_BIT)) 219 220 #define GET_USP(regs) \ 221 (!compat_user_mode(regs) ? (regs)->sp : (regs)->compat_sp) 222 223 #define SET_USP(ptregs, value) \ 224 (!compat_user_mode(regs) ? ((regs)->sp = value) : ((regs)->compat_sp = value)) 225 226 extern int regs_query_register_offset(const char *name); 227 extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, 228 unsigned int n); 229 230 /** 231 * regs_get_register() - get register value from its offset 232 * @regs: pt_regs from which register value is gotten 233 * @offset: offset of the register. 234 * 235 * regs_get_register returns the value of a register whose offset from @regs. 236 * The @offset is the offset of the register in struct pt_regs. 237 * If @offset is bigger than MAX_REG_OFFSET, this returns 0. 238 */ 239 static inline u64 regs_get_register(struct pt_regs *regs, unsigned int offset) 240 { 241 u64 val = 0; 242 243 WARN_ON(offset & 7); 244 245 offset >>= 3; 246 switch (offset) { 247 case 0 ... 30: 248 val = regs->regs[offset]; 249 break; 250 case offsetof(struct pt_regs, sp) >> 3: 251 val = regs->sp; 252 break; 253 case offsetof(struct pt_regs, pc) >> 3: 254 val = regs->pc; 255 break; 256 case offsetof(struct pt_regs, pstate) >> 3: 257 val = regs->pstate; 258 break; 259 default: 260 val = 0; 261 } 262 263 return val; 264 } 265 266 /* 267 * Read a register given an architectural register index r. 268 * This handles the common case where 31 means XZR, not SP. 269 */ 270 static inline unsigned long pt_regs_read_reg(const struct pt_regs *regs, int r) 271 { 272 return (r == 31) ? 0 : regs->regs[r]; 273 } 274 275 /* 276 * Write a register given an architectural register index r. 277 * This handles the common case where 31 means XZR, not SP. 278 */ 279 static inline void pt_regs_write_reg(struct pt_regs *regs, int r, 280 unsigned long val) 281 { 282 if (r != 31) 283 regs->regs[r] = val; 284 } 285 286 /* Valid only for Kernel mode traps. */ 287 static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) 288 { 289 return regs->sp; 290 } 291 292 static inline unsigned long regs_return_value(struct pt_regs *regs) 293 { 294 return regs->regs[0]; 295 } 296 297 /** 298 * regs_get_kernel_argument() - get Nth function argument in kernel 299 * @regs: pt_regs of that context 300 * @n: function argument number (start from 0) 301 * 302 * regs_get_argument() returns @n th argument of the function call. 303 * 304 * Note that this chooses the most likely register mapping. In very rare 305 * cases this may not return correct data, for example, if one of the 306 * function parameters is 16 bytes or bigger. In such cases, we cannot 307 * get access the parameter correctly and the register assignment of 308 * subsequent parameters will be shifted. 309 */ 310 static inline unsigned long regs_get_kernel_argument(struct pt_regs *regs, 311 unsigned int n) 312 { 313 #define NR_REG_ARGUMENTS 8 314 if (n < NR_REG_ARGUMENTS) 315 return pt_regs_read_reg(regs, n); 316 return 0; 317 } 318 319 /* We must avoid circular header include via sched.h */ 320 struct task_struct; 321 int valid_user_regs(struct user_pt_regs *regs, struct task_struct *task); 322 323 #define GET_IP(regs) ((unsigned long)(regs)->pc) 324 #define SET_IP(regs, value) ((regs)->pc = ((u64) (value))) 325 326 #define GET_FP(ptregs) ((unsigned long)(ptregs)->regs[29]) 327 #define SET_FP(ptregs, value) ((ptregs)->regs[29] = ((u64) (value))) 328 329 #include <asm-generic/ptrace.h> 330 331 #define procedure_link_pointer(regs) ((regs)->regs[30]) 332 333 static inline void procedure_link_pointer_set(struct pt_regs *regs, 334 unsigned long val) 335 { 336 procedure_link_pointer(regs) = val; 337 } 338 339 #undef profile_pc 340 extern unsigned long profile_pc(struct pt_regs *regs); 341 342 #endif /* __ASSEMBLY__ */ 343 #endif 344