1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Macros for accessing system registers with older binutils. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 9 #ifndef __ASM_SYSREG_H 10 #define __ASM_SYSREG_H 11 12 #include <linux/bits.h> 13 #include <linux/stringify.h> 14 15 /* 16 * ARMv8 ARM reserves the following encoding for system registers: 17 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", 18 * C5.2, version:ARM DDI 0487A.f) 19 * [20-19] : Op0 20 * [18-16] : Op1 21 * [15-12] : CRn 22 * [11-8] : CRm 23 * [7-5] : Op2 24 */ 25 #define Op0_shift 19 26 #define Op0_mask 0x3 27 #define Op1_shift 16 28 #define Op1_mask 0x7 29 #define CRn_shift 12 30 #define CRn_mask 0xf 31 #define CRm_shift 8 32 #define CRm_mask 0xf 33 #define Op2_shift 5 34 #define Op2_mask 0x7 35 36 #define sys_reg(op0, op1, crn, crm, op2) \ 37 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ 38 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ 39 ((op2) << Op2_shift)) 40 41 #define sys_insn sys_reg 42 43 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask) 44 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask) 45 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask) 46 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask) 47 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask) 48 49 #ifndef CONFIG_BROKEN_GAS_INST 50 51 #ifdef __ASSEMBLY__ 52 #define __emit_inst(x) .inst (x) 53 #else 54 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t" 55 #endif 56 57 #else /* CONFIG_BROKEN_GAS_INST */ 58 59 #ifndef CONFIG_CPU_BIG_ENDIAN 60 #define __INSTR_BSWAP(x) (x) 61 #else /* CONFIG_CPU_BIG_ENDIAN */ 62 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ 63 (((x) << 8) & 0x00ff0000) | \ 64 (((x) >> 8) & 0x0000ff00) | \ 65 (((x) >> 24) & 0x000000ff)) 66 #endif /* CONFIG_CPU_BIG_ENDIAN */ 67 68 #ifdef __ASSEMBLY__ 69 #define __emit_inst(x) .long __INSTR_BSWAP(x) 70 #else /* __ASSEMBLY__ */ 71 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" 72 #endif /* __ASSEMBLY__ */ 73 74 #endif /* CONFIG_BROKEN_GAS_INST */ 75 76 /* 77 * Instructions for modifying PSTATE fields. 78 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints, 79 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions 80 * for accessing PSTATE fields have the following encoding: 81 * Op0 = 0, CRn = 4 82 * Op1, Op2 encodes the PSTATE field modified and defines the constraints. 83 * CRm = Imm4 for the instruction. 84 * Rt = 0x1f 85 */ 86 #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) 87 #define PSTATE_Imm_shift CRm_shift 88 89 #define PSTATE_PAN pstate_field(0, 4) 90 #define PSTATE_UAO pstate_field(0, 3) 91 #define PSTATE_SSBS pstate_field(3, 1) 92 93 #define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift)) 94 #define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift)) 95 #define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift)) 96 97 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \ 98 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f)) 99 100 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31) 101 102 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) 103 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) 104 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) 105 106 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) 107 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0) 108 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2) 109 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2) 110 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2) 111 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) 112 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) 113 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) 114 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) 115 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) 116 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4) 117 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) 118 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) 119 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) 120 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) 121 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6) 122 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6) 123 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0) 124 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0) 125 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0) 126 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0) 127 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) 128 129 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) 130 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) 131 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) 132 133 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0) 134 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1) 135 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) 136 #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) 137 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4) 138 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) 139 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) 140 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) 141 142 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) 143 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) 144 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2) 145 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) 146 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) 147 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) 148 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) 149 #define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7) 150 151 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) 152 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) 153 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) 154 155 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) 156 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) 157 #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4) 158 159 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) 160 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) 161 162 #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) 163 #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) 164 165 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) 166 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) 167 168 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) 169 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) 170 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) 171 172 #define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0) 173 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) 174 #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2) 175 176 #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) 177 178 #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) 179 #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) 180 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) 181 182 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) 183 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1) 184 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2) 185 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3) 186 187 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0) 188 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1) 189 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2) 190 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3) 191 192 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0) 193 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1) 194 195 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0) 196 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1) 197 198 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 199 200 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) 201 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1) 202 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0) 203 204 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0) 205 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1) 206 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0) 207 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1) 208 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2) 209 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3) 210 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0) 211 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1) 212 213 #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0) 214 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0) 215 216 #define SYS_PAR_EL1_F BIT(0) 217 #define SYS_PAR_EL1_FST GENMASK(6, 1) 218 219 /*** Statistical Profiling Extension ***/ 220 /* ID registers */ 221 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) 222 #define SYS_PMSIDR_EL1_FE_SHIFT 0 223 #define SYS_PMSIDR_EL1_FT_SHIFT 1 224 #define SYS_PMSIDR_EL1_FL_SHIFT 2 225 #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3 226 #define SYS_PMSIDR_EL1_LDS_SHIFT 4 227 #define SYS_PMSIDR_EL1_ERND_SHIFT 5 228 #define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8 229 #define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL 230 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12 231 #define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL 232 #define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16 233 #define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL 234 235 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) 236 #define SYS_PMBIDR_EL1_ALIGN_SHIFT 0 237 #define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU 238 #define SYS_PMBIDR_EL1_P_SHIFT 4 239 #define SYS_PMBIDR_EL1_F_SHIFT 5 240 241 /* Sampling controls */ 242 #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) 243 #define SYS_PMSCR_EL1_E0SPE_SHIFT 0 244 #define SYS_PMSCR_EL1_E1SPE_SHIFT 1 245 #define SYS_PMSCR_EL1_CX_SHIFT 3 246 #define SYS_PMSCR_EL1_PA_SHIFT 4 247 #define SYS_PMSCR_EL1_TS_SHIFT 5 248 #define SYS_PMSCR_EL1_PCT_SHIFT 6 249 250 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) 251 #define SYS_PMSCR_EL2_E0HSPE_SHIFT 0 252 #define SYS_PMSCR_EL2_E2SPE_SHIFT 1 253 #define SYS_PMSCR_EL2_CX_SHIFT 3 254 #define SYS_PMSCR_EL2_PA_SHIFT 4 255 #define SYS_PMSCR_EL2_TS_SHIFT 5 256 #define SYS_PMSCR_EL2_PCT_SHIFT 6 257 258 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) 259 260 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) 261 #define SYS_PMSIRR_EL1_RND_SHIFT 0 262 #define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8 263 #define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL 264 265 /* Filtering controls */ 266 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) 267 #define SYS_PMSFCR_EL1_FE_SHIFT 0 268 #define SYS_PMSFCR_EL1_FT_SHIFT 1 269 #define SYS_PMSFCR_EL1_FL_SHIFT 2 270 #define SYS_PMSFCR_EL1_B_SHIFT 16 271 #define SYS_PMSFCR_EL1_LD_SHIFT 17 272 #define SYS_PMSFCR_EL1_ST_SHIFT 18 273 274 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) 275 #define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL 276 277 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) 278 #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 279 280 /* Buffer controls */ 281 #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) 282 #define SYS_PMBLIMITR_EL1_E_SHIFT 0 283 #define SYS_PMBLIMITR_EL1_FM_SHIFT 1 284 #define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL 285 #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT) 286 287 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) 288 289 /* Buffer error reporting */ 290 #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) 291 #define SYS_PMBSR_EL1_COLL_SHIFT 16 292 #define SYS_PMBSR_EL1_S_SHIFT 17 293 #define SYS_PMBSR_EL1_EA_SHIFT 18 294 #define SYS_PMBSR_EL1_DL_SHIFT 19 295 #define SYS_PMBSR_EL1_EC_SHIFT 26 296 #define SYS_PMBSR_EL1_EC_MASK 0x3fUL 297 298 #define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT) 299 #define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT) 300 #define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT) 301 302 #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0 303 #define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL 304 305 #define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0 306 #define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL 307 308 #define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT) 309 310 /*** End of Statistical Profiling Extension ***/ 311 312 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) 313 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) 314 315 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) 316 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) 317 318 #define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0) 319 #define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1) 320 #define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2) 321 #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) 322 #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) 323 324 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) 325 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1) 326 327 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0) 328 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1) 329 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2) 330 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) 331 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) 332 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0) 333 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1) 334 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2) 335 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3) 336 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) 337 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0) 338 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1) 339 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2) 340 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3) 341 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) 342 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3) 343 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) 344 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6) 345 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7) 346 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 347 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 348 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2) 349 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) 350 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) 351 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) 352 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) 353 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 354 355 #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1) 356 #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4) 357 358 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) 359 360 #define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0) 361 #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1) 362 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) 363 364 #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0) 365 366 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) 367 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) 368 369 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) 370 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1) 371 372 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0) 373 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1) 374 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) 375 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3) 376 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4) 377 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5) 378 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6) 379 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) 380 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0) 381 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1) 382 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2) 383 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0) 384 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3) 385 386 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2) 387 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) 388 389 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) 390 391 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) 392 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) 393 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2) 394 395 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1) 396 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2) 397 398 #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0) 399 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1) 400 #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0) 401 402 #define __PMEV_op2(n) ((n) & 0x7) 403 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) 404 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) 405 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) 406 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) 407 408 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7) 409 410 #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0) 411 #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) 412 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) 413 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) 414 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) 415 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0) 416 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3) 417 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) 418 #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0) 419 420 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1) 421 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) 422 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) 423 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) 424 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2) 425 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3) 426 427 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) 428 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0) 429 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1) 430 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2) 431 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3) 432 433 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) 434 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) 435 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0) 436 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1) 437 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) 438 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) 439 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5) 440 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) 441 442 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x) 443 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0) 444 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1) 445 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2) 446 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3) 447 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4) 448 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5) 449 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6) 450 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7) 451 452 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x) 453 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0) 454 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1) 455 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2) 456 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3) 457 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4) 458 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5) 459 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) 460 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) 461 462 /* VHE encodings for architectural EL0/1 system registers */ 463 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0) 464 #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2) 465 #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0) 466 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0) 467 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1) 468 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2) 469 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0) 470 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1) 471 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0) 472 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1) 473 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0) 474 #define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0) 475 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0) 476 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0) 477 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0) 478 #define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1) 479 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0) 480 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0) 481 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1) 482 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2) 483 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0) 484 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1) 485 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2) 486 487 /* Common SCTLR_ELx flags. */ 488 #define SCTLR_ELx_DSSBS (BIT(44)) 489 #define SCTLR_ELx_ENIA (BIT(31)) 490 #define SCTLR_ELx_ENIB (BIT(30)) 491 #define SCTLR_ELx_ENDA (BIT(27)) 492 #define SCTLR_ELx_EE (BIT(25)) 493 #define SCTLR_ELx_IESB (BIT(21)) 494 #define SCTLR_ELx_WXN (BIT(19)) 495 #define SCTLR_ELx_ENDB (BIT(13)) 496 #define SCTLR_ELx_I (BIT(12)) 497 #define SCTLR_ELx_SA (BIT(3)) 498 #define SCTLR_ELx_C (BIT(2)) 499 #define SCTLR_ELx_A (BIT(1)) 500 #define SCTLR_ELx_M (BIT(0)) 501 502 #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \ 503 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB) 504 505 /* SCTLR_EL2 specific flags. */ 506 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \ 507 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \ 508 (BIT(29))) 509 510 #ifdef CONFIG_CPU_BIG_ENDIAN 511 #define ENDIAN_SET_EL2 SCTLR_ELx_EE 512 #else 513 #define ENDIAN_SET_EL2 0 514 #endif 515 516 /* SCTLR_EL1 specific flags. */ 517 #define SCTLR_EL1_UCI (BIT(26)) 518 #define SCTLR_EL1_E0E (BIT(24)) 519 #define SCTLR_EL1_SPAN (BIT(23)) 520 #define SCTLR_EL1_NTWE (BIT(18)) 521 #define SCTLR_EL1_NTWI (BIT(16)) 522 #define SCTLR_EL1_UCT (BIT(15)) 523 #define SCTLR_EL1_DZE (BIT(14)) 524 #define SCTLR_EL1_UMA (BIT(9)) 525 #define SCTLR_EL1_SED (BIT(8)) 526 #define SCTLR_EL1_ITD (BIT(7)) 527 #define SCTLR_EL1_CP15BEN (BIT(5)) 528 #define SCTLR_EL1_SA0 (BIT(4)) 529 530 #define SCTLR_EL1_RES1 ((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \ 531 (BIT(29))) 532 533 #ifdef CONFIG_CPU_BIG_ENDIAN 534 #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) 535 #else 536 #define ENDIAN_SET_EL1 0 537 #endif 538 539 #define SCTLR_EL1_SET (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA |\ 540 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I |\ 541 SCTLR_EL1_DZE | SCTLR_EL1_UCT |\ 542 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN |\ 543 ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_RES1) 544 545 /* MAIR_ELx memory attributes (used by Linux) */ 546 #define MAIR_ATTR_DEVICE_nGnRnE UL(0x00) 547 #define MAIR_ATTR_DEVICE_nGnRE UL(0x04) 548 #define MAIR_ATTR_DEVICE_GRE UL(0x0c) 549 #define MAIR_ATTR_NORMAL_NC UL(0x44) 550 #define MAIR_ATTR_NORMAL_WT UL(0xbb) 551 #define MAIR_ATTR_NORMAL UL(0xff) 552 #define MAIR_ATTR_MASK UL(0xff) 553 554 /* Position the attr at the correct index */ 555 #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) 556 557 /* id_aa64isar0 */ 558 #define ID_AA64ISAR0_RNDR_SHIFT 60 559 #define ID_AA64ISAR0_TS_SHIFT 52 560 #define ID_AA64ISAR0_FHM_SHIFT 48 561 #define ID_AA64ISAR0_DP_SHIFT 44 562 #define ID_AA64ISAR0_SM4_SHIFT 40 563 #define ID_AA64ISAR0_SM3_SHIFT 36 564 #define ID_AA64ISAR0_SHA3_SHIFT 32 565 #define ID_AA64ISAR0_RDM_SHIFT 28 566 #define ID_AA64ISAR0_ATOMICS_SHIFT 20 567 #define ID_AA64ISAR0_CRC32_SHIFT 16 568 #define ID_AA64ISAR0_SHA2_SHIFT 12 569 #define ID_AA64ISAR0_SHA1_SHIFT 8 570 #define ID_AA64ISAR0_AES_SHIFT 4 571 572 /* id_aa64isar1 */ 573 #define ID_AA64ISAR1_I8MM_SHIFT 52 574 #define ID_AA64ISAR1_DGH_SHIFT 48 575 #define ID_AA64ISAR1_BF16_SHIFT 44 576 #define ID_AA64ISAR1_SPECRES_SHIFT 40 577 #define ID_AA64ISAR1_SB_SHIFT 36 578 #define ID_AA64ISAR1_FRINTTS_SHIFT 32 579 #define ID_AA64ISAR1_GPI_SHIFT 28 580 #define ID_AA64ISAR1_GPA_SHIFT 24 581 #define ID_AA64ISAR1_LRCPC_SHIFT 20 582 #define ID_AA64ISAR1_FCMA_SHIFT 16 583 #define ID_AA64ISAR1_JSCVT_SHIFT 12 584 #define ID_AA64ISAR1_API_SHIFT 8 585 #define ID_AA64ISAR1_APA_SHIFT 4 586 #define ID_AA64ISAR1_DPB_SHIFT 0 587 588 #define ID_AA64ISAR1_APA_NI 0x0 589 #define ID_AA64ISAR1_APA_ARCHITECTED 0x1 590 #define ID_AA64ISAR1_API_NI 0x0 591 #define ID_AA64ISAR1_API_IMP_DEF 0x1 592 #define ID_AA64ISAR1_GPA_NI 0x0 593 #define ID_AA64ISAR1_GPA_ARCHITECTED 0x1 594 #define ID_AA64ISAR1_GPI_NI 0x0 595 #define ID_AA64ISAR1_GPI_IMP_DEF 0x1 596 597 /* id_aa64pfr0 */ 598 #define ID_AA64PFR0_CSV3_SHIFT 60 599 #define ID_AA64PFR0_CSV2_SHIFT 56 600 #define ID_AA64PFR0_DIT_SHIFT 48 601 #define ID_AA64PFR0_SVE_SHIFT 32 602 #define ID_AA64PFR0_RAS_SHIFT 28 603 #define ID_AA64PFR0_GIC_SHIFT 24 604 #define ID_AA64PFR0_ASIMD_SHIFT 20 605 #define ID_AA64PFR0_FP_SHIFT 16 606 #define ID_AA64PFR0_EL3_SHIFT 12 607 #define ID_AA64PFR0_EL2_SHIFT 8 608 #define ID_AA64PFR0_EL1_SHIFT 4 609 #define ID_AA64PFR0_EL0_SHIFT 0 610 611 #define ID_AA64PFR0_SVE 0x1 612 #define ID_AA64PFR0_RAS_V1 0x1 613 #define ID_AA64PFR0_FP_NI 0xf 614 #define ID_AA64PFR0_FP_SUPPORTED 0x0 615 #define ID_AA64PFR0_ASIMD_NI 0xf 616 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0 617 #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1 618 #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1 619 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2 620 621 /* id_aa64pfr1 */ 622 #define ID_AA64PFR1_SSBS_SHIFT 4 623 624 #define ID_AA64PFR1_SSBS_PSTATE_NI 0 625 #define ID_AA64PFR1_SSBS_PSTATE_ONLY 1 626 #define ID_AA64PFR1_SSBS_PSTATE_INSNS 2 627 628 /* id_aa64zfr0 */ 629 #define ID_AA64ZFR0_F64MM_SHIFT 56 630 #define ID_AA64ZFR0_F32MM_SHIFT 52 631 #define ID_AA64ZFR0_I8MM_SHIFT 44 632 #define ID_AA64ZFR0_SM4_SHIFT 40 633 #define ID_AA64ZFR0_SHA3_SHIFT 32 634 #define ID_AA64ZFR0_BF16_SHIFT 20 635 #define ID_AA64ZFR0_BITPERM_SHIFT 16 636 #define ID_AA64ZFR0_AES_SHIFT 4 637 #define ID_AA64ZFR0_SVEVER_SHIFT 0 638 639 #define ID_AA64ZFR0_F64MM 0x1 640 #define ID_AA64ZFR0_F32MM 0x1 641 #define ID_AA64ZFR0_I8MM 0x1 642 #define ID_AA64ZFR0_BF16 0x1 643 #define ID_AA64ZFR0_SM4 0x1 644 #define ID_AA64ZFR0_SHA3 0x1 645 #define ID_AA64ZFR0_BITPERM 0x1 646 #define ID_AA64ZFR0_AES 0x1 647 #define ID_AA64ZFR0_AES_PMULL 0x2 648 #define ID_AA64ZFR0_SVEVER_SVE2 0x1 649 650 /* id_aa64mmfr0 */ 651 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 652 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 653 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 654 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16 655 #define ID_AA64MMFR0_SNSMEM_SHIFT 12 656 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8 657 #define ID_AA64MMFR0_ASID_SHIFT 4 658 #define ID_AA64MMFR0_PARANGE_SHIFT 0 659 660 #define ID_AA64MMFR0_TGRAN4_NI 0xf 661 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 662 #define ID_AA64MMFR0_TGRAN64_NI 0xf 663 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 664 #define ID_AA64MMFR0_TGRAN16_NI 0x0 665 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 666 #define ID_AA64MMFR0_PARANGE_48 0x5 667 #define ID_AA64MMFR0_PARANGE_52 0x6 668 669 #ifdef CONFIG_ARM64_PA_BITS_52 670 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_52 671 #else 672 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_48 673 #endif 674 675 /* id_aa64mmfr1 */ 676 #define ID_AA64MMFR1_PAN_SHIFT 20 677 #define ID_AA64MMFR1_LOR_SHIFT 16 678 #define ID_AA64MMFR1_HPD_SHIFT 12 679 #define ID_AA64MMFR1_VHE_SHIFT 8 680 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4 681 #define ID_AA64MMFR1_HADBS_SHIFT 0 682 683 #define ID_AA64MMFR1_VMIDBITS_8 0 684 #define ID_AA64MMFR1_VMIDBITS_16 2 685 686 /* id_aa64mmfr2 */ 687 #define ID_AA64MMFR2_E0PD_SHIFT 60 688 #define ID_AA64MMFR2_FWB_SHIFT 40 689 #define ID_AA64MMFR2_AT_SHIFT 32 690 #define ID_AA64MMFR2_LVA_SHIFT 16 691 #define ID_AA64MMFR2_IESB_SHIFT 12 692 #define ID_AA64MMFR2_LSM_SHIFT 8 693 #define ID_AA64MMFR2_UAO_SHIFT 4 694 #define ID_AA64MMFR2_CNP_SHIFT 0 695 696 /* id_aa64dfr0 */ 697 #define ID_AA64DFR0_PMSVER_SHIFT 32 698 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 699 #define ID_AA64DFR0_WRPS_SHIFT 20 700 #define ID_AA64DFR0_BRPS_SHIFT 12 701 #define ID_AA64DFR0_PMUVER_SHIFT 8 702 #define ID_AA64DFR0_TRACEVER_SHIFT 4 703 #define ID_AA64DFR0_DEBUGVER_SHIFT 0 704 705 #define ID_ISAR5_RDM_SHIFT 24 706 #define ID_ISAR5_CRC32_SHIFT 16 707 #define ID_ISAR5_SHA2_SHIFT 12 708 #define ID_ISAR5_SHA1_SHIFT 8 709 #define ID_ISAR5_AES_SHIFT 4 710 #define ID_ISAR5_SEVL_SHIFT 0 711 712 #define ID_ISAR6_I8MM_SHIFT 24 713 #define ID_ISAR6_BF16_SHIFT 20 714 #define ID_ISAR6_SPECRES_SHIFT 16 715 #define ID_ISAR6_SB_SHIFT 12 716 #define ID_ISAR6_FHM_SHIFT 8 717 #define ID_ISAR6_DP_SHIFT 4 718 #define ID_ISAR6_JSCVT_SHIFT 0 719 720 #define MVFR0_FPROUND_SHIFT 28 721 #define MVFR0_FPSHVEC_SHIFT 24 722 #define MVFR0_FPSQRT_SHIFT 20 723 #define MVFR0_FPDIVIDE_SHIFT 16 724 #define MVFR0_FPTRAP_SHIFT 12 725 #define MVFR0_FPDP_SHIFT 8 726 #define MVFR0_FPSP_SHIFT 4 727 #define MVFR0_SIMD_SHIFT 0 728 729 #define MVFR1_SIMDFMAC_SHIFT 28 730 #define MVFR1_FPHP_SHIFT 24 731 #define MVFR1_SIMDHP_SHIFT 20 732 #define MVFR1_SIMDSP_SHIFT 16 733 #define MVFR1_SIMDINT_SHIFT 12 734 #define MVFR1_SIMDLS_SHIFT 8 735 #define MVFR1_FPDNAN_SHIFT 4 736 #define MVFR1_FPFTZ_SHIFT 0 737 738 739 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 740 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 741 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 742 743 #define ID_AA64MMFR0_TGRAN4_NI 0xf 744 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 745 #define ID_AA64MMFR0_TGRAN64_NI 0xf 746 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 747 #define ID_AA64MMFR0_TGRAN16_NI 0x0 748 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 749 750 #if defined(CONFIG_ARM64_4K_PAGES) 751 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT 752 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED 753 #elif defined(CONFIG_ARM64_16K_PAGES) 754 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT 755 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED 756 #elif defined(CONFIG_ARM64_64K_PAGES) 757 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT 758 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED 759 #endif 760 761 762 /* 763 * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which 764 * are reserved by the SVE architecture for future expansion of the LEN 765 * field, with compatible semantics. 766 */ 767 #define ZCR_ELx_LEN_SHIFT 0 768 #define ZCR_ELx_LEN_SIZE 9 769 #define ZCR_ELx_LEN_MASK 0x1ff 770 771 #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */ 772 #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */ 773 #define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN) 774 775 776 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ 777 #define SYS_MPIDR_SAFE_VAL (BIT(31)) 778 779 #ifdef __ASSEMBLY__ 780 781 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 782 .equ .L__reg_num_x\num, \num 783 .endr 784 .equ .L__reg_num_xzr, 31 785 786 .macro mrs_s, rt, sreg 787 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt)) 788 .endm 789 790 .macro msr_s, sreg, rt 791 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt)) 792 .endm 793 794 #else 795 796 #include <linux/build_bug.h> 797 #include <linux/types.h> 798 799 #define __DEFINE_MRS_MSR_S_REGNUM \ 800 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \ 801 " .equ .L__reg_num_x\\num, \\num\n" \ 802 " .endr\n" \ 803 " .equ .L__reg_num_xzr, 31\n" 804 805 #define DEFINE_MRS_S \ 806 __DEFINE_MRS_MSR_S_REGNUM \ 807 " .macro mrs_s, rt, sreg\n" \ 808 __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt)) \ 809 " .endm\n" 810 811 #define DEFINE_MSR_S \ 812 __DEFINE_MRS_MSR_S_REGNUM \ 813 " .macro msr_s, sreg, rt\n" \ 814 __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt)) \ 815 " .endm\n" 816 817 #define UNDEFINE_MRS_S \ 818 " .purgem mrs_s\n" 819 820 #define UNDEFINE_MSR_S \ 821 " .purgem msr_s\n" 822 823 #define __mrs_s(v, r) \ 824 DEFINE_MRS_S \ 825 " mrs_s " v ", " __stringify(r) "\n" \ 826 UNDEFINE_MRS_S 827 828 #define __msr_s(r, v) \ 829 DEFINE_MSR_S \ 830 " msr_s " __stringify(r) ", " v "\n" \ 831 UNDEFINE_MSR_S 832 833 /* 834 * Unlike read_cpuid, calls to read_sysreg are never expected to be 835 * optimized away or replaced with synthetic values. 836 */ 837 #define read_sysreg(r) ({ \ 838 u64 __val; \ 839 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ 840 __val; \ 841 }) 842 843 /* 844 * The "Z" constraint normally means a zero immediate, but when combined with 845 * the "%x0" template means XZR. 846 */ 847 #define write_sysreg(v, r) do { \ 848 u64 __val = (u64)(v); \ 849 asm volatile("msr " __stringify(r) ", %x0" \ 850 : : "rZ" (__val)); \ 851 } while (0) 852 853 /* 854 * For registers without architectural names, or simply unsupported by 855 * GAS. 856 */ 857 #define read_sysreg_s(r) ({ \ 858 u64 __val; \ 859 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \ 860 __val; \ 861 }) 862 863 #define write_sysreg_s(v, r) do { \ 864 u64 __val = (u64)(v); \ 865 asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); \ 866 } while (0) 867 868 /* 869 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the 870 * set mask are set. Other bits are left as-is. 871 */ 872 #define sysreg_clear_set(sysreg, clear, set) do { \ 873 u64 __scs_val = read_sysreg(sysreg); \ 874 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 875 if (__scs_new != __scs_val) \ 876 write_sysreg(__scs_new, sysreg); \ 877 } while (0) 878 879 #endif 880 881 #endif /* __ASM_SYSREG_H */ 882