1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 79 #include <asm/cpu.h> 80 #include <asm/cpufeature.h> 81 #include <asm/cpu_ops.h> 82 #include <asm/fpsimd.h> 83 #include <asm/hwcap.h> 84 #include <asm/insn.h> 85 #include <asm/kvm_host.h> 86 #include <asm/mmu_context.h> 87 #include <asm/mte.h> 88 #include <asm/processor.h> 89 #include <asm/smp.h> 90 #include <asm/sysreg.h> 91 #include <asm/traps.h> 92 #include <asm/vectors.h> 93 #include <asm/virt.h> 94 95 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 96 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 97 98 #ifdef CONFIG_COMPAT 99 #define COMPAT_ELF_HWCAP_DEFAULT \ 100 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 101 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 102 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 103 COMPAT_HWCAP_LPAE) 104 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 105 unsigned int compat_elf_hwcap2 __read_mostly; 106 #endif 107 108 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 109 EXPORT_SYMBOL(system_cpucaps); 110 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 111 112 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 113 114 bool arm64_use_ng_mappings = false; 115 EXPORT_SYMBOL(arm64_use_ng_mappings); 116 117 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 118 119 /* 120 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 121 * support it? 122 */ 123 static bool __read_mostly allow_mismatched_32bit_el0; 124 125 /* 126 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 127 * seen at least one CPU capable of 32-bit EL0. 128 */ 129 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 130 131 /* 132 * Mask of CPUs supporting 32-bit EL0. 133 * Only valid if arm64_mismatched_32bit_el0 is enabled. 134 */ 135 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 136 137 void dump_cpu_features(void) 138 { 139 /* file-wide pr_fmt adds "CPU features: " prefix */ 140 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 141 } 142 143 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 144 .sys_reg = SYS_##reg, \ 145 .field_pos = reg##_##field##_SHIFT, \ 146 .field_width = reg##_##field##_WIDTH, \ 147 .sign = reg##_##field##_SIGNED, \ 148 .min_field_value = reg##_##field##_##min_value, 149 150 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 151 { \ 152 .sign = SIGNED, \ 153 .visible = VISIBLE, \ 154 .strict = STRICT, \ 155 .type = TYPE, \ 156 .shift = SHIFT, \ 157 .width = WIDTH, \ 158 .safe_val = SAFE_VAL, \ 159 } 160 161 /* Define a feature with unsigned values */ 162 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 163 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 164 165 /* Define a feature with a signed value */ 166 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 167 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 168 169 #define ARM64_FTR_END \ 170 { \ 171 .width = 0, \ 172 } 173 174 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 175 176 static bool __system_matches_cap(unsigned int n); 177 178 /* 179 * NOTE: Any changes to the visibility of features should be kept in 180 * sync with the documentation of the CPU feature register ABI. 181 */ 182 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 183 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 184 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 185 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 186 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 188 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 190 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 191 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 192 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 193 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 197 ARM64_FTR_END, 198 }; 199 200 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 204 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 206 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 207 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 208 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 209 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 210 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 211 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 212 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 213 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 214 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 215 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 217 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 219 ARM64_FTR_END, 220 }; 221 222 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 229 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 231 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 232 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 234 ARM64_FTR_END, 235 }; 236 237 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 238 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 243 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 245 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 248 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 249 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY), 253 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY), 254 ARM64_FTR_END, 255 }; 256 257 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 258 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 259 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 262 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 263 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 264 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 265 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 266 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 267 ARM64_FTR_END, 268 }; 269 270 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 271 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 272 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 273 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 274 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 275 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 276 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 277 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 278 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 279 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 280 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 281 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 282 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 283 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 284 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 285 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 286 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 287 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 288 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 289 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 290 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 291 ARM64_FTR_END, 292 }; 293 294 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 295 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 296 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 297 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 298 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 299 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 300 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 301 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 302 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 303 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 304 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 305 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 306 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 307 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 308 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 309 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 310 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 311 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 312 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 313 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 314 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 315 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 316 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 317 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 318 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 319 ARM64_FTR_END, 320 }; 321 322 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 323 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 324 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 325 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 326 /* 327 * Page size not being supported at Stage-2 is not fatal. You 328 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 329 * your favourite nesting hypervisor. 330 * 331 * There is a small corner case where the hypervisor explicitly 332 * advertises a given granule size at Stage-2 (value 2) on some 333 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 334 * vCPUs. Although this is not forbidden by the architecture, it 335 * indicates that the hypervisor is being silly (or buggy). 336 * 337 * We make no effort to cope with this and pretend that if these 338 * fields are inconsistent across vCPUs, then it isn't worth 339 * trying to bring KVM up. 340 */ 341 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 342 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 343 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 344 /* 345 * We already refuse to boot CPUs that don't support our configured 346 * page size, so we can only detect mismatches for a page size other 347 * than the one we're currently using. Unfortunately, SoCs like this 348 * exist in the wild so, even though we don't like it, we'll have to go 349 * along with it and treat them as non-strict. 350 */ 351 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 352 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 354 355 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 356 /* Linux shouldn't care about secure memory */ 357 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 358 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 359 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 360 /* 361 * Differing PARange is fine as long as all peripherals and memory are mapped 362 * within the minimum PARange of all CPUs 363 */ 364 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 365 ARM64_FTR_END, 366 }; 367 368 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 369 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 370 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 371 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 372 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 373 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 374 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 375 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 376 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 377 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 378 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 379 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 380 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 381 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 382 ARM64_FTR_END, 383 }; 384 385 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 386 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 387 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 389 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 390 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 391 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 392 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 393 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 394 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 395 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 396 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 397 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 398 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 399 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 400 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 401 ARM64_FTR_END, 402 }; 403 404 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 405 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 406 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 407 ARM64_FTR_END, 408 }; 409 410 static const struct arm64_ftr_bits ftr_ctr[] = { 411 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 412 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 413 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 414 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 415 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 416 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 417 /* 418 * Linux can handle differing I-cache policies. Userspace JITs will 419 * make use of *minLine. 420 * If we have differing I-cache policies, report it as the weakest - VIPT. 421 */ 422 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 423 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 424 ARM64_FTR_END, 425 }; 426 427 static struct arm64_ftr_override __ro_after_init no_override = { }; 428 429 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 430 .name = "SYS_CTR_EL0", 431 .ftr_bits = ftr_ctr, 432 .override = &no_override, 433 }; 434 435 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 436 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 441 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 444 ARM64_FTR_END, 445 }; 446 447 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 448 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 449 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 453 /* 454 * We can instantiate multiple PMU instances with different levels 455 * of support. 456 */ 457 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 459 ARM64_FTR_END, 460 }; 461 462 static const struct arm64_ftr_bits ftr_mvfr0[] = { 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 468 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 471 ARM64_FTR_END, 472 }; 473 474 static const struct arm64_ftr_bits ftr_mvfr1[] = { 475 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 478 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 480 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 483 ARM64_FTR_END, 484 }; 485 486 static const struct arm64_ftr_bits ftr_mvfr2[] = { 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 489 ARM64_FTR_END, 490 }; 491 492 static const struct arm64_ftr_bits ftr_dczid[] = { 493 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 494 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 495 ARM64_FTR_END, 496 }; 497 498 static const struct arm64_ftr_bits ftr_gmid[] = { 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 500 ARM64_FTR_END, 501 }; 502 503 static const struct arm64_ftr_bits ftr_id_isar0[] = { 504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 505 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 507 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 511 ARM64_FTR_END, 512 }; 513 514 static const struct arm64_ftr_bits ftr_id_isar5[] = { 515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 516 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 517 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 518 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 519 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 520 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 521 ARM64_FTR_END, 522 }; 523 524 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 525 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 532 533 /* 534 * SpecSEI = 1 indicates that the PE might generate an SError on an 535 * external abort on speculative read. It is safe to assume that an 536 * SError might be generated than it will not be. Hence it has been 537 * classified as FTR_HIGHER_SAFE. 538 */ 539 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 540 ARM64_FTR_END, 541 }; 542 543 static const struct arm64_ftr_bits ftr_id_isar4[] = { 544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 546 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 547 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 548 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 549 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 550 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 551 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 552 ARM64_FTR_END, 553 }; 554 555 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 557 ARM64_FTR_END, 558 }; 559 560 static const struct arm64_ftr_bits ftr_id_isar6[] = { 561 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 562 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 563 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 564 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 565 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 566 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 567 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 568 ARM64_FTR_END, 569 }; 570 571 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 572 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 573 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 575 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 576 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 577 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 578 ARM64_FTR_END, 579 }; 580 581 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 582 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 583 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 584 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 585 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 586 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 587 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 588 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 589 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 590 ARM64_FTR_END, 591 }; 592 593 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 594 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 595 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 596 ARM64_FTR_END, 597 }; 598 599 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 600 /* [31:28] TraceFilt */ 601 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 602 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 603 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 604 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 605 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 606 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 607 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 608 ARM64_FTR_END, 609 }; 610 611 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 612 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 613 ARM64_FTR_END, 614 }; 615 616 /* 617 * Common ftr bits for a 32bit register with all hidden, strict 618 * attributes, with 4bit feature fields and a default safe value of 619 * 0. Covers the following 32bit registers: 620 * id_isar[1-3], id_mmfr[1-3] 621 */ 622 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 623 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 624 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 625 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 626 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 627 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 628 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 629 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 630 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 631 ARM64_FTR_END, 632 }; 633 634 /* Table for a single 32bit feature value */ 635 static const struct arm64_ftr_bits ftr_single32[] = { 636 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 637 ARM64_FTR_END, 638 }; 639 640 static const struct arm64_ftr_bits ftr_raz[] = { 641 ARM64_FTR_END, 642 }; 643 644 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 645 .sys_id = id, \ 646 .reg = &(struct arm64_ftr_reg){ \ 647 .name = id_str, \ 648 .override = (ovr), \ 649 .ftr_bits = &((table)[0]), \ 650 }} 651 652 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 653 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 654 655 #define ARM64_FTR_REG(id, table) \ 656 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 657 658 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override; 659 struct arm64_ftr_override __ro_after_init id_aa64pfr0_override; 660 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override; 661 struct arm64_ftr_override __ro_after_init id_aa64zfr0_override; 662 struct arm64_ftr_override __ro_after_init id_aa64smfr0_override; 663 struct arm64_ftr_override __ro_after_init id_aa64isar1_override; 664 struct arm64_ftr_override __ro_after_init id_aa64isar2_override; 665 666 struct arm64_ftr_override arm64_sw_feature_override; 667 668 static const struct __ftr_reg_entry { 669 u32 sys_id; 670 struct arm64_ftr_reg *reg; 671 } arm64_ftr_regs[] = { 672 673 /* Op1 = 0, CRn = 0, CRm = 1 */ 674 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 675 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 676 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 677 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 678 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 679 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 680 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 681 682 /* Op1 = 0, CRn = 0, CRm = 2 */ 683 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 684 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 685 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 686 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 687 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 688 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 689 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 690 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 691 692 /* Op1 = 0, CRn = 0, CRm = 3 */ 693 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 694 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 695 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 696 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 697 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 698 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 699 700 /* Op1 = 0, CRn = 0, CRm = 4 */ 701 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 702 &id_aa64pfr0_override), 703 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 704 &id_aa64pfr1_override), 705 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 706 &id_aa64zfr0_override), 707 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 708 &id_aa64smfr0_override), 709 710 /* Op1 = 0, CRn = 0, CRm = 5 */ 711 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 712 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 713 714 /* Op1 = 0, CRn = 0, CRm = 6 */ 715 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 716 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 717 &id_aa64isar1_override), 718 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 719 &id_aa64isar2_override), 720 721 /* Op1 = 0, CRn = 0, CRm = 7 */ 722 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 723 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 724 &id_aa64mmfr1_override), 725 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 726 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 727 728 /* Op1 = 1, CRn = 0, CRm = 0 */ 729 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 730 731 /* Op1 = 3, CRn = 0, CRm = 0 */ 732 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 733 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 734 735 /* Op1 = 3, CRn = 14, CRm = 0 */ 736 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 737 }; 738 739 static int search_cmp_ftr_reg(const void *id, const void *regp) 740 { 741 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 742 } 743 744 /* 745 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 746 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 747 * ascending order of sys_id, we use binary search to find a matching 748 * entry. 749 * 750 * returns - Upon success, matching ftr_reg entry for id. 751 * - NULL on failure. It is upto the caller to decide 752 * the impact of a failure. 753 */ 754 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 755 { 756 const struct __ftr_reg_entry *ret; 757 758 ret = bsearch((const void *)(unsigned long)sys_id, 759 arm64_ftr_regs, 760 ARRAY_SIZE(arm64_ftr_regs), 761 sizeof(arm64_ftr_regs[0]), 762 search_cmp_ftr_reg); 763 if (ret) 764 return ret->reg; 765 return NULL; 766 } 767 768 /* 769 * get_arm64_ftr_reg - Looks up a feature register entry using 770 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 771 * 772 * returns - Upon success, matching ftr_reg entry for id. 773 * - NULL on failure but with an WARN_ON(). 774 */ 775 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 776 { 777 struct arm64_ftr_reg *reg; 778 779 reg = get_arm64_ftr_reg_nowarn(sys_id); 780 781 /* 782 * Requesting a non-existent register search is an error. Warn 783 * and let the caller handle it. 784 */ 785 WARN_ON(!reg); 786 return reg; 787 } 788 789 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 790 s64 ftr_val) 791 { 792 u64 mask = arm64_ftr_mask(ftrp); 793 794 reg &= ~mask; 795 reg |= (ftr_val << ftrp->shift) & mask; 796 return reg; 797 } 798 799 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 800 s64 cur) 801 { 802 s64 ret = 0; 803 804 switch (ftrp->type) { 805 case FTR_EXACT: 806 ret = ftrp->safe_val; 807 break; 808 case FTR_LOWER_SAFE: 809 ret = min(new, cur); 810 break; 811 case FTR_HIGHER_OR_ZERO_SAFE: 812 if (!cur || !new) 813 break; 814 fallthrough; 815 case FTR_HIGHER_SAFE: 816 ret = max(new, cur); 817 break; 818 default: 819 BUG(); 820 } 821 822 return ret; 823 } 824 825 static void __init sort_ftr_regs(void) 826 { 827 unsigned int i; 828 829 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 830 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 831 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 832 unsigned int j = 0; 833 834 /* 835 * Features here must be sorted in descending order with respect 836 * to their shift values and should not overlap with each other. 837 */ 838 for (; ftr_bits->width != 0; ftr_bits++, j++) { 839 unsigned int width = ftr_reg->ftr_bits[j].width; 840 unsigned int shift = ftr_reg->ftr_bits[j].shift; 841 unsigned int prev_shift; 842 843 WARN((shift + width) > 64, 844 "%s has invalid feature at shift %d\n", 845 ftr_reg->name, shift); 846 847 /* 848 * Skip the first feature. There is nothing to 849 * compare against for now. 850 */ 851 if (j == 0) 852 continue; 853 854 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 855 WARN((shift + width) > prev_shift, 856 "%s has feature overlap at shift %d\n", 857 ftr_reg->name, shift); 858 } 859 860 /* 861 * Skip the first register. There is nothing to 862 * compare against for now. 863 */ 864 if (i == 0) 865 continue; 866 /* 867 * Registers here must be sorted in ascending order with respect 868 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 869 * to work correctly. 870 */ 871 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 872 } 873 } 874 875 /* 876 * Initialise the CPU feature register from Boot CPU values. 877 * Also initiliases the strict_mask for the register. 878 * Any bits that are not covered by an arm64_ftr_bits entry are considered 879 * RES0 for the system-wide value, and must strictly match. 880 */ 881 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 882 { 883 u64 val = 0; 884 u64 strict_mask = ~0x0ULL; 885 u64 user_mask = 0; 886 u64 valid_mask = 0; 887 888 const struct arm64_ftr_bits *ftrp; 889 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 890 891 if (!reg) 892 return; 893 894 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 895 u64 ftr_mask = arm64_ftr_mask(ftrp); 896 s64 ftr_new = arm64_ftr_value(ftrp, new); 897 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 898 899 if ((ftr_mask & reg->override->mask) == ftr_mask) { 900 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 901 char *str = NULL; 902 903 if (ftr_ovr != tmp) { 904 /* Unsafe, remove the override */ 905 reg->override->mask &= ~ftr_mask; 906 reg->override->val &= ~ftr_mask; 907 tmp = ftr_ovr; 908 str = "ignoring override"; 909 } else if (ftr_new != tmp) { 910 /* Override was valid */ 911 ftr_new = tmp; 912 str = "forced"; 913 } else if (ftr_ovr == tmp) { 914 /* Override was the safe value */ 915 str = "already set"; 916 } 917 918 if (str) 919 pr_warn("%s[%d:%d]: %s to %llx\n", 920 reg->name, 921 ftrp->shift + ftrp->width - 1, 922 ftrp->shift, str, tmp); 923 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 924 reg->override->val &= ~ftr_mask; 925 pr_warn("%s[%d:%d]: impossible override, ignored\n", 926 reg->name, 927 ftrp->shift + ftrp->width - 1, 928 ftrp->shift); 929 } 930 931 val = arm64_ftr_set_value(ftrp, val, ftr_new); 932 933 valid_mask |= ftr_mask; 934 if (!ftrp->strict) 935 strict_mask &= ~ftr_mask; 936 if (ftrp->visible) 937 user_mask |= ftr_mask; 938 else 939 reg->user_val = arm64_ftr_set_value(ftrp, 940 reg->user_val, 941 ftrp->safe_val); 942 } 943 944 val &= valid_mask; 945 946 reg->sys_val = val; 947 reg->strict_mask = strict_mask; 948 reg->user_mask = user_mask; 949 } 950 951 extern const struct arm64_cpu_capabilities arm64_errata[]; 952 static const struct arm64_cpu_capabilities arm64_features[]; 953 954 static void __init 955 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 956 { 957 for (; caps->matches; caps++) { 958 if (WARN(caps->capability >= ARM64_NCAPS, 959 "Invalid capability %d\n", caps->capability)) 960 continue; 961 if (WARN(cpucap_ptrs[caps->capability], 962 "Duplicate entry for capability %d\n", 963 caps->capability)) 964 continue; 965 cpucap_ptrs[caps->capability] = caps; 966 } 967 } 968 969 static void __init init_cpucap_indirect_list(void) 970 { 971 init_cpucap_indirect_list_from_array(arm64_features); 972 init_cpucap_indirect_list_from_array(arm64_errata); 973 } 974 975 static void __init setup_boot_cpu_capabilities(void); 976 977 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 978 { 979 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 980 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 981 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 982 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 983 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 984 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 985 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 986 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 987 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 988 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 989 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 990 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 991 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 992 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 993 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 994 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 995 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 996 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 997 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 998 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 999 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1000 } 1001 1002 #ifdef CONFIG_ARM64_PSEUDO_NMI 1003 static bool enable_pseudo_nmi; 1004 1005 static int __init early_enable_pseudo_nmi(char *p) 1006 { 1007 return kstrtobool(p, &enable_pseudo_nmi); 1008 } 1009 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1010 1011 static __init void detect_system_supports_pseudo_nmi(void) 1012 { 1013 struct device_node *np; 1014 1015 if (!enable_pseudo_nmi) 1016 return; 1017 1018 /* 1019 * Detect broken MediaTek firmware that doesn't properly save and 1020 * restore GIC priorities. 1021 */ 1022 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1023 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1024 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1025 enable_pseudo_nmi = false; 1026 } 1027 of_node_put(np); 1028 } 1029 #else /* CONFIG_ARM64_PSEUDO_NMI */ 1030 static inline void detect_system_supports_pseudo_nmi(void) { } 1031 #endif 1032 1033 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1034 { 1035 /* Before we start using the tables, make sure it is sorted */ 1036 sort_ftr_regs(); 1037 1038 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1039 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1040 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1041 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1042 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1043 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1044 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1045 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1046 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1047 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1048 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1049 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1050 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1051 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1052 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1053 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1054 1055 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1056 init_32bit_cpu_features(&info->aarch32); 1057 1058 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1059 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1060 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1061 1062 vec_init_vq_map(ARM64_VEC_SVE); 1063 1064 cpacr_restore(cpacr); 1065 } 1066 1067 if (IS_ENABLED(CONFIG_ARM64_SME) && 1068 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1069 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1070 1071 /* 1072 * We mask out SMPS since even if the hardware 1073 * supports priorities the kernel does not at present 1074 * and we block access to them. 1075 */ 1076 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1077 vec_init_vq_map(ARM64_VEC_SME); 1078 1079 cpacr_restore(cpacr); 1080 } 1081 1082 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1083 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1084 } 1085 1086 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1087 { 1088 const struct arm64_ftr_bits *ftrp; 1089 1090 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1091 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1092 s64 ftr_new = arm64_ftr_value(ftrp, new); 1093 1094 if (ftr_cur == ftr_new) 1095 continue; 1096 /* Find a safe value */ 1097 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1098 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1099 } 1100 1101 } 1102 1103 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1104 { 1105 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1106 1107 if (!regp) 1108 return 0; 1109 1110 update_cpu_ftr_reg(regp, val); 1111 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1112 return 0; 1113 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1114 regp->name, boot, cpu, val); 1115 return 1; 1116 } 1117 1118 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1119 { 1120 const struct arm64_ftr_bits *ftrp; 1121 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1122 1123 if (!regp) 1124 return; 1125 1126 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1127 if (ftrp->shift == field) { 1128 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1129 break; 1130 } 1131 } 1132 1133 /* Bogus field? */ 1134 WARN_ON(!ftrp->width); 1135 } 1136 1137 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1138 struct cpuinfo_arm64 *boot) 1139 { 1140 static bool boot_cpu_32bit_regs_overridden = false; 1141 1142 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1143 return; 1144 1145 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1146 return; 1147 1148 boot->aarch32 = info->aarch32; 1149 init_32bit_cpu_features(&boot->aarch32); 1150 boot_cpu_32bit_regs_overridden = true; 1151 } 1152 1153 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1154 struct cpuinfo_32bit *boot) 1155 { 1156 int taint = 0; 1157 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1158 1159 /* 1160 * If we don't have AArch32 at EL1, then relax the strictness of 1161 * EL1-dependent register fields to avoid spurious sanity check fails. 1162 */ 1163 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1164 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1165 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1166 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1167 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1168 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1169 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1170 } 1171 1172 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1173 info->reg_id_dfr0, boot->reg_id_dfr0); 1174 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1175 info->reg_id_dfr1, boot->reg_id_dfr1); 1176 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1177 info->reg_id_isar0, boot->reg_id_isar0); 1178 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1179 info->reg_id_isar1, boot->reg_id_isar1); 1180 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1181 info->reg_id_isar2, boot->reg_id_isar2); 1182 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1183 info->reg_id_isar3, boot->reg_id_isar3); 1184 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1185 info->reg_id_isar4, boot->reg_id_isar4); 1186 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1187 info->reg_id_isar5, boot->reg_id_isar5); 1188 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1189 info->reg_id_isar6, boot->reg_id_isar6); 1190 1191 /* 1192 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1193 * ACTLR formats could differ across CPUs and therefore would have to 1194 * be trapped for virtualization anyway. 1195 */ 1196 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1197 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1198 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1199 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1200 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1201 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1202 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1203 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1204 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1205 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1206 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1207 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1208 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1209 info->reg_id_pfr0, boot->reg_id_pfr0); 1210 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1211 info->reg_id_pfr1, boot->reg_id_pfr1); 1212 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1213 info->reg_id_pfr2, boot->reg_id_pfr2); 1214 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1215 info->reg_mvfr0, boot->reg_mvfr0); 1216 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1217 info->reg_mvfr1, boot->reg_mvfr1); 1218 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1219 info->reg_mvfr2, boot->reg_mvfr2); 1220 1221 return taint; 1222 } 1223 1224 /* 1225 * Update system wide CPU feature registers with the values from a 1226 * non-boot CPU. Also performs SANITY checks to make sure that there 1227 * aren't any insane variations from that of the boot CPU. 1228 */ 1229 void update_cpu_features(int cpu, 1230 struct cpuinfo_arm64 *info, 1231 struct cpuinfo_arm64 *boot) 1232 { 1233 int taint = 0; 1234 1235 /* 1236 * The kernel can handle differing I-cache policies, but otherwise 1237 * caches should look identical. Userspace JITs will make use of 1238 * *minLine. 1239 */ 1240 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1241 info->reg_ctr, boot->reg_ctr); 1242 1243 /* 1244 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1245 * could result in too much or too little memory being zeroed if a 1246 * process is preempted and migrated between CPUs. 1247 */ 1248 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1249 info->reg_dczid, boot->reg_dczid); 1250 1251 /* If different, timekeeping will be broken (especially with KVM) */ 1252 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1253 info->reg_cntfrq, boot->reg_cntfrq); 1254 1255 /* 1256 * The kernel uses self-hosted debug features and expects CPUs to 1257 * support identical debug features. We presently need CTX_CMPs, WRPs, 1258 * and BRPs to be identical. 1259 * ID_AA64DFR1 is currently RES0. 1260 */ 1261 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1262 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1263 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1264 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1265 /* 1266 * Even in big.LITTLE, processors should be identical instruction-set 1267 * wise. 1268 */ 1269 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1270 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1271 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1272 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1273 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1274 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1275 1276 /* 1277 * Differing PARange support is fine as long as all peripherals and 1278 * memory are mapped within the minimum PARange of all CPUs. 1279 * Linux should not care about secure memory. 1280 */ 1281 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1282 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1283 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1284 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1285 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1286 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1287 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1288 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1289 1290 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1291 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1292 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1293 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1294 1295 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1296 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1297 1298 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1299 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1300 1301 /* Probe vector lengths */ 1302 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1303 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1304 if (!system_capabilities_finalized()) { 1305 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1306 1307 vec_update_vq_map(ARM64_VEC_SVE); 1308 1309 cpacr_restore(cpacr); 1310 } 1311 } 1312 1313 if (IS_ENABLED(CONFIG_ARM64_SME) && 1314 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1315 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1316 1317 /* 1318 * We mask out SMPS since even if the hardware 1319 * supports priorities the kernel does not at present 1320 * and we block access to them. 1321 */ 1322 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1323 1324 /* Probe vector lengths */ 1325 if (!system_capabilities_finalized()) 1326 vec_update_vq_map(ARM64_VEC_SME); 1327 1328 cpacr_restore(cpacr); 1329 } 1330 1331 /* 1332 * The kernel uses the LDGM/STGM instructions and the number of tags 1333 * they read/write depends on the GMID_EL1.BS field. Check that the 1334 * value is the same on all CPUs. 1335 */ 1336 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1337 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1338 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1339 info->reg_gmid, boot->reg_gmid); 1340 } 1341 1342 /* 1343 * If we don't have AArch32 at all then skip the checks entirely 1344 * as the register values may be UNKNOWN and we're not going to be 1345 * using them for anything. 1346 * 1347 * This relies on a sanitised view of the AArch64 ID registers 1348 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1349 */ 1350 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1351 lazy_init_32bit_cpu_features(info, boot); 1352 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1353 &boot->aarch32); 1354 } 1355 1356 /* 1357 * Mismatched CPU features are a recipe for disaster. Don't even 1358 * pretend to support them. 1359 */ 1360 if (taint) { 1361 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1362 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1363 } 1364 } 1365 1366 u64 read_sanitised_ftr_reg(u32 id) 1367 { 1368 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1369 1370 if (!regp) 1371 return 0; 1372 return regp->sys_val; 1373 } 1374 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1375 1376 #define read_sysreg_case(r) \ 1377 case r: val = read_sysreg_s(r); break; 1378 1379 /* 1380 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1381 * Read the system register on the current CPU 1382 */ 1383 u64 __read_sysreg_by_encoding(u32 sys_id) 1384 { 1385 struct arm64_ftr_reg *regp; 1386 u64 val; 1387 1388 switch (sys_id) { 1389 read_sysreg_case(SYS_ID_PFR0_EL1); 1390 read_sysreg_case(SYS_ID_PFR1_EL1); 1391 read_sysreg_case(SYS_ID_PFR2_EL1); 1392 read_sysreg_case(SYS_ID_DFR0_EL1); 1393 read_sysreg_case(SYS_ID_DFR1_EL1); 1394 read_sysreg_case(SYS_ID_MMFR0_EL1); 1395 read_sysreg_case(SYS_ID_MMFR1_EL1); 1396 read_sysreg_case(SYS_ID_MMFR2_EL1); 1397 read_sysreg_case(SYS_ID_MMFR3_EL1); 1398 read_sysreg_case(SYS_ID_MMFR4_EL1); 1399 read_sysreg_case(SYS_ID_MMFR5_EL1); 1400 read_sysreg_case(SYS_ID_ISAR0_EL1); 1401 read_sysreg_case(SYS_ID_ISAR1_EL1); 1402 read_sysreg_case(SYS_ID_ISAR2_EL1); 1403 read_sysreg_case(SYS_ID_ISAR3_EL1); 1404 read_sysreg_case(SYS_ID_ISAR4_EL1); 1405 read_sysreg_case(SYS_ID_ISAR5_EL1); 1406 read_sysreg_case(SYS_ID_ISAR6_EL1); 1407 read_sysreg_case(SYS_MVFR0_EL1); 1408 read_sysreg_case(SYS_MVFR1_EL1); 1409 read_sysreg_case(SYS_MVFR2_EL1); 1410 1411 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1412 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1413 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1414 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1415 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1416 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1417 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1418 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1419 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1420 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1421 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1422 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1423 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1424 1425 read_sysreg_case(SYS_CNTFRQ_EL0); 1426 read_sysreg_case(SYS_CTR_EL0); 1427 read_sysreg_case(SYS_DCZID_EL0); 1428 1429 default: 1430 BUG(); 1431 return 0; 1432 } 1433 1434 regp = get_arm64_ftr_reg(sys_id); 1435 if (regp) { 1436 val &= ~regp->override->mask; 1437 val |= (regp->override->val & regp->override->mask); 1438 } 1439 1440 return val; 1441 } 1442 1443 #include <linux/irqchip/arm-gic-v3.h> 1444 1445 static bool 1446 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1447 { 1448 return true; 1449 } 1450 1451 static bool 1452 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1453 { 1454 int val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1455 entry->field_width, 1456 entry->sign); 1457 1458 return val >= entry->min_field_value; 1459 } 1460 1461 static u64 1462 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1463 { 1464 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1465 if (scope == SCOPE_SYSTEM) 1466 return read_sanitised_ftr_reg(entry->sys_reg); 1467 else 1468 return __read_sysreg_by_encoding(entry->sys_reg); 1469 } 1470 1471 static bool 1472 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1473 { 1474 int mask; 1475 struct arm64_ftr_reg *regp; 1476 u64 val = read_scoped_sysreg(entry, scope); 1477 1478 regp = get_arm64_ftr_reg(entry->sys_reg); 1479 if (!regp) 1480 return false; 1481 1482 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1483 entry->field_pos, 1484 entry->field_width); 1485 if (!mask) 1486 return false; 1487 1488 return feature_matches(val, entry); 1489 } 1490 1491 static bool 1492 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1493 { 1494 u64 val = read_scoped_sysreg(entry, scope); 1495 return feature_matches(val, entry); 1496 } 1497 1498 const struct cpumask *system_32bit_el0_cpumask(void) 1499 { 1500 if (!system_supports_32bit_el0()) 1501 return cpu_none_mask; 1502 1503 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1504 return cpu_32bit_el0_mask; 1505 1506 return cpu_possible_mask; 1507 } 1508 1509 static int __init parse_32bit_el0_param(char *str) 1510 { 1511 allow_mismatched_32bit_el0 = true; 1512 return 0; 1513 } 1514 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1515 1516 static ssize_t aarch32_el0_show(struct device *dev, 1517 struct device_attribute *attr, char *buf) 1518 { 1519 const struct cpumask *mask = system_32bit_el0_cpumask(); 1520 1521 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1522 } 1523 static const DEVICE_ATTR_RO(aarch32_el0); 1524 1525 static int __init aarch32_el0_sysfs_init(void) 1526 { 1527 struct device *dev_root; 1528 int ret = 0; 1529 1530 if (!allow_mismatched_32bit_el0) 1531 return 0; 1532 1533 dev_root = bus_get_dev_root(&cpu_subsys); 1534 if (dev_root) { 1535 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1536 put_device(dev_root); 1537 } 1538 return ret; 1539 } 1540 device_initcall(aarch32_el0_sysfs_init); 1541 1542 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1543 { 1544 if (!has_cpuid_feature(entry, scope)) 1545 return allow_mismatched_32bit_el0; 1546 1547 if (scope == SCOPE_SYSTEM) 1548 pr_info("detected: 32-bit EL0 Support\n"); 1549 1550 return true; 1551 } 1552 1553 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1554 { 1555 bool has_sre; 1556 1557 if (!has_cpuid_feature(entry, scope)) 1558 return false; 1559 1560 has_sre = gic_enable_sre(); 1561 if (!has_sre) 1562 pr_warn_once("%s present but disabled by higher exception level\n", 1563 entry->desc); 1564 1565 return has_sre; 1566 } 1567 1568 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1569 int scope) 1570 { 1571 u64 ctr; 1572 1573 if (scope == SCOPE_SYSTEM) 1574 ctr = arm64_ftr_reg_ctrel0.sys_val; 1575 else 1576 ctr = read_cpuid_effective_cachetype(); 1577 1578 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1579 } 1580 1581 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1582 { 1583 /* 1584 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1585 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1586 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1587 * value. 1588 */ 1589 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1590 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1591 } 1592 1593 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1594 int scope) 1595 { 1596 u64 ctr; 1597 1598 if (scope == SCOPE_SYSTEM) 1599 ctr = arm64_ftr_reg_ctrel0.sys_val; 1600 else 1601 ctr = read_cpuid_cachetype(); 1602 1603 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1604 } 1605 1606 static bool __maybe_unused 1607 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1608 { 1609 /* 1610 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1611 * may share TLB entries with a CPU stuck in the crashed 1612 * kernel. 1613 */ 1614 if (is_kdump_kernel()) 1615 return false; 1616 1617 if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1618 return false; 1619 1620 return has_cpuid_feature(entry, scope); 1621 } 1622 1623 /* 1624 * This check is triggered during the early boot before the cpufeature 1625 * is initialised. Checking the status on the local CPU allows the boot 1626 * CPU to detect the need for non-global mappings and thus avoiding a 1627 * pagetable re-write after all the CPUs are booted. This check will be 1628 * anyway run on individual CPUs, allowing us to get the consistent 1629 * state once the SMP CPUs are up and thus make the switch to non-global 1630 * mappings if required. 1631 */ 1632 bool kaslr_requires_kpti(void) 1633 { 1634 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 1635 return false; 1636 1637 /* 1638 * E0PD does a similar job to KPTI so can be used instead 1639 * where available. 1640 */ 1641 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 1642 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 1643 if (cpuid_feature_extract_unsigned_field(mmfr2, 1644 ID_AA64MMFR2_EL1_E0PD_SHIFT)) 1645 return false; 1646 } 1647 1648 /* 1649 * Systems affected by Cavium erratum 24756 are incompatible 1650 * with KPTI. 1651 */ 1652 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) { 1653 extern const struct midr_range cavium_erratum_27456_cpus[]; 1654 1655 if (is_midr_in_range_list(read_cpuid_id(), 1656 cavium_erratum_27456_cpus)) 1657 return false; 1658 } 1659 1660 return kaslr_enabled(); 1661 } 1662 1663 static bool __meltdown_safe = true; 1664 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1665 1666 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1667 int scope) 1668 { 1669 /* List of CPUs that are not vulnerable and don't need KPTI */ 1670 static const struct midr_range kpti_safe_list[] = { 1671 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1672 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1673 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1674 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1675 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1676 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1677 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1678 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1679 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1680 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1681 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1682 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1683 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1684 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1685 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1686 { /* sentinel */ } 1687 }; 1688 char const *str = "kpti command line option"; 1689 bool meltdown_safe; 1690 1691 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1692 1693 /* Defer to CPU feature registers */ 1694 if (has_cpuid_feature(entry, scope)) 1695 meltdown_safe = true; 1696 1697 if (!meltdown_safe) 1698 __meltdown_safe = false; 1699 1700 /* 1701 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1702 * ThunderX leads to apparent I-cache corruption of kernel text, which 1703 * ends as well as you might imagine. Don't even try. We cannot rely 1704 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1705 * because cpucap detection order may change. However, since we know 1706 * affected CPUs are always in a homogeneous configuration, it is 1707 * safe to rely on this_cpu_has_cap() here. 1708 */ 1709 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1710 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1711 __kpti_forced = -1; 1712 } 1713 1714 /* Useful for KASLR robustness */ 1715 if (kaslr_requires_kpti()) { 1716 if (!__kpti_forced) { 1717 str = "KASLR"; 1718 __kpti_forced = 1; 1719 } 1720 } 1721 1722 if (cpu_mitigations_off() && !__kpti_forced) { 1723 str = "mitigations=off"; 1724 __kpti_forced = -1; 1725 } 1726 1727 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1728 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1729 return false; 1730 } 1731 1732 /* Forced? */ 1733 if (__kpti_forced) { 1734 pr_info_once("kernel page table isolation forced %s by %s\n", 1735 __kpti_forced > 0 ? "ON" : "OFF", str); 1736 return __kpti_forced > 0; 1737 } 1738 1739 return !meltdown_safe; 1740 } 1741 1742 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2) 1743 static bool has_lpa2_at_stage1(u64 mmfr0) 1744 { 1745 unsigned int tgran; 1746 1747 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1748 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 1749 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2; 1750 } 1751 1752 static bool has_lpa2_at_stage2(u64 mmfr0) 1753 { 1754 unsigned int tgran; 1755 1756 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1757 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT); 1758 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2; 1759 } 1760 1761 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1762 { 1763 u64 mmfr0; 1764 1765 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 1766 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0); 1767 } 1768 #else 1769 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1770 { 1771 return false; 1772 } 1773 #endif 1774 1775 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1776 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) 1777 1778 extern 1779 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt, 1780 phys_addr_t size, pgprot_t prot, 1781 phys_addr_t (*pgtable_alloc)(int), int flags); 1782 1783 static phys_addr_t __initdata kpti_ng_temp_alloc; 1784 1785 static phys_addr_t __init kpti_ng_pgd_alloc(int shift) 1786 { 1787 kpti_ng_temp_alloc -= PAGE_SIZE; 1788 return kpti_ng_temp_alloc; 1789 } 1790 1791 static int __init __kpti_install_ng_mappings(void *__unused) 1792 { 1793 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long); 1794 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1795 kpti_remap_fn *remap_fn; 1796 1797 int cpu = smp_processor_id(); 1798 int levels = CONFIG_PGTABLE_LEVELS; 1799 int order = order_base_2(levels); 1800 u64 kpti_ng_temp_pgd_pa = 0; 1801 pgd_t *kpti_ng_temp_pgd; 1802 u64 alloc = 0; 1803 1804 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1805 1806 if (!cpu) { 1807 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 1808 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE); 1809 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd); 1810 1811 // 1812 // Create a minimal page table hierarchy that permits us to map 1813 // the swapper page tables temporarily as we traverse them. 1814 // 1815 // The physical pages are laid out as follows: 1816 // 1817 // +--------+-/-------+-/------ +-\\--------+ 1818 // : PTE[] : | PMD[] : | PUD[] : || PGD[] : 1819 // +--------+-\-------+-\------ +-//--------+ 1820 // ^ 1821 // The first page is mapped into this hierarchy at a PMD_SHIFT 1822 // aligned virtual address, so that we can manipulate the PTE 1823 // level entries while the mapping is active. The first entry 1824 // covers the PTE[] page itself, the remaining entries are free 1825 // to be used as a ad-hoc fixmap. 1826 // 1827 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc), 1828 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL, 1829 kpti_ng_pgd_alloc, 0); 1830 } 1831 1832 cpu_install_idmap(); 1833 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA); 1834 cpu_uninstall_idmap(); 1835 1836 if (!cpu) { 1837 free_pages(alloc, order); 1838 arm64_use_ng_mappings = true; 1839 } 1840 1841 return 0; 1842 } 1843 1844 static void __init kpti_install_ng_mappings(void) 1845 { 1846 /* Check whether KPTI is going to be used */ 1847 if (!arm64_kernel_unmapped_at_el0()) 1848 return; 1849 1850 /* 1851 * We don't need to rewrite the page-tables if either we've done 1852 * it already or we have KASLR enabled and therefore have not 1853 * created any global mappings at all. 1854 */ 1855 if (arm64_use_ng_mappings) 1856 return; 1857 1858 stop_machine(__kpti_install_ng_mappings, NULL, cpu_online_mask); 1859 } 1860 1861 #else 1862 static inline void kpti_install_ng_mappings(void) 1863 { 1864 } 1865 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1866 1867 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 1868 { 1869 if (__this_cpu_read(this_cpu_vector) == vectors) { 1870 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1871 1872 __this_cpu_write(this_cpu_vector, v); 1873 } 1874 1875 } 1876 1877 static int __init parse_kpti(char *str) 1878 { 1879 bool enabled; 1880 int ret = kstrtobool(str, &enabled); 1881 1882 if (ret) 1883 return ret; 1884 1885 __kpti_forced = enabled ? 1 : -1; 1886 return 0; 1887 } 1888 early_param("kpti", parse_kpti); 1889 1890 #ifdef CONFIG_ARM64_HW_AFDBM 1891 static struct cpumask dbm_cpus __read_mostly; 1892 1893 static inline void __cpu_enable_hw_dbm(void) 1894 { 1895 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1896 1897 write_sysreg(tcr, tcr_el1); 1898 isb(); 1899 local_flush_tlb_all(); 1900 } 1901 1902 static bool cpu_has_broken_dbm(void) 1903 { 1904 /* List of CPUs which have broken DBM support. */ 1905 static const struct midr_range cpus[] = { 1906 #ifdef CONFIG_ARM64_ERRATUM_1024718 1907 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1908 /* Kryo4xx Silver (rdpe => r1p0) */ 1909 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1910 #endif 1911 #ifdef CONFIG_ARM64_ERRATUM_2051678 1912 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 1913 #endif 1914 {}, 1915 }; 1916 1917 return is_midr_in_range_list(read_cpuid_id(), cpus); 1918 } 1919 1920 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1921 { 1922 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1923 !cpu_has_broken_dbm(); 1924 } 1925 1926 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1927 { 1928 if (cpu_can_use_dbm(cap)) { 1929 __cpu_enable_hw_dbm(); 1930 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 1931 } 1932 } 1933 1934 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1935 int __unused) 1936 { 1937 /* 1938 * DBM is a non-conflicting feature. i.e, the kernel can safely 1939 * run a mix of CPUs with and without the feature. So, we 1940 * unconditionally enable the capability to allow any late CPU 1941 * to use the feature. We only enable the control bits on the 1942 * CPU, if it is supported. 1943 */ 1944 1945 return true; 1946 } 1947 1948 #endif 1949 1950 #ifdef CONFIG_ARM64_AMU_EXTN 1951 1952 /* 1953 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1954 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1955 * information regarding all the events that it supports. When a CPU bit is 1956 * set in the cpumask, the user of this feature can only rely on the presence 1957 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1958 * counters are enabled or access to these counters is enabled by code 1959 * executed at higher exception levels (firmware). 1960 */ 1961 static struct cpumask amu_cpus __read_mostly; 1962 1963 bool cpu_has_amu_feat(int cpu) 1964 { 1965 return cpumask_test_cpu(cpu, &amu_cpus); 1966 } 1967 1968 int get_cpu_with_amu_feat(void) 1969 { 1970 return cpumask_any(&amu_cpus); 1971 } 1972 1973 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1974 { 1975 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1976 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1977 1978 /* 0 reference values signal broken/disabled counters */ 1979 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 1980 update_freq_counters_refs(); 1981 } 1982 } 1983 1984 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1985 int __unused) 1986 { 1987 /* 1988 * The AMU extension is a non-conflicting feature: the kernel can 1989 * safely run a mix of CPUs with and without support for the 1990 * activity monitors extension. Therefore, unconditionally enable 1991 * the capability to allow any late CPU to use the feature. 1992 * 1993 * With this feature unconditionally enabled, the cpu_enable 1994 * function will be called for all CPUs that match the criteria, 1995 * including secondary and hotplugged, marking this feature as 1996 * present on that respective CPU. The enable function will also 1997 * print a detection message. 1998 */ 1999 2000 return true; 2001 } 2002 #else 2003 int get_cpu_with_amu_feat(void) 2004 { 2005 return nr_cpu_ids; 2006 } 2007 #endif 2008 2009 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 2010 { 2011 return is_kernel_in_hyp_mode(); 2012 } 2013 2014 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 2015 { 2016 /* 2017 * Copy register values that aren't redirected by hardware. 2018 * 2019 * Before code patching, we only set tpidr_el1, all CPUs need to copy 2020 * this value to tpidr_el2 before we patch the code. Once we've done 2021 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 2022 * do anything here. 2023 */ 2024 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 2025 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 2026 } 2027 2028 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 2029 int scope) 2030 { 2031 if (kvm_get_mode() != KVM_MODE_NV) 2032 return false; 2033 2034 if (!has_cpuid_feature(cap, scope)) { 2035 pr_warn("unavailable: %s\n", cap->desc); 2036 return false; 2037 } 2038 2039 return true; 2040 } 2041 2042 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2043 int __unused) 2044 { 2045 u64 val; 2046 2047 val = read_sysreg(id_aa64mmfr1_el1); 2048 if (!cpuid_feature_extract_unsigned_field(val, ID_AA64MMFR1_EL1_VH_SHIFT)) 2049 return false; 2050 2051 val = arm64_sw_feature_override.val & arm64_sw_feature_override.mask; 2052 return cpuid_feature_extract_unsigned_field(val, ARM64_SW_FEATURE_OVERRIDE_HVHE); 2053 } 2054 2055 #ifdef CONFIG_ARM64_PAN 2056 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2057 { 2058 /* 2059 * We modify PSTATE. This won't work from irq context as the PSTATE 2060 * is discarded once we return from the exception. 2061 */ 2062 WARN_ON_ONCE(in_interrupt()); 2063 2064 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2065 set_pstate_pan(1); 2066 } 2067 #endif /* CONFIG_ARM64_PAN */ 2068 2069 #ifdef CONFIG_ARM64_RAS_EXTN 2070 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2071 { 2072 /* Firmware may have left a deferred SError in this register. */ 2073 write_sysreg_s(0, SYS_DISR_EL1); 2074 } 2075 #endif /* CONFIG_ARM64_RAS_EXTN */ 2076 2077 #ifdef CONFIG_ARM64_PTR_AUTH 2078 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2079 { 2080 int boot_val, sec_val; 2081 2082 /* We don't expect to be called with SCOPE_SYSTEM */ 2083 WARN_ON(scope == SCOPE_SYSTEM); 2084 /* 2085 * The ptr-auth feature levels are not intercompatible with lower 2086 * levels. Hence we must match ptr-auth feature level of the secondary 2087 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2088 * from the sanitised register whereas direct register read is done for 2089 * the secondary CPUs. 2090 * The sanitised feature state is guaranteed to match that of the 2091 * boot CPU as a mismatched secondary CPU is parked before it gets 2092 * a chance to update the state, with the capability. 2093 */ 2094 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2095 entry->field_pos, entry->sign); 2096 if (scope & SCOPE_BOOT_CPU) 2097 return boot_val >= entry->min_field_value; 2098 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2099 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2100 entry->field_pos, entry->sign); 2101 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2102 } 2103 2104 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2105 int scope) 2106 { 2107 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2108 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2109 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2110 2111 return apa || apa3 || api; 2112 } 2113 2114 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2115 int __unused) 2116 { 2117 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2118 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2119 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2120 2121 return gpa || gpa3 || gpi; 2122 } 2123 #endif /* CONFIG_ARM64_PTR_AUTH */ 2124 2125 #ifdef CONFIG_ARM64_E0PD 2126 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2127 { 2128 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2129 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 2130 } 2131 #endif /* CONFIG_ARM64_E0PD */ 2132 2133 #ifdef CONFIG_ARM64_PSEUDO_NMI 2134 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2135 int scope) 2136 { 2137 /* 2138 * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU 2139 * feature, so will be detected earlier. 2140 */ 2141 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS); 2142 if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS)) 2143 return false; 2144 2145 return enable_pseudo_nmi; 2146 } 2147 2148 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2149 int scope) 2150 { 2151 /* 2152 * If we're not using priority masking then we won't be poking PMR_EL1, 2153 * and there's no need to relax synchronization of writes to it, and 2154 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2155 * that. 2156 * 2157 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2158 * feature, so will be detected earlier. 2159 */ 2160 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2161 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2162 return false; 2163 2164 /* 2165 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2166 * hint for interrupt distribution, a DSB is not necessary when 2167 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2168 * 2169 * Linux itself doesn't use 1:N distribution, so has no need to 2170 * set PMHE. The only reason to have it set is if EL3 requires it 2171 * (and we can't change it). 2172 */ 2173 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2174 } 2175 #endif 2176 2177 #ifdef CONFIG_ARM64_BTI 2178 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2179 { 2180 /* 2181 * Use of X16/X17 for tail-calls and trampolines that jump to 2182 * function entry points using BR is a requirement for 2183 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2184 * So, be strict and forbid other BRs using other registers to 2185 * jump onto a PACIxSP instruction: 2186 */ 2187 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2188 isb(); 2189 } 2190 #endif /* CONFIG_ARM64_BTI */ 2191 2192 #ifdef CONFIG_ARM64_MTE 2193 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2194 { 2195 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2196 2197 mte_cpu_setup(); 2198 2199 /* 2200 * Clear the tags in the zero page. This needs to be done via the 2201 * linear map which has the Tagged attribute. 2202 */ 2203 if (try_page_mte_tagging(ZERO_PAGE(0))) { 2204 mte_clear_page_tags(lm_alias(empty_zero_page)); 2205 set_page_mte_tagged(ZERO_PAGE(0)); 2206 } 2207 2208 kasan_init_hw_tags_cpu(); 2209 } 2210 #endif /* CONFIG_ARM64_MTE */ 2211 2212 static void user_feature_fixup(void) 2213 { 2214 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2215 struct arm64_ftr_reg *regp; 2216 2217 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2218 if (regp) 2219 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2220 } 2221 } 2222 2223 static void elf_hwcap_fixup(void) 2224 { 2225 #ifdef CONFIG_COMPAT 2226 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2227 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2228 #endif /* CONFIG_COMPAT */ 2229 } 2230 2231 #ifdef CONFIG_KVM 2232 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2233 { 2234 return kvm_get_mode() == KVM_MODE_PROTECTED; 2235 } 2236 #endif /* CONFIG_KVM */ 2237 2238 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2239 { 2240 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2241 } 2242 2243 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2244 { 2245 set_pstate_dit(1); 2246 } 2247 2248 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2249 { 2250 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2251 } 2252 2253 /* Internal helper functions to match cpu capability type */ 2254 static bool 2255 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2256 { 2257 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2258 } 2259 2260 static bool 2261 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2262 { 2263 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2264 } 2265 2266 static bool 2267 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2268 { 2269 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2270 } 2271 2272 static const struct arm64_cpu_capabilities arm64_features[] = { 2273 { 2274 .capability = ARM64_ALWAYS_BOOT, 2275 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2276 .matches = has_always, 2277 }, 2278 { 2279 .capability = ARM64_ALWAYS_SYSTEM, 2280 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2281 .matches = has_always, 2282 }, 2283 { 2284 .desc = "GIC system register CPU interface", 2285 .capability = ARM64_HAS_GIC_CPUIF_SYSREGS, 2286 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2287 .matches = has_useable_gicv3_cpuif, 2288 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2289 }, 2290 { 2291 .desc = "Enhanced Counter Virtualization", 2292 .capability = ARM64_HAS_ECV, 2293 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2294 .matches = has_cpuid_feature, 2295 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2296 }, 2297 { 2298 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2299 .capability = ARM64_HAS_ECV_CNTPOFF, 2300 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2301 .matches = has_cpuid_feature, 2302 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2303 }, 2304 #ifdef CONFIG_ARM64_PAN 2305 { 2306 .desc = "Privileged Access Never", 2307 .capability = ARM64_HAS_PAN, 2308 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2309 .matches = has_cpuid_feature, 2310 .cpu_enable = cpu_enable_pan, 2311 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2312 }, 2313 #endif /* CONFIG_ARM64_PAN */ 2314 #ifdef CONFIG_ARM64_EPAN 2315 { 2316 .desc = "Enhanced Privileged Access Never", 2317 .capability = ARM64_HAS_EPAN, 2318 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2319 .matches = has_cpuid_feature, 2320 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2321 }, 2322 #endif /* CONFIG_ARM64_EPAN */ 2323 #ifdef CONFIG_ARM64_LSE_ATOMICS 2324 { 2325 .desc = "LSE atomic instructions", 2326 .capability = ARM64_HAS_LSE_ATOMICS, 2327 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2328 .matches = has_cpuid_feature, 2329 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2330 }, 2331 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2332 { 2333 .desc = "Virtualization Host Extensions", 2334 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2335 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2336 .matches = runs_at_el2, 2337 .cpu_enable = cpu_copy_el2regs, 2338 }, 2339 { 2340 .desc = "Nested Virtualization Support", 2341 .capability = ARM64_HAS_NESTED_VIRT, 2342 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2343 .matches = has_nested_virt_support, 2344 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2) 2345 }, 2346 { 2347 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2348 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2349 .matches = has_32bit_el0, 2350 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2351 }, 2352 #ifdef CONFIG_KVM 2353 { 2354 .desc = "32-bit EL1 Support", 2355 .capability = ARM64_HAS_32BIT_EL1, 2356 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2357 .matches = has_cpuid_feature, 2358 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2359 }, 2360 { 2361 .desc = "Protected KVM", 2362 .capability = ARM64_KVM_PROTECTED_MODE, 2363 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2364 .matches = is_kvm_protected_mode, 2365 }, 2366 { 2367 .desc = "HCRX_EL2 register", 2368 .capability = ARM64_HAS_HCX, 2369 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2370 .matches = has_cpuid_feature, 2371 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2372 }, 2373 #endif 2374 { 2375 .desc = "Kernel page table isolation (KPTI)", 2376 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2377 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2378 .cpu_enable = cpu_enable_kpti, 2379 .matches = unmap_kernel_at_el0, 2380 /* 2381 * The ID feature fields below are used to indicate that 2382 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2383 * more details. 2384 */ 2385 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2386 }, 2387 { 2388 .capability = ARM64_HAS_FPSIMD, 2389 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2390 .matches = has_cpuid_feature, 2391 .cpu_enable = cpu_enable_fpsimd, 2392 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2393 }, 2394 #ifdef CONFIG_ARM64_PMEM 2395 { 2396 .desc = "Data cache clean to Point of Persistence", 2397 .capability = ARM64_HAS_DCPOP, 2398 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2399 .matches = has_cpuid_feature, 2400 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2401 }, 2402 { 2403 .desc = "Data cache clean to Point of Deep Persistence", 2404 .capability = ARM64_HAS_DCPODP, 2405 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2406 .matches = has_cpuid_feature, 2407 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2408 }, 2409 #endif 2410 #ifdef CONFIG_ARM64_SVE 2411 { 2412 .desc = "Scalable Vector Extension", 2413 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2414 .capability = ARM64_SVE, 2415 .cpu_enable = cpu_enable_sve, 2416 .matches = has_cpuid_feature, 2417 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2418 }, 2419 #endif /* CONFIG_ARM64_SVE */ 2420 #ifdef CONFIG_ARM64_RAS_EXTN 2421 { 2422 .desc = "RAS Extension Support", 2423 .capability = ARM64_HAS_RAS_EXTN, 2424 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2425 .matches = has_cpuid_feature, 2426 .cpu_enable = cpu_clear_disr, 2427 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2428 }, 2429 #endif /* CONFIG_ARM64_RAS_EXTN */ 2430 #ifdef CONFIG_ARM64_AMU_EXTN 2431 { 2432 .desc = "Activity Monitors Unit (AMU)", 2433 .capability = ARM64_HAS_AMU_EXTN, 2434 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2435 .matches = has_amu, 2436 .cpu_enable = cpu_amu_enable, 2437 .cpus = &amu_cpus, 2438 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2439 }, 2440 #endif /* CONFIG_ARM64_AMU_EXTN */ 2441 { 2442 .desc = "Data cache clean to the PoU not required for I/D coherence", 2443 .capability = ARM64_HAS_CACHE_IDC, 2444 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2445 .matches = has_cache_idc, 2446 .cpu_enable = cpu_emulate_effective_ctr, 2447 }, 2448 { 2449 .desc = "Instruction cache invalidation not required for I/D coherence", 2450 .capability = ARM64_HAS_CACHE_DIC, 2451 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2452 .matches = has_cache_dic, 2453 }, 2454 { 2455 .desc = "Stage-2 Force Write-Back", 2456 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2457 .capability = ARM64_HAS_STAGE2_FWB, 2458 .matches = has_cpuid_feature, 2459 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2460 }, 2461 { 2462 .desc = "ARMv8.4 Translation Table Level", 2463 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2464 .capability = ARM64_HAS_ARMv8_4_TTL, 2465 .matches = has_cpuid_feature, 2466 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2467 }, 2468 { 2469 .desc = "TLB range maintenance instructions", 2470 .capability = ARM64_HAS_TLB_RANGE, 2471 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2472 .matches = has_cpuid_feature, 2473 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2474 }, 2475 #ifdef CONFIG_ARM64_HW_AFDBM 2476 { 2477 .desc = "Hardware dirty bit management", 2478 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2479 .capability = ARM64_HW_DBM, 2480 .matches = has_hw_dbm, 2481 .cpu_enable = cpu_enable_hw_dbm, 2482 .cpus = &dbm_cpus, 2483 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2484 }, 2485 #endif 2486 { 2487 .desc = "CRC32 instructions", 2488 .capability = ARM64_HAS_CRC32, 2489 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2490 .matches = has_cpuid_feature, 2491 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2492 }, 2493 { 2494 .desc = "Speculative Store Bypassing Safe (SSBS)", 2495 .capability = ARM64_SSBS, 2496 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2497 .matches = has_cpuid_feature, 2498 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2499 }, 2500 #ifdef CONFIG_ARM64_CNP 2501 { 2502 .desc = "Common not Private translations", 2503 .capability = ARM64_HAS_CNP, 2504 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2505 .matches = has_useable_cnp, 2506 .cpu_enable = cpu_enable_cnp, 2507 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2508 }, 2509 #endif 2510 { 2511 .desc = "Speculation barrier (SB)", 2512 .capability = ARM64_HAS_SB, 2513 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2514 .matches = has_cpuid_feature, 2515 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2516 }, 2517 #ifdef CONFIG_ARM64_PTR_AUTH 2518 { 2519 .desc = "Address authentication (architected QARMA5 algorithm)", 2520 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2521 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2522 .matches = has_address_auth_cpucap, 2523 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2524 }, 2525 { 2526 .desc = "Address authentication (architected QARMA3 algorithm)", 2527 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2528 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2529 .matches = has_address_auth_cpucap, 2530 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2531 }, 2532 { 2533 .desc = "Address authentication (IMP DEF algorithm)", 2534 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2535 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2536 .matches = has_address_auth_cpucap, 2537 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2538 }, 2539 { 2540 .capability = ARM64_HAS_ADDRESS_AUTH, 2541 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2542 .matches = has_address_auth_metacap, 2543 }, 2544 { 2545 .desc = "Generic authentication (architected QARMA5 algorithm)", 2546 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2547 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2548 .matches = has_cpuid_feature, 2549 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2550 }, 2551 { 2552 .desc = "Generic authentication (architected QARMA3 algorithm)", 2553 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2554 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2555 .matches = has_cpuid_feature, 2556 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2557 }, 2558 { 2559 .desc = "Generic authentication (IMP DEF algorithm)", 2560 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2561 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2562 .matches = has_cpuid_feature, 2563 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2564 }, 2565 { 2566 .capability = ARM64_HAS_GENERIC_AUTH, 2567 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2568 .matches = has_generic_auth, 2569 }, 2570 #endif /* CONFIG_ARM64_PTR_AUTH */ 2571 #ifdef CONFIG_ARM64_PSEUDO_NMI 2572 { 2573 /* 2574 * Depends on having GICv3 2575 */ 2576 .desc = "IRQ priority masking", 2577 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2578 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2579 .matches = can_use_gic_priorities, 2580 }, 2581 { 2582 /* 2583 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2584 */ 2585 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2586 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2587 .matches = has_gic_prio_relaxed_sync, 2588 }, 2589 #endif 2590 #ifdef CONFIG_ARM64_E0PD 2591 { 2592 .desc = "E0PD", 2593 .capability = ARM64_HAS_E0PD, 2594 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2595 .cpu_enable = cpu_enable_e0pd, 2596 .matches = has_cpuid_feature, 2597 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2598 }, 2599 #endif 2600 { 2601 .desc = "Random Number Generator", 2602 .capability = ARM64_HAS_RNG, 2603 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2604 .matches = has_cpuid_feature, 2605 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2606 }, 2607 #ifdef CONFIG_ARM64_BTI 2608 { 2609 .desc = "Branch Target Identification", 2610 .capability = ARM64_BTI, 2611 #ifdef CONFIG_ARM64_BTI_KERNEL 2612 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2613 #else 2614 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2615 #endif 2616 .matches = has_cpuid_feature, 2617 .cpu_enable = bti_enable, 2618 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2619 }, 2620 #endif 2621 #ifdef CONFIG_ARM64_MTE 2622 { 2623 .desc = "Memory Tagging Extension", 2624 .capability = ARM64_MTE, 2625 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2626 .matches = has_cpuid_feature, 2627 .cpu_enable = cpu_enable_mte, 2628 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2629 }, 2630 { 2631 .desc = "Asymmetric MTE Tag Check Fault", 2632 .capability = ARM64_MTE_ASYMM, 2633 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2634 .matches = has_cpuid_feature, 2635 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2636 }, 2637 #endif /* CONFIG_ARM64_MTE */ 2638 { 2639 .desc = "RCpc load-acquire (LDAPR)", 2640 .capability = ARM64_HAS_LDAPR, 2641 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2642 .matches = has_cpuid_feature, 2643 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2644 }, 2645 { 2646 .desc = "Fine Grained Traps", 2647 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2648 .capability = ARM64_HAS_FGT, 2649 .matches = has_cpuid_feature, 2650 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2651 }, 2652 #ifdef CONFIG_ARM64_SME 2653 { 2654 .desc = "Scalable Matrix Extension", 2655 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2656 .capability = ARM64_SME, 2657 .matches = has_cpuid_feature, 2658 .cpu_enable = cpu_enable_sme, 2659 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2660 }, 2661 /* FA64 should be sorted after the base SME capability */ 2662 { 2663 .desc = "FA64", 2664 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2665 .capability = ARM64_SME_FA64, 2666 .matches = has_cpuid_feature, 2667 .cpu_enable = cpu_enable_fa64, 2668 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2669 }, 2670 { 2671 .desc = "SME2", 2672 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2673 .capability = ARM64_SME2, 2674 .matches = has_cpuid_feature, 2675 .cpu_enable = cpu_enable_sme2, 2676 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2677 }, 2678 #endif /* CONFIG_ARM64_SME */ 2679 { 2680 .desc = "WFx with timeout", 2681 .capability = ARM64_HAS_WFXT, 2682 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2683 .matches = has_cpuid_feature, 2684 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 2685 }, 2686 { 2687 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2688 .capability = ARM64_HAS_TIDCP1, 2689 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2690 .matches = has_cpuid_feature, 2691 .cpu_enable = cpu_trap_el0_impdef, 2692 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 2693 }, 2694 { 2695 .desc = "Data independent timing control (DIT)", 2696 .capability = ARM64_HAS_DIT, 2697 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2698 .matches = has_cpuid_feature, 2699 .cpu_enable = cpu_enable_dit, 2700 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 2701 }, 2702 { 2703 .desc = "Memory Copy and Memory Set instructions", 2704 .capability = ARM64_HAS_MOPS, 2705 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2706 .matches = has_cpuid_feature, 2707 .cpu_enable = cpu_enable_mops, 2708 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 2709 }, 2710 { 2711 .capability = ARM64_HAS_TCR2, 2712 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2713 .matches = has_cpuid_feature, 2714 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 2715 }, 2716 { 2717 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 2718 .capability = ARM64_HAS_S1PIE, 2719 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2720 .matches = has_cpuid_feature, 2721 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 2722 }, 2723 { 2724 .desc = "VHE for hypervisor only", 2725 .capability = ARM64_KVM_HVHE, 2726 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2727 .matches = hvhe_possible, 2728 }, 2729 { 2730 .desc = "Enhanced Virtualization Traps", 2731 .capability = ARM64_HAS_EVT, 2732 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2733 .matches = has_cpuid_feature, 2734 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 2735 }, 2736 { 2737 .desc = "52-bit Virtual Addressing for KVM (LPA2)", 2738 .capability = ARM64_HAS_LPA2, 2739 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2740 .matches = has_lpa2, 2741 }, 2742 {}, 2743 }; 2744 2745 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 2746 .matches = has_user_cpuid_feature, \ 2747 ARM64_CPUID_FIELDS(reg, field, min_value) 2748 2749 #define __HWCAP_CAP(name, cap_type, cap) \ 2750 .desc = name, \ 2751 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2752 .hwcap_type = cap_type, \ 2753 .hwcap = cap, \ 2754 2755 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 2756 { \ 2757 __HWCAP_CAP(#cap, cap_type, cap) \ 2758 HWCAP_CPUID_MATCH(reg, field, min_value) \ 2759 } 2760 2761 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2762 { \ 2763 __HWCAP_CAP(#cap, cap_type, cap) \ 2764 .matches = cpucap_multi_entry_cap_matches, \ 2765 .match_list = list, \ 2766 } 2767 2768 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2769 { \ 2770 __HWCAP_CAP(#cap, cap_type, cap) \ 2771 .matches = match, \ 2772 } 2773 2774 #ifdef CONFIG_ARM64_PTR_AUTH 2775 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2776 { 2777 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 2778 }, 2779 { 2780 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 2781 }, 2782 { 2783 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 2784 }, 2785 {}, 2786 }; 2787 2788 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2789 { 2790 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 2791 }, 2792 { 2793 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 2794 }, 2795 { 2796 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 2797 }, 2798 {}, 2799 }; 2800 #endif 2801 2802 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2803 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2804 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 2805 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2806 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2807 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2808 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2809 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2810 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 2811 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2812 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2813 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 2814 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 2815 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2816 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2817 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2818 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2819 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 2820 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 2821 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2822 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2823 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2824 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 2825 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2826 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2827 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2828 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2829 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2830 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2831 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 2832 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2833 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 2834 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 2835 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 2836 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 2837 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2838 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2839 #ifdef CONFIG_ARM64_SVE 2840 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 2841 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 2842 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2843 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2844 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2845 HWCAP_CAP(ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 2846 HWCAP_CAP(ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 2847 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 2848 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 2849 HWCAP_CAP(ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 2850 HWCAP_CAP(ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 2851 HWCAP_CAP(ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 2852 HWCAP_CAP(ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 2853 HWCAP_CAP(ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 2854 #endif 2855 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 2856 #ifdef CONFIG_ARM64_BTI 2857 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 2858 #endif 2859 #ifdef CONFIG_ARM64_PTR_AUTH 2860 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 2861 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 2862 #endif 2863 #ifdef CONFIG_ARM64_MTE 2864 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 2865 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 2866 #endif /* CONFIG_ARM64_MTE */ 2867 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 2868 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 2869 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 2870 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 2871 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 2872 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 2873 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 2874 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 2875 #ifdef CONFIG_ARM64_SME 2876 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 2877 HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 2878 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 2879 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 2880 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 2881 HWCAP_CAP(ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 2882 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 2883 HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 2884 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 2885 HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 2886 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 2887 HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 2888 HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 2889 HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 2890 #endif /* CONFIG_ARM64_SME */ 2891 {}, 2892 }; 2893 2894 #ifdef CONFIG_COMPAT 2895 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 2896 { 2897 /* 2898 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 2899 * in line with that of arm32 as in vfp_init(). We make sure that the 2900 * check is future proof, by making sure value is non-zero. 2901 */ 2902 u32 mvfr1; 2903 2904 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 2905 if (scope == SCOPE_SYSTEM) 2906 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 2907 else 2908 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 2909 2910 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 2911 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 2912 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 2913 } 2914 #endif 2915 2916 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 2917 #ifdef CONFIG_COMPAT 2918 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 2919 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 2920 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 2921 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 2922 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 2923 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 2924 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 2925 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 2926 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 2927 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 2928 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 2929 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 2930 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 2931 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 2932 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 2933 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 2934 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 2935 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 2936 #endif 2937 {}, 2938 }; 2939 2940 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2941 { 2942 switch (cap->hwcap_type) { 2943 case CAP_HWCAP: 2944 cpu_set_feature(cap->hwcap); 2945 break; 2946 #ifdef CONFIG_COMPAT 2947 case CAP_COMPAT_HWCAP: 2948 compat_elf_hwcap |= (u32)cap->hwcap; 2949 break; 2950 case CAP_COMPAT_HWCAP2: 2951 compat_elf_hwcap2 |= (u32)cap->hwcap; 2952 break; 2953 #endif 2954 default: 2955 WARN_ON(1); 2956 break; 2957 } 2958 } 2959 2960 /* Check if we have a particular HWCAP enabled */ 2961 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2962 { 2963 bool rc; 2964 2965 switch (cap->hwcap_type) { 2966 case CAP_HWCAP: 2967 rc = cpu_have_feature(cap->hwcap); 2968 break; 2969 #ifdef CONFIG_COMPAT 2970 case CAP_COMPAT_HWCAP: 2971 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 2972 break; 2973 case CAP_COMPAT_HWCAP2: 2974 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 2975 break; 2976 #endif 2977 default: 2978 WARN_ON(1); 2979 rc = false; 2980 } 2981 2982 return rc; 2983 } 2984 2985 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 2986 { 2987 /* We support emulation of accesses to CPU ID feature registers */ 2988 cpu_set_named_feature(CPUID); 2989 for (; hwcaps->matches; hwcaps++) 2990 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 2991 cap_set_elf_hwcap(hwcaps); 2992 } 2993 2994 static void update_cpu_capabilities(u16 scope_mask) 2995 { 2996 int i; 2997 const struct arm64_cpu_capabilities *caps; 2998 2999 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3000 for (i = 0; i < ARM64_NCAPS; i++) { 3001 caps = cpucap_ptrs[i]; 3002 if (!caps || !(caps->type & scope_mask) || 3003 cpus_have_cap(caps->capability) || 3004 !caps->matches(caps, cpucap_default_scope(caps))) 3005 continue; 3006 3007 if (caps->desc && !caps->cpus) 3008 pr_info("detected: %s\n", caps->desc); 3009 3010 __set_bit(caps->capability, system_cpucaps); 3011 3012 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 3013 set_bit(caps->capability, boot_cpucaps); 3014 } 3015 } 3016 3017 /* 3018 * Enable all the available capabilities on this CPU. The capabilities 3019 * with BOOT_CPU scope are handled separately and hence skipped here. 3020 */ 3021 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3022 { 3023 int i; 3024 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3025 3026 for_each_available_cap(i) { 3027 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3028 3029 if (WARN_ON(!cap)) 3030 continue; 3031 3032 if (!(cap->type & non_boot_scope)) 3033 continue; 3034 3035 if (cap->cpu_enable) 3036 cap->cpu_enable(cap); 3037 } 3038 return 0; 3039 } 3040 3041 /* 3042 * Run through the enabled capabilities and enable() it on all active 3043 * CPUs 3044 */ 3045 static void __init enable_cpu_capabilities(u16 scope_mask) 3046 { 3047 int i; 3048 const struct arm64_cpu_capabilities *caps; 3049 bool boot_scope; 3050 3051 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3052 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3053 3054 for (i = 0; i < ARM64_NCAPS; i++) { 3055 unsigned int num; 3056 3057 caps = cpucap_ptrs[i]; 3058 if (!caps || !(caps->type & scope_mask)) 3059 continue; 3060 num = caps->capability; 3061 if (!cpus_have_cap(num)) 3062 continue; 3063 3064 if (boot_scope && caps->cpu_enable) 3065 /* 3066 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3067 * before any secondary CPU boots. Thus, each secondary 3068 * will enable the capability as appropriate via 3069 * check_local_cpu_capabilities(). The only exception is 3070 * the boot CPU, for which the capability must be 3071 * enabled here. This approach avoids costly 3072 * stop_machine() calls for this case. 3073 */ 3074 caps->cpu_enable(caps); 3075 } 3076 3077 /* 3078 * For all non-boot scope capabilities, use stop_machine() 3079 * as it schedules the work allowing us to modify PSTATE, 3080 * instead of on_each_cpu() which uses an IPI, giving us a 3081 * PSTATE that disappears when we return. 3082 */ 3083 if (!boot_scope) 3084 stop_machine(cpu_enable_non_boot_scope_capabilities, 3085 NULL, cpu_online_mask); 3086 } 3087 3088 /* 3089 * Run through the list of capabilities to check for conflicts. 3090 * If the system has already detected a capability, take necessary 3091 * action on this CPU. 3092 */ 3093 static void verify_local_cpu_caps(u16 scope_mask) 3094 { 3095 int i; 3096 bool cpu_has_cap, system_has_cap; 3097 const struct arm64_cpu_capabilities *caps; 3098 3099 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3100 3101 for (i = 0; i < ARM64_NCAPS; i++) { 3102 caps = cpucap_ptrs[i]; 3103 if (!caps || !(caps->type & scope_mask)) 3104 continue; 3105 3106 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3107 system_has_cap = cpus_have_cap(caps->capability); 3108 3109 if (system_has_cap) { 3110 /* 3111 * Check if the new CPU misses an advertised feature, 3112 * which is not safe to miss. 3113 */ 3114 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3115 break; 3116 /* 3117 * We have to issue cpu_enable() irrespective of 3118 * whether the CPU has it or not, as it is enabeld 3119 * system wide. It is upto the call back to take 3120 * appropriate action on this CPU. 3121 */ 3122 if (caps->cpu_enable) 3123 caps->cpu_enable(caps); 3124 } else { 3125 /* 3126 * Check if the CPU has this capability if it isn't 3127 * safe to have when the system doesn't. 3128 */ 3129 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3130 break; 3131 } 3132 } 3133 3134 if (i < ARM64_NCAPS) { 3135 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3136 smp_processor_id(), caps->capability, 3137 caps->desc, system_has_cap, cpu_has_cap); 3138 3139 if (cpucap_panic_on_conflict(caps)) 3140 cpu_panic_kernel(); 3141 else 3142 cpu_die_early(); 3143 } 3144 } 3145 3146 /* 3147 * Check for CPU features that are used in early boot 3148 * based on the Boot CPU value. 3149 */ 3150 static void check_early_cpu_features(void) 3151 { 3152 verify_cpu_asid_bits(); 3153 3154 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3155 } 3156 3157 static void 3158 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3159 { 3160 3161 for (; caps->matches; caps++) 3162 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3163 pr_crit("CPU%d: missing HWCAP: %s\n", 3164 smp_processor_id(), caps->desc); 3165 cpu_die_early(); 3166 } 3167 } 3168 3169 static void verify_local_elf_hwcaps(void) 3170 { 3171 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3172 3173 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3174 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3175 } 3176 3177 static void verify_sve_features(void) 3178 { 3179 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3180 3181 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3182 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3183 smp_processor_id()); 3184 cpu_die_early(); 3185 } 3186 3187 cpacr_restore(cpacr); 3188 } 3189 3190 static void verify_sme_features(void) 3191 { 3192 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3193 3194 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3195 pr_crit("CPU%d: SME: vector length support mismatch\n", 3196 smp_processor_id()); 3197 cpu_die_early(); 3198 } 3199 3200 cpacr_restore(cpacr); 3201 } 3202 3203 static void verify_hyp_capabilities(void) 3204 { 3205 u64 safe_mmfr1, mmfr0, mmfr1; 3206 int parange, ipa_max; 3207 unsigned int safe_vmid_bits, vmid_bits; 3208 3209 if (!IS_ENABLED(CONFIG_KVM)) 3210 return; 3211 3212 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3213 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 3214 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3215 3216 /* Verify VMID bits */ 3217 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3218 vmid_bits = get_vmid_bits(mmfr1); 3219 if (vmid_bits < safe_vmid_bits) { 3220 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3221 cpu_die_early(); 3222 } 3223 3224 /* Verify IPA range */ 3225 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3226 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3227 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3228 if (ipa_max < get_kvm_ipa_limit()) { 3229 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3230 cpu_die_early(); 3231 } 3232 } 3233 3234 /* 3235 * Run through the enabled system capabilities and enable() it on this CPU. 3236 * The capabilities were decided based on the available CPUs at the boot time. 3237 * Any new CPU should match the system wide status of the capability. If the 3238 * new CPU doesn't have a capability which the system now has enabled, we 3239 * cannot do anything to fix it up and could cause unexpected failures. So 3240 * we park the CPU. 3241 */ 3242 static void verify_local_cpu_capabilities(void) 3243 { 3244 /* 3245 * The capabilities with SCOPE_BOOT_CPU are checked from 3246 * check_early_cpu_features(), as they need to be verified 3247 * on all secondary CPUs. 3248 */ 3249 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3250 verify_local_elf_hwcaps(); 3251 3252 if (system_supports_sve()) 3253 verify_sve_features(); 3254 3255 if (system_supports_sme()) 3256 verify_sme_features(); 3257 3258 if (is_hyp_mode_available()) 3259 verify_hyp_capabilities(); 3260 } 3261 3262 void check_local_cpu_capabilities(void) 3263 { 3264 /* 3265 * All secondary CPUs should conform to the early CPU features 3266 * in use by the kernel based on boot CPU. 3267 */ 3268 check_early_cpu_features(); 3269 3270 /* 3271 * If we haven't finalised the system capabilities, this CPU gets 3272 * a chance to update the errata work arounds and local features. 3273 * Otherwise, this CPU should verify that it has all the system 3274 * advertised capabilities. 3275 */ 3276 if (!system_capabilities_finalized()) 3277 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3278 else 3279 verify_local_cpu_capabilities(); 3280 } 3281 3282 bool this_cpu_has_cap(unsigned int n) 3283 { 3284 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3285 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3286 3287 if (cap) 3288 return cap->matches(cap, SCOPE_LOCAL_CPU); 3289 } 3290 3291 return false; 3292 } 3293 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3294 3295 /* 3296 * This helper function is used in a narrow window when, 3297 * - The system wide safe registers are set with all the SMP CPUs and, 3298 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3299 */ 3300 static bool __maybe_unused __system_matches_cap(unsigned int n) 3301 { 3302 if (n < ARM64_NCAPS) { 3303 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3304 3305 if (cap) 3306 return cap->matches(cap, SCOPE_SYSTEM); 3307 } 3308 return false; 3309 } 3310 3311 void cpu_set_feature(unsigned int num) 3312 { 3313 set_bit(num, elf_hwcap); 3314 } 3315 3316 bool cpu_have_feature(unsigned int num) 3317 { 3318 return test_bit(num, elf_hwcap); 3319 } 3320 EXPORT_SYMBOL_GPL(cpu_have_feature); 3321 3322 unsigned long cpu_get_elf_hwcap(void) 3323 { 3324 /* 3325 * We currently only populate the first 32 bits of AT_HWCAP. Please 3326 * note that for userspace compatibility we guarantee that bits 62 3327 * and 63 will always be returned as 0. 3328 */ 3329 return elf_hwcap[0]; 3330 } 3331 3332 unsigned long cpu_get_elf_hwcap2(void) 3333 { 3334 return elf_hwcap[1]; 3335 } 3336 3337 static void __init setup_boot_cpu_capabilities(void) 3338 { 3339 /* 3340 * The boot CPU's feature register values have been recorded. Detect 3341 * boot cpucaps and local cpucaps for the boot CPU, then enable and 3342 * patch alternatives for the available boot cpucaps. 3343 */ 3344 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3345 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3346 apply_boot_alternatives(); 3347 } 3348 3349 void __init setup_boot_cpu_features(void) 3350 { 3351 /* 3352 * Initialize the indirect array of CPU capabilities pointers before we 3353 * handle the boot CPU. 3354 */ 3355 init_cpucap_indirect_list(); 3356 3357 /* 3358 * Detect broken pseudo-NMI. Must be called _before_ the call to 3359 * setup_boot_cpu_capabilities() since it interacts with 3360 * can_use_gic_priorities(). 3361 */ 3362 detect_system_supports_pseudo_nmi(); 3363 3364 setup_boot_cpu_capabilities(); 3365 } 3366 3367 static void __init setup_system_capabilities(void) 3368 { 3369 /* 3370 * The system-wide safe feature register values have been finalized. 3371 * Detect, enable, and patch alternatives for the available system 3372 * cpucaps. 3373 */ 3374 update_cpu_capabilities(SCOPE_SYSTEM); 3375 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3376 apply_alternatives_all(); 3377 3378 /* 3379 * Log any cpucaps with a cpumask as these aren't logged by 3380 * update_cpu_capabilities(). 3381 */ 3382 for (int i = 0; i < ARM64_NCAPS; i++) { 3383 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 3384 3385 if (caps && caps->cpus && caps->desc && 3386 cpumask_any(caps->cpus) < nr_cpu_ids) 3387 pr_info("detected: %s on CPU%*pbl\n", 3388 caps->desc, cpumask_pr_args(caps->cpus)); 3389 } 3390 3391 /* 3392 * TTBR0 PAN doesn't have its own cpucap, so log it manually. 3393 */ 3394 if (system_uses_ttbr0_pan()) 3395 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3396 } 3397 3398 void __init setup_system_features(void) 3399 { 3400 setup_system_capabilities(); 3401 3402 kpti_install_ng_mappings(); 3403 3404 sve_setup(); 3405 sme_setup(); 3406 3407 /* 3408 * Check for sane CTR_EL0.CWG value. 3409 */ 3410 if (!cache_type_cwg()) 3411 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3412 ARCH_DMA_MINALIGN); 3413 } 3414 3415 void __init setup_user_features(void) 3416 { 3417 user_feature_fixup(); 3418 3419 setup_elf_hwcaps(arm64_elf_hwcaps); 3420 3421 if (system_supports_32bit_el0()) { 3422 setup_elf_hwcaps(compat_elf_hwcaps); 3423 elf_hwcap_fixup(); 3424 } 3425 3426 minsigstksz_setup(); 3427 } 3428 3429 static int enable_mismatched_32bit_el0(unsigned int cpu) 3430 { 3431 /* 3432 * The first 32-bit-capable CPU we detected and so can no longer 3433 * be offlined by userspace. -1 indicates we haven't yet onlined 3434 * a 32-bit-capable CPU. 3435 */ 3436 static int lucky_winner = -1; 3437 3438 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3439 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); 3440 3441 if (cpu_32bit) { 3442 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3443 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3444 } 3445 3446 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3447 return 0; 3448 3449 if (lucky_winner >= 0) 3450 return 0; 3451 3452 /* 3453 * We've detected a mismatch. We need to keep one of our CPUs with 3454 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3455 * every CPU in the system for a 32-bit task. 3456 */ 3457 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3458 cpu_active_mask); 3459 get_cpu_device(lucky_winner)->offline_disabled = true; 3460 setup_elf_hwcaps(compat_elf_hwcaps); 3461 elf_hwcap_fixup(); 3462 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3463 cpu, lucky_winner); 3464 return 0; 3465 } 3466 3467 static int __init init_32bit_el0_mask(void) 3468 { 3469 if (!allow_mismatched_32bit_el0) 3470 return 0; 3471 3472 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3473 return -ENOMEM; 3474 3475 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3476 "arm64/mismatched_32bit_el0:online", 3477 enable_mismatched_32bit_el0, NULL); 3478 } 3479 subsys_initcall_sync(init_32bit_el0_mask); 3480 3481 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3482 { 3483 cpu_enable_swapper_cnp(); 3484 } 3485 3486 /* 3487 * We emulate only the following system register space. 3488 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 3489 * See Table C5-6 System instruction encodings for System register accesses, 3490 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3491 */ 3492 static inline bool __attribute_const__ is_emulated(u32 id) 3493 { 3494 return (sys_reg_Op0(id) == 0x3 && 3495 sys_reg_CRn(id) == 0x0 && 3496 sys_reg_Op1(id) == 0x0 && 3497 (sys_reg_CRm(id) == 0 || 3498 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 3499 } 3500 3501 /* 3502 * With CRm == 0, reg should be one of : 3503 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3504 */ 3505 static inline int emulate_id_reg(u32 id, u64 *valp) 3506 { 3507 switch (id) { 3508 case SYS_MIDR_EL1: 3509 *valp = read_cpuid_id(); 3510 break; 3511 case SYS_MPIDR_EL1: 3512 *valp = SYS_MPIDR_SAFE_VAL; 3513 break; 3514 case SYS_REVIDR_EL1: 3515 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3516 *valp = 0; 3517 break; 3518 default: 3519 return -EINVAL; 3520 } 3521 3522 return 0; 3523 } 3524 3525 static int emulate_sys_reg(u32 id, u64 *valp) 3526 { 3527 struct arm64_ftr_reg *regp; 3528 3529 if (!is_emulated(id)) 3530 return -EINVAL; 3531 3532 if (sys_reg_CRm(id) == 0) 3533 return emulate_id_reg(id, valp); 3534 3535 regp = get_arm64_ftr_reg_nowarn(id); 3536 if (regp) 3537 *valp = arm64_ftr_reg_user_value(regp); 3538 else 3539 /* 3540 * The untracked registers are either IMPLEMENTATION DEFINED 3541 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3542 */ 3543 *valp = 0; 3544 return 0; 3545 } 3546 3547 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3548 { 3549 int rc; 3550 u64 val; 3551 3552 rc = emulate_sys_reg(sys_reg, &val); 3553 if (!rc) { 3554 pt_regs_write_reg(regs, rt, val); 3555 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3556 } 3557 return rc; 3558 } 3559 3560 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 3561 { 3562 u32 sys_reg, rt; 3563 3564 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 3565 return false; 3566 3567 /* 3568 * sys_reg values are defined as used in mrs/msr instruction. 3569 * shift the imm value to get the encoding. 3570 */ 3571 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 3572 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 3573 return do_emulate_mrs(regs, sys_reg, rt) == 0; 3574 } 3575 3576 enum mitigation_state arm64_get_meltdown_state(void) 3577 { 3578 if (__meltdown_safe) 3579 return SPECTRE_UNAFFECTED; 3580 3581 if (arm64_kernel_unmapped_at_el0()) 3582 return SPECTRE_MITIGATED; 3583 3584 return SPECTRE_VULNERABLE; 3585 } 3586 3587 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 3588 char *buf) 3589 { 3590 switch (arm64_get_meltdown_state()) { 3591 case SPECTRE_UNAFFECTED: 3592 return sprintf(buf, "Not affected\n"); 3593 3594 case SPECTRE_MITIGATED: 3595 return sprintf(buf, "Mitigation: PTI\n"); 3596 3597 default: 3598 return sprintf(buf, "Vulnerable\n"); 3599 } 3600 } 3601