1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 79 #include <asm/cpu.h> 80 #include <asm/cpufeature.h> 81 #include <asm/cpu_ops.h> 82 #include <asm/fpsimd.h> 83 #include <asm/hwcap.h> 84 #include <asm/insn.h> 85 #include <asm/kvm_host.h> 86 #include <asm/mmu_context.h> 87 #include <asm/mte.h> 88 #include <asm/processor.h> 89 #include <asm/smp.h> 90 #include <asm/sysreg.h> 91 #include <asm/traps.h> 92 #include <asm/vectors.h> 93 #include <asm/virt.h> 94 95 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 96 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 97 98 #ifdef CONFIG_COMPAT 99 #define COMPAT_ELF_HWCAP_DEFAULT \ 100 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 101 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 102 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 103 COMPAT_HWCAP_LPAE) 104 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 105 unsigned int compat_elf_hwcap2 __read_mostly; 106 #endif 107 108 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 109 EXPORT_SYMBOL(system_cpucaps); 110 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 111 112 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 113 114 bool arm64_use_ng_mappings = false; 115 EXPORT_SYMBOL(arm64_use_ng_mappings); 116 117 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 118 119 /* 120 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 121 * support it? 122 */ 123 static bool __read_mostly allow_mismatched_32bit_el0; 124 125 /* 126 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 127 * seen at least one CPU capable of 32-bit EL0. 128 */ 129 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 130 131 /* 132 * Mask of CPUs supporting 32-bit EL0. 133 * Only valid if arm64_mismatched_32bit_el0 is enabled. 134 */ 135 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 136 137 void dump_cpu_features(void) 138 { 139 /* file-wide pr_fmt adds "CPU features: " prefix */ 140 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 141 } 142 143 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 144 .sys_reg = SYS_##reg, \ 145 .field_pos = reg##_##field##_SHIFT, \ 146 .field_width = reg##_##field##_WIDTH, \ 147 .sign = reg##_##field##_SIGNED, \ 148 .min_field_value = reg##_##field##_##min_value, 149 150 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 151 { \ 152 .sign = SIGNED, \ 153 .visible = VISIBLE, \ 154 .strict = STRICT, \ 155 .type = TYPE, \ 156 .shift = SHIFT, \ 157 .width = WIDTH, \ 158 .safe_val = SAFE_VAL, \ 159 } 160 161 /* Define a feature with unsigned values */ 162 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 163 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 164 165 /* Define a feature with a signed value */ 166 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 167 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 168 169 #define ARM64_FTR_END \ 170 { \ 171 .width = 0, \ 172 } 173 174 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 175 176 static bool __system_matches_cap(unsigned int n); 177 178 /* 179 * NOTE: Any changes to the visibility of features should be kept in 180 * sync with the documentation of the CPU feature register ABI. 181 */ 182 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 183 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 184 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 185 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 186 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 188 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 190 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 191 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 192 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 193 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 197 ARM64_FTR_END, 198 }; 199 200 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 204 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 206 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 207 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 208 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 209 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 210 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 211 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 212 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 213 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 214 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 215 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 217 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 219 ARM64_FTR_END, 220 }; 221 222 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 229 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 231 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 232 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 234 ARM64_FTR_END, 235 }; 236 237 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 238 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 243 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 245 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 248 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 249 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY), 253 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY), 254 ARM64_FTR_END, 255 }; 256 257 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 258 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 259 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 262 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 263 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 264 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 265 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 266 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 267 ARM64_FTR_END, 268 }; 269 270 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 271 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 272 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 273 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 274 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 275 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 276 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 277 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 278 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 279 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 280 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 281 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 282 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 283 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 284 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 285 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 286 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 287 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 288 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 289 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 290 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 291 ARM64_FTR_END, 292 }; 293 294 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 295 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 296 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 297 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 298 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 299 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 300 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 301 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 302 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 303 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 304 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 305 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 306 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 307 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 308 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 309 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 310 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 311 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 312 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 313 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 314 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 315 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 316 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 317 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 318 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 319 ARM64_FTR_END, 320 }; 321 322 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 323 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 324 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 325 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 326 /* 327 * Page size not being supported at Stage-2 is not fatal. You 328 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 329 * your favourite nesting hypervisor. 330 * 331 * There is a small corner case where the hypervisor explicitly 332 * advertises a given granule size at Stage-2 (value 2) on some 333 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 334 * vCPUs. Although this is not forbidden by the architecture, it 335 * indicates that the hypervisor is being silly (or buggy). 336 * 337 * We make no effort to cope with this and pretend that if these 338 * fields are inconsistent across vCPUs, then it isn't worth 339 * trying to bring KVM up. 340 */ 341 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 342 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 343 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 344 /* 345 * We already refuse to boot CPUs that don't support our configured 346 * page size, so we can only detect mismatches for a page size other 347 * than the one we're currently using. Unfortunately, SoCs like this 348 * exist in the wild so, even though we don't like it, we'll have to go 349 * along with it and treat them as non-strict. 350 */ 351 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 352 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 354 355 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 356 /* Linux shouldn't care about secure memory */ 357 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 358 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 359 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 360 /* 361 * Differing PARange is fine as long as all peripherals and memory are mapped 362 * within the minimum PARange of all CPUs 363 */ 364 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 365 ARM64_FTR_END, 366 }; 367 368 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 369 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 370 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 371 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 372 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 373 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 374 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 375 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 376 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 377 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 378 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 379 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 380 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 381 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 382 ARM64_FTR_END, 383 }; 384 385 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 386 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 387 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 389 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 390 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 391 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 392 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 393 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 394 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 395 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 396 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 397 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 398 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 399 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 400 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 401 ARM64_FTR_END, 402 }; 403 404 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 405 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 406 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 407 ARM64_FTR_END, 408 }; 409 410 static const struct arm64_ftr_bits ftr_ctr[] = { 411 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 412 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 413 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 414 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 415 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 416 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 417 /* 418 * Linux can handle differing I-cache policies. Userspace JITs will 419 * make use of *minLine. 420 * If we have differing I-cache policies, report it as the weakest - VIPT. 421 */ 422 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 423 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 424 ARM64_FTR_END, 425 }; 426 427 static struct arm64_ftr_override __ro_after_init no_override = { }; 428 429 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 430 .name = "SYS_CTR_EL0", 431 .ftr_bits = ftr_ctr, 432 .override = &no_override, 433 }; 434 435 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 436 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 441 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 444 ARM64_FTR_END, 445 }; 446 447 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 448 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 449 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 453 /* 454 * We can instantiate multiple PMU instances with different levels 455 * of support. 456 */ 457 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 459 ARM64_FTR_END, 460 }; 461 462 static const struct arm64_ftr_bits ftr_mvfr0[] = { 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 468 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 471 ARM64_FTR_END, 472 }; 473 474 static const struct arm64_ftr_bits ftr_mvfr1[] = { 475 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 478 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 480 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 483 ARM64_FTR_END, 484 }; 485 486 static const struct arm64_ftr_bits ftr_mvfr2[] = { 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 489 ARM64_FTR_END, 490 }; 491 492 static const struct arm64_ftr_bits ftr_dczid[] = { 493 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 494 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 495 ARM64_FTR_END, 496 }; 497 498 static const struct arm64_ftr_bits ftr_gmid[] = { 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 500 ARM64_FTR_END, 501 }; 502 503 static const struct arm64_ftr_bits ftr_id_isar0[] = { 504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 505 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 507 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 511 ARM64_FTR_END, 512 }; 513 514 static const struct arm64_ftr_bits ftr_id_isar5[] = { 515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 516 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 517 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 518 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 519 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 520 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 521 ARM64_FTR_END, 522 }; 523 524 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 525 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 532 533 /* 534 * SpecSEI = 1 indicates that the PE might generate an SError on an 535 * external abort on speculative read. It is safe to assume that an 536 * SError might be generated than it will not be. Hence it has been 537 * classified as FTR_HIGHER_SAFE. 538 */ 539 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 540 ARM64_FTR_END, 541 }; 542 543 static const struct arm64_ftr_bits ftr_id_isar4[] = { 544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 546 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 547 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 548 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 549 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 550 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 551 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 552 ARM64_FTR_END, 553 }; 554 555 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 557 ARM64_FTR_END, 558 }; 559 560 static const struct arm64_ftr_bits ftr_id_isar6[] = { 561 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 562 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 563 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 564 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 565 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 566 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 567 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 568 ARM64_FTR_END, 569 }; 570 571 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 572 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 573 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 575 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 576 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 577 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 578 ARM64_FTR_END, 579 }; 580 581 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 582 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 583 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 584 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 585 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 586 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 587 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 588 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 589 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 590 ARM64_FTR_END, 591 }; 592 593 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 594 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 595 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 596 ARM64_FTR_END, 597 }; 598 599 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 600 /* [31:28] TraceFilt */ 601 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 602 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 603 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 604 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 605 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 606 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 607 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 608 ARM64_FTR_END, 609 }; 610 611 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 612 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 613 ARM64_FTR_END, 614 }; 615 616 /* 617 * Common ftr bits for a 32bit register with all hidden, strict 618 * attributes, with 4bit feature fields and a default safe value of 619 * 0. Covers the following 32bit registers: 620 * id_isar[1-3], id_mmfr[1-3] 621 */ 622 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 623 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 624 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 625 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 626 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 627 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 628 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 629 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 630 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 631 ARM64_FTR_END, 632 }; 633 634 /* Table for a single 32bit feature value */ 635 static const struct arm64_ftr_bits ftr_single32[] = { 636 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 637 ARM64_FTR_END, 638 }; 639 640 static const struct arm64_ftr_bits ftr_raz[] = { 641 ARM64_FTR_END, 642 }; 643 644 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 645 .sys_id = id, \ 646 .reg = &(struct arm64_ftr_reg){ \ 647 .name = id_str, \ 648 .override = (ovr), \ 649 .ftr_bits = &((table)[0]), \ 650 }} 651 652 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 653 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 654 655 #define ARM64_FTR_REG(id, table) \ 656 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 657 658 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override; 659 struct arm64_ftr_override __ro_after_init id_aa64pfr0_override; 660 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override; 661 struct arm64_ftr_override __ro_after_init id_aa64zfr0_override; 662 struct arm64_ftr_override __ro_after_init id_aa64smfr0_override; 663 struct arm64_ftr_override __ro_after_init id_aa64isar1_override; 664 struct arm64_ftr_override __ro_after_init id_aa64isar2_override; 665 666 struct arm64_ftr_override arm64_sw_feature_override; 667 668 static const struct __ftr_reg_entry { 669 u32 sys_id; 670 struct arm64_ftr_reg *reg; 671 } arm64_ftr_regs[] = { 672 673 /* Op1 = 0, CRn = 0, CRm = 1 */ 674 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 675 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 676 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 677 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 678 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 679 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 680 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 681 682 /* Op1 = 0, CRn = 0, CRm = 2 */ 683 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 684 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 685 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 686 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 687 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 688 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 689 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 690 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 691 692 /* Op1 = 0, CRn = 0, CRm = 3 */ 693 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 694 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 695 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 696 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 697 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 698 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 699 700 /* Op1 = 0, CRn = 0, CRm = 4 */ 701 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 702 &id_aa64pfr0_override), 703 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 704 &id_aa64pfr1_override), 705 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 706 &id_aa64zfr0_override), 707 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 708 &id_aa64smfr0_override), 709 710 /* Op1 = 0, CRn = 0, CRm = 5 */ 711 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 712 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 713 714 /* Op1 = 0, CRn = 0, CRm = 6 */ 715 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 716 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 717 &id_aa64isar1_override), 718 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 719 &id_aa64isar2_override), 720 721 /* Op1 = 0, CRn = 0, CRm = 7 */ 722 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 723 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 724 &id_aa64mmfr1_override), 725 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 726 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 727 728 /* Op1 = 1, CRn = 0, CRm = 0 */ 729 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 730 731 /* Op1 = 3, CRn = 0, CRm = 0 */ 732 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 733 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 734 735 /* Op1 = 3, CRn = 14, CRm = 0 */ 736 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 737 }; 738 739 static int search_cmp_ftr_reg(const void *id, const void *regp) 740 { 741 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 742 } 743 744 /* 745 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 746 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 747 * ascending order of sys_id, we use binary search to find a matching 748 * entry. 749 * 750 * returns - Upon success, matching ftr_reg entry for id. 751 * - NULL on failure. It is upto the caller to decide 752 * the impact of a failure. 753 */ 754 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 755 { 756 const struct __ftr_reg_entry *ret; 757 758 ret = bsearch((const void *)(unsigned long)sys_id, 759 arm64_ftr_regs, 760 ARRAY_SIZE(arm64_ftr_regs), 761 sizeof(arm64_ftr_regs[0]), 762 search_cmp_ftr_reg); 763 if (ret) 764 return ret->reg; 765 return NULL; 766 } 767 768 /* 769 * get_arm64_ftr_reg - Looks up a feature register entry using 770 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 771 * 772 * returns - Upon success, matching ftr_reg entry for id. 773 * - NULL on failure but with an WARN_ON(). 774 */ 775 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 776 { 777 struct arm64_ftr_reg *reg; 778 779 reg = get_arm64_ftr_reg_nowarn(sys_id); 780 781 /* 782 * Requesting a non-existent register search is an error. Warn 783 * and let the caller handle it. 784 */ 785 WARN_ON(!reg); 786 return reg; 787 } 788 789 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 790 s64 ftr_val) 791 { 792 u64 mask = arm64_ftr_mask(ftrp); 793 794 reg &= ~mask; 795 reg |= (ftr_val << ftrp->shift) & mask; 796 return reg; 797 } 798 799 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 800 s64 cur) 801 { 802 s64 ret = 0; 803 804 switch (ftrp->type) { 805 case FTR_EXACT: 806 ret = ftrp->safe_val; 807 break; 808 case FTR_LOWER_SAFE: 809 ret = min(new, cur); 810 break; 811 case FTR_HIGHER_OR_ZERO_SAFE: 812 if (!cur || !new) 813 break; 814 fallthrough; 815 case FTR_HIGHER_SAFE: 816 ret = max(new, cur); 817 break; 818 default: 819 BUG(); 820 } 821 822 return ret; 823 } 824 825 static void __init sort_ftr_regs(void) 826 { 827 unsigned int i; 828 829 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 830 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 831 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 832 unsigned int j = 0; 833 834 /* 835 * Features here must be sorted in descending order with respect 836 * to their shift values and should not overlap with each other. 837 */ 838 for (; ftr_bits->width != 0; ftr_bits++, j++) { 839 unsigned int width = ftr_reg->ftr_bits[j].width; 840 unsigned int shift = ftr_reg->ftr_bits[j].shift; 841 unsigned int prev_shift; 842 843 WARN((shift + width) > 64, 844 "%s has invalid feature at shift %d\n", 845 ftr_reg->name, shift); 846 847 /* 848 * Skip the first feature. There is nothing to 849 * compare against for now. 850 */ 851 if (j == 0) 852 continue; 853 854 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 855 WARN((shift + width) > prev_shift, 856 "%s has feature overlap at shift %d\n", 857 ftr_reg->name, shift); 858 } 859 860 /* 861 * Skip the first register. There is nothing to 862 * compare against for now. 863 */ 864 if (i == 0) 865 continue; 866 /* 867 * Registers here must be sorted in ascending order with respect 868 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 869 * to work correctly. 870 */ 871 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 872 } 873 } 874 875 /* 876 * Initialise the CPU feature register from Boot CPU values. 877 * Also initiliases the strict_mask for the register. 878 * Any bits that are not covered by an arm64_ftr_bits entry are considered 879 * RES0 for the system-wide value, and must strictly match. 880 */ 881 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 882 { 883 u64 val = 0; 884 u64 strict_mask = ~0x0ULL; 885 u64 user_mask = 0; 886 u64 valid_mask = 0; 887 888 const struct arm64_ftr_bits *ftrp; 889 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 890 891 if (!reg) 892 return; 893 894 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 895 u64 ftr_mask = arm64_ftr_mask(ftrp); 896 s64 ftr_new = arm64_ftr_value(ftrp, new); 897 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 898 899 if ((ftr_mask & reg->override->mask) == ftr_mask) { 900 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 901 char *str = NULL; 902 903 if (ftr_ovr != tmp) { 904 /* Unsafe, remove the override */ 905 reg->override->mask &= ~ftr_mask; 906 reg->override->val &= ~ftr_mask; 907 tmp = ftr_ovr; 908 str = "ignoring override"; 909 } else if (ftr_new != tmp) { 910 /* Override was valid */ 911 ftr_new = tmp; 912 str = "forced"; 913 } else if (ftr_ovr == tmp) { 914 /* Override was the safe value */ 915 str = "already set"; 916 } 917 918 if (str) 919 pr_warn("%s[%d:%d]: %s to %llx\n", 920 reg->name, 921 ftrp->shift + ftrp->width - 1, 922 ftrp->shift, str, tmp); 923 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 924 reg->override->val &= ~ftr_mask; 925 pr_warn("%s[%d:%d]: impossible override, ignored\n", 926 reg->name, 927 ftrp->shift + ftrp->width - 1, 928 ftrp->shift); 929 } 930 931 val = arm64_ftr_set_value(ftrp, val, ftr_new); 932 933 valid_mask |= ftr_mask; 934 if (!ftrp->strict) 935 strict_mask &= ~ftr_mask; 936 if (ftrp->visible) 937 user_mask |= ftr_mask; 938 else 939 reg->user_val = arm64_ftr_set_value(ftrp, 940 reg->user_val, 941 ftrp->safe_val); 942 } 943 944 val &= valid_mask; 945 946 reg->sys_val = val; 947 reg->strict_mask = strict_mask; 948 reg->user_mask = user_mask; 949 } 950 951 extern const struct arm64_cpu_capabilities arm64_errata[]; 952 static const struct arm64_cpu_capabilities arm64_features[]; 953 954 static void __init 955 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 956 { 957 for (; caps->matches; caps++) { 958 if (WARN(caps->capability >= ARM64_NCAPS, 959 "Invalid capability %d\n", caps->capability)) 960 continue; 961 if (WARN(cpucap_ptrs[caps->capability], 962 "Duplicate entry for capability %d\n", 963 caps->capability)) 964 continue; 965 cpucap_ptrs[caps->capability] = caps; 966 } 967 } 968 969 static void __init init_cpucap_indirect_list(void) 970 { 971 init_cpucap_indirect_list_from_array(arm64_features); 972 init_cpucap_indirect_list_from_array(arm64_errata); 973 } 974 975 static void __init setup_boot_cpu_capabilities(void); 976 977 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 978 { 979 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 980 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 981 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 982 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 983 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 984 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 985 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 986 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 987 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 988 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 989 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 990 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 991 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 992 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 993 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 994 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 995 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 996 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 997 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 998 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 999 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1000 } 1001 1002 #ifdef CONFIG_ARM64_PSEUDO_NMI 1003 static bool enable_pseudo_nmi; 1004 1005 static int __init early_enable_pseudo_nmi(char *p) 1006 { 1007 return kstrtobool(p, &enable_pseudo_nmi); 1008 } 1009 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1010 1011 static __init void detect_system_supports_pseudo_nmi(void) 1012 { 1013 struct device_node *np; 1014 1015 if (!enable_pseudo_nmi) 1016 return; 1017 1018 /* 1019 * Detect broken MediaTek firmware that doesn't properly save and 1020 * restore GIC priorities. 1021 */ 1022 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1023 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1024 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1025 enable_pseudo_nmi = false; 1026 } 1027 of_node_put(np); 1028 } 1029 #else /* CONFIG_ARM64_PSEUDO_NMI */ 1030 static inline void detect_system_supports_pseudo_nmi(void) { } 1031 #endif 1032 1033 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1034 { 1035 /* Before we start using the tables, make sure it is sorted */ 1036 sort_ftr_regs(); 1037 1038 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1039 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1040 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1041 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1042 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1043 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1044 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1045 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1046 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1047 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1048 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1049 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1050 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1051 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1052 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1053 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1054 1055 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1056 init_32bit_cpu_features(&info->aarch32); 1057 1058 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1059 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1060 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1061 1062 vec_init_vq_map(ARM64_VEC_SVE); 1063 1064 cpacr_restore(cpacr); 1065 } 1066 1067 if (IS_ENABLED(CONFIG_ARM64_SME) && 1068 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1069 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1070 1071 /* 1072 * We mask out SMPS since even if the hardware 1073 * supports priorities the kernel does not at present 1074 * and we block access to them. 1075 */ 1076 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1077 vec_init_vq_map(ARM64_VEC_SME); 1078 1079 cpacr_restore(cpacr); 1080 } 1081 1082 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1083 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1084 1085 /* 1086 * Initialize the indirect array of CPU capabilities pointers before we 1087 * handle the boot CPU below. 1088 */ 1089 init_cpucap_indirect_list(); 1090 1091 /* 1092 * Detect broken pseudo-NMI. Must be called _before_ the call to 1093 * setup_boot_cpu_capabilities() since it interacts with 1094 * can_use_gic_priorities(). 1095 */ 1096 detect_system_supports_pseudo_nmi(); 1097 1098 /* 1099 * Detect and enable early CPU capabilities based on the boot CPU, 1100 * after we have initialised the CPU feature infrastructure. 1101 */ 1102 setup_boot_cpu_capabilities(); 1103 } 1104 1105 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1106 { 1107 const struct arm64_ftr_bits *ftrp; 1108 1109 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1110 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1111 s64 ftr_new = arm64_ftr_value(ftrp, new); 1112 1113 if (ftr_cur == ftr_new) 1114 continue; 1115 /* Find a safe value */ 1116 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1117 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1118 } 1119 1120 } 1121 1122 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1123 { 1124 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1125 1126 if (!regp) 1127 return 0; 1128 1129 update_cpu_ftr_reg(regp, val); 1130 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1131 return 0; 1132 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1133 regp->name, boot, cpu, val); 1134 return 1; 1135 } 1136 1137 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1138 { 1139 const struct arm64_ftr_bits *ftrp; 1140 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1141 1142 if (!regp) 1143 return; 1144 1145 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1146 if (ftrp->shift == field) { 1147 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1148 break; 1149 } 1150 } 1151 1152 /* Bogus field? */ 1153 WARN_ON(!ftrp->width); 1154 } 1155 1156 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1157 struct cpuinfo_arm64 *boot) 1158 { 1159 static bool boot_cpu_32bit_regs_overridden = false; 1160 1161 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1162 return; 1163 1164 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1165 return; 1166 1167 boot->aarch32 = info->aarch32; 1168 init_32bit_cpu_features(&boot->aarch32); 1169 boot_cpu_32bit_regs_overridden = true; 1170 } 1171 1172 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1173 struct cpuinfo_32bit *boot) 1174 { 1175 int taint = 0; 1176 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1177 1178 /* 1179 * If we don't have AArch32 at EL1, then relax the strictness of 1180 * EL1-dependent register fields to avoid spurious sanity check fails. 1181 */ 1182 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1183 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1184 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1185 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1186 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1187 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1188 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1189 } 1190 1191 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1192 info->reg_id_dfr0, boot->reg_id_dfr0); 1193 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1194 info->reg_id_dfr1, boot->reg_id_dfr1); 1195 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1196 info->reg_id_isar0, boot->reg_id_isar0); 1197 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1198 info->reg_id_isar1, boot->reg_id_isar1); 1199 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1200 info->reg_id_isar2, boot->reg_id_isar2); 1201 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1202 info->reg_id_isar3, boot->reg_id_isar3); 1203 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1204 info->reg_id_isar4, boot->reg_id_isar4); 1205 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1206 info->reg_id_isar5, boot->reg_id_isar5); 1207 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1208 info->reg_id_isar6, boot->reg_id_isar6); 1209 1210 /* 1211 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1212 * ACTLR formats could differ across CPUs and therefore would have to 1213 * be trapped for virtualization anyway. 1214 */ 1215 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1216 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1217 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1218 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1219 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1220 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1221 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1222 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1223 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1224 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1225 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1226 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1227 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1228 info->reg_id_pfr0, boot->reg_id_pfr0); 1229 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1230 info->reg_id_pfr1, boot->reg_id_pfr1); 1231 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1232 info->reg_id_pfr2, boot->reg_id_pfr2); 1233 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1234 info->reg_mvfr0, boot->reg_mvfr0); 1235 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1236 info->reg_mvfr1, boot->reg_mvfr1); 1237 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1238 info->reg_mvfr2, boot->reg_mvfr2); 1239 1240 return taint; 1241 } 1242 1243 /* 1244 * Update system wide CPU feature registers with the values from a 1245 * non-boot CPU. Also performs SANITY checks to make sure that there 1246 * aren't any insane variations from that of the boot CPU. 1247 */ 1248 void update_cpu_features(int cpu, 1249 struct cpuinfo_arm64 *info, 1250 struct cpuinfo_arm64 *boot) 1251 { 1252 int taint = 0; 1253 1254 /* 1255 * The kernel can handle differing I-cache policies, but otherwise 1256 * caches should look identical. Userspace JITs will make use of 1257 * *minLine. 1258 */ 1259 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1260 info->reg_ctr, boot->reg_ctr); 1261 1262 /* 1263 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1264 * could result in too much or too little memory being zeroed if a 1265 * process is preempted and migrated between CPUs. 1266 */ 1267 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1268 info->reg_dczid, boot->reg_dczid); 1269 1270 /* If different, timekeeping will be broken (especially with KVM) */ 1271 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1272 info->reg_cntfrq, boot->reg_cntfrq); 1273 1274 /* 1275 * The kernel uses self-hosted debug features and expects CPUs to 1276 * support identical debug features. We presently need CTX_CMPs, WRPs, 1277 * and BRPs to be identical. 1278 * ID_AA64DFR1 is currently RES0. 1279 */ 1280 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1281 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1282 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1283 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1284 /* 1285 * Even in big.LITTLE, processors should be identical instruction-set 1286 * wise. 1287 */ 1288 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1289 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1290 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1291 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1292 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1293 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1294 1295 /* 1296 * Differing PARange support is fine as long as all peripherals and 1297 * memory are mapped within the minimum PARange of all CPUs. 1298 * Linux should not care about secure memory. 1299 */ 1300 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1301 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1302 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1303 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1304 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1305 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1306 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1307 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1308 1309 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1310 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1311 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1312 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1313 1314 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1315 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1316 1317 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1318 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1319 1320 /* Probe vector lengths */ 1321 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1322 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1323 if (!system_capabilities_finalized()) { 1324 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1325 1326 vec_update_vq_map(ARM64_VEC_SVE); 1327 1328 cpacr_restore(cpacr); 1329 } 1330 } 1331 1332 if (IS_ENABLED(CONFIG_ARM64_SME) && 1333 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1334 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1335 1336 /* 1337 * We mask out SMPS since even if the hardware 1338 * supports priorities the kernel does not at present 1339 * and we block access to them. 1340 */ 1341 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1342 1343 /* Probe vector lengths */ 1344 if (!system_capabilities_finalized()) 1345 vec_update_vq_map(ARM64_VEC_SME); 1346 1347 cpacr_restore(cpacr); 1348 } 1349 1350 /* 1351 * The kernel uses the LDGM/STGM instructions and the number of tags 1352 * they read/write depends on the GMID_EL1.BS field. Check that the 1353 * value is the same on all CPUs. 1354 */ 1355 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1356 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1357 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1358 info->reg_gmid, boot->reg_gmid); 1359 } 1360 1361 /* 1362 * If we don't have AArch32 at all then skip the checks entirely 1363 * as the register values may be UNKNOWN and we're not going to be 1364 * using them for anything. 1365 * 1366 * This relies on a sanitised view of the AArch64 ID registers 1367 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1368 */ 1369 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1370 lazy_init_32bit_cpu_features(info, boot); 1371 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1372 &boot->aarch32); 1373 } 1374 1375 /* 1376 * Mismatched CPU features are a recipe for disaster. Don't even 1377 * pretend to support them. 1378 */ 1379 if (taint) { 1380 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1381 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1382 } 1383 } 1384 1385 u64 read_sanitised_ftr_reg(u32 id) 1386 { 1387 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1388 1389 if (!regp) 1390 return 0; 1391 return regp->sys_val; 1392 } 1393 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1394 1395 #define read_sysreg_case(r) \ 1396 case r: val = read_sysreg_s(r); break; 1397 1398 /* 1399 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1400 * Read the system register on the current CPU 1401 */ 1402 u64 __read_sysreg_by_encoding(u32 sys_id) 1403 { 1404 struct arm64_ftr_reg *regp; 1405 u64 val; 1406 1407 switch (sys_id) { 1408 read_sysreg_case(SYS_ID_PFR0_EL1); 1409 read_sysreg_case(SYS_ID_PFR1_EL1); 1410 read_sysreg_case(SYS_ID_PFR2_EL1); 1411 read_sysreg_case(SYS_ID_DFR0_EL1); 1412 read_sysreg_case(SYS_ID_DFR1_EL1); 1413 read_sysreg_case(SYS_ID_MMFR0_EL1); 1414 read_sysreg_case(SYS_ID_MMFR1_EL1); 1415 read_sysreg_case(SYS_ID_MMFR2_EL1); 1416 read_sysreg_case(SYS_ID_MMFR3_EL1); 1417 read_sysreg_case(SYS_ID_MMFR4_EL1); 1418 read_sysreg_case(SYS_ID_MMFR5_EL1); 1419 read_sysreg_case(SYS_ID_ISAR0_EL1); 1420 read_sysreg_case(SYS_ID_ISAR1_EL1); 1421 read_sysreg_case(SYS_ID_ISAR2_EL1); 1422 read_sysreg_case(SYS_ID_ISAR3_EL1); 1423 read_sysreg_case(SYS_ID_ISAR4_EL1); 1424 read_sysreg_case(SYS_ID_ISAR5_EL1); 1425 read_sysreg_case(SYS_ID_ISAR6_EL1); 1426 read_sysreg_case(SYS_MVFR0_EL1); 1427 read_sysreg_case(SYS_MVFR1_EL1); 1428 read_sysreg_case(SYS_MVFR2_EL1); 1429 1430 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1431 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1432 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1433 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1434 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1435 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1436 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1437 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1438 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1439 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1440 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1441 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1442 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1443 1444 read_sysreg_case(SYS_CNTFRQ_EL0); 1445 read_sysreg_case(SYS_CTR_EL0); 1446 read_sysreg_case(SYS_DCZID_EL0); 1447 1448 default: 1449 BUG(); 1450 return 0; 1451 } 1452 1453 regp = get_arm64_ftr_reg(sys_id); 1454 if (regp) { 1455 val &= ~regp->override->mask; 1456 val |= (regp->override->val & regp->override->mask); 1457 } 1458 1459 return val; 1460 } 1461 1462 #include <linux/irqchip/arm-gic-v3.h> 1463 1464 static bool 1465 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1466 { 1467 return true; 1468 } 1469 1470 static bool 1471 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1472 { 1473 int val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1474 entry->field_width, 1475 entry->sign); 1476 1477 return val >= entry->min_field_value; 1478 } 1479 1480 static u64 1481 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1482 { 1483 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1484 if (scope == SCOPE_SYSTEM) 1485 return read_sanitised_ftr_reg(entry->sys_reg); 1486 else 1487 return __read_sysreg_by_encoding(entry->sys_reg); 1488 } 1489 1490 static bool 1491 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1492 { 1493 int mask; 1494 struct arm64_ftr_reg *regp; 1495 u64 val = read_scoped_sysreg(entry, scope); 1496 1497 regp = get_arm64_ftr_reg(entry->sys_reg); 1498 if (!regp) 1499 return false; 1500 1501 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1502 entry->field_pos, 1503 entry->field_width); 1504 if (!mask) 1505 return false; 1506 1507 return feature_matches(val, entry); 1508 } 1509 1510 static bool 1511 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1512 { 1513 u64 val = read_scoped_sysreg(entry, scope); 1514 return feature_matches(val, entry); 1515 } 1516 1517 const struct cpumask *system_32bit_el0_cpumask(void) 1518 { 1519 if (!system_supports_32bit_el0()) 1520 return cpu_none_mask; 1521 1522 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1523 return cpu_32bit_el0_mask; 1524 1525 return cpu_possible_mask; 1526 } 1527 1528 static int __init parse_32bit_el0_param(char *str) 1529 { 1530 allow_mismatched_32bit_el0 = true; 1531 return 0; 1532 } 1533 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1534 1535 static ssize_t aarch32_el0_show(struct device *dev, 1536 struct device_attribute *attr, char *buf) 1537 { 1538 const struct cpumask *mask = system_32bit_el0_cpumask(); 1539 1540 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1541 } 1542 static const DEVICE_ATTR_RO(aarch32_el0); 1543 1544 static int __init aarch32_el0_sysfs_init(void) 1545 { 1546 struct device *dev_root; 1547 int ret = 0; 1548 1549 if (!allow_mismatched_32bit_el0) 1550 return 0; 1551 1552 dev_root = bus_get_dev_root(&cpu_subsys); 1553 if (dev_root) { 1554 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1555 put_device(dev_root); 1556 } 1557 return ret; 1558 } 1559 device_initcall(aarch32_el0_sysfs_init); 1560 1561 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1562 { 1563 if (!has_cpuid_feature(entry, scope)) 1564 return allow_mismatched_32bit_el0; 1565 1566 if (scope == SCOPE_SYSTEM) 1567 pr_info("detected: 32-bit EL0 Support\n"); 1568 1569 return true; 1570 } 1571 1572 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1573 { 1574 bool has_sre; 1575 1576 if (!has_cpuid_feature(entry, scope)) 1577 return false; 1578 1579 has_sre = gic_enable_sre(); 1580 if (!has_sre) 1581 pr_warn_once("%s present but disabled by higher exception level\n", 1582 entry->desc); 1583 1584 return has_sre; 1585 } 1586 1587 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 1588 { 1589 u32 midr = read_cpuid_id(); 1590 1591 /* Cavium ThunderX pass 1.x and 2.x */ 1592 return midr_is_cpu_model_range(midr, MIDR_THUNDERX, 1593 MIDR_CPU_VAR_REV(0, 0), 1594 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 1595 } 1596 1597 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1598 int scope) 1599 { 1600 u64 ctr; 1601 1602 if (scope == SCOPE_SYSTEM) 1603 ctr = arm64_ftr_reg_ctrel0.sys_val; 1604 else 1605 ctr = read_cpuid_effective_cachetype(); 1606 1607 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1608 } 1609 1610 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1611 { 1612 /* 1613 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1614 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1615 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1616 * value. 1617 */ 1618 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1619 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1620 } 1621 1622 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1623 int scope) 1624 { 1625 u64 ctr; 1626 1627 if (scope == SCOPE_SYSTEM) 1628 ctr = arm64_ftr_reg_ctrel0.sys_val; 1629 else 1630 ctr = read_cpuid_cachetype(); 1631 1632 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1633 } 1634 1635 static bool __maybe_unused 1636 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1637 { 1638 /* 1639 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1640 * may share TLB entries with a CPU stuck in the crashed 1641 * kernel. 1642 */ 1643 if (is_kdump_kernel()) 1644 return false; 1645 1646 if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1647 return false; 1648 1649 return has_cpuid_feature(entry, scope); 1650 } 1651 1652 /* 1653 * This check is triggered during the early boot before the cpufeature 1654 * is initialised. Checking the status on the local CPU allows the boot 1655 * CPU to detect the need for non-global mappings and thus avoiding a 1656 * pagetable re-write after all the CPUs are booted. This check will be 1657 * anyway run on individual CPUs, allowing us to get the consistent 1658 * state once the SMP CPUs are up and thus make the switch to non-global 1659 * mappings if required. 1660 */ 1661 bool kaslr_requires_kpti(void) 1662 { 1663 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 1664 return false; 1665 1666 /* 1667 * E0PD does a similar job to KPTI so can be used instead 1668 * where available. 1669 */ 1670 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 1671 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 1672 if (cpuid_feature_extract_unsigned_field(mmfr2, 1673 ID_AA64MMFR2_EL1_E0PD_SHIFT)) 1674 return false; 1675 } 1676 1677 /* 1678 * Systems affected by Cavium erratum 24756 are incompatible 1679 * with KPTI. 1680 */ 1681 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) { 1682 extern const struct midr_range cavium_erratum_27456_cpus[]; 1683 1684 if (is_midr_in_range_list(read_cpuid_id(), 1685 cavium_erratum_27456_cpus)) 1686 return false; 1687 } 1688 1689 return kaslr_enabled(); 1690 } 1691 1692 static bool __meltdown_safe = true; 1693 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1694 1695 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1696 int scope) 1697 { 1698 /* List of CPUs that are not vulnerable and don't need KPTI */ 1699 static const struct midr_range kpti_safe_list[] = { 1700 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1701 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1702 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1703 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1704 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1705 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1706 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1707 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1708 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1709 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1710 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1711 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1712 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1713 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1714 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1715 { /* sentinel */ } 1716 }; 1717 char const *str = "kpti command line option"; 1718 bool meltdown_safe; 1719 1720 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1721 1722 /* Defer to CPU feature registers */ 1723 if (has_cpuid_feature(entry, scope)) 1724 meltdown_safe = true; 1725 1726 if (!meltdown_safe) 1727 __meltdown_safe = false; 1728 1729 /* 1730 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1731 * ThunderX leads to apparent I-cache corruption of kernel text, which 1732 * ends as well as you might imagine. Don't even try. We cannot rely 1733 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1734 * because cpucap detection order may change. However, since we know 1735 * affected CPUs are always in a homogeneous configuration, it is 1736 * safe to rely on this_cpu_has_cap() here. 1737 */ 1738 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1739 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1740 __kpti_forced = -1; 1741 } 1742 1743 /* Useful for KASLR robustness */ 1744 if (kaslr_requires_kpti()) { 1745 if (!__kpti_forced) { 1746 str = "KASLR"; 1747 __kpti_forced = 1; 1748 } 1749 } 1750 1751 if (cpu_mitigations_off() && !__kpti_forced) { 1752 str = "mitigations=off"; 1753 __kpti_forced = -1; 1754 } 1755 1756 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1757 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1758 return false; 1759 } 1760 1761 /* Forced? */ 1762 if (__kpti_forced) { 1763 pr_info_once("kernel page table isolation forced %s by %s\n", 1764 __kpti_forced > 0 ? "ON" : "OFF", str); 1765 return __kpti_forced > 0; 1766 } 1767 1768 return !meltdown_safe; 1769 } 1770 1771 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1772 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) 1773 1774 extern 1775 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt, 1776 phys_addr_t size, pgprot_t prot, 1777 phys_addr_t (*pgtable_alloc)(int), int flags); 1778 1779 static phys_addr_t __initdata kpti_ng_temp_alloc; 1780 1781 static phys_addr_t __init kpti_ng_pgd_alloc(int shift) 1782 { 1783 kpti_ng_temp_alloc -= PAGE_SIZE; 1784 return kpti_ng_temp_alloc; 1785 } 1786 1787 static int __init __kpti_install_ng_mappings(void *__unused) 1788 { 1789 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long); 1790 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1791 kpti_remap_fn *remap_fn; 1792 1793 int cpu = smp_processor_id(); 1794 int levels = CONFIG_PGTABLE_LEVELS; 1795 int order = order_base_2(levels); 1796 u64 kpti_ng_temp_pgd_pa = 0; 1797 pgd_t *kpti_ng_temp_pgd; 1798 u64 alloc = 0; 1799 1800 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1801 1802 if (!cpu) { 1803 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 1804 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE); 1805 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd); 1806 1807 // 1808 // Create a minimal page table hierarchy that permits us to map 1809 // the swapper page tables temporarily as we traverse them. 1810 // 1811 // The physical pages are laid out as follows: 1812 // 1813 // +--------+-/-------+-/------ +-\\--------+ 1814 // : PTE[] : | PMD[] : | PUD[] : || PGD[] : 1815 // +--------+-\-------+-\------ +-//--------+ 1816 // ^ 1817 // The first page is mapped into this hierarchy at a PMD_SHIFT 1818 // aligned virtual address, so that we can manipulate the PTE 1819 // level entries while the mapping is active. The first entry 1820 // covers the PTE[] page itself, the remaining entries are free 1821 // to be used as a ad-hoc fixmap. 1822 // 1823 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc), 1824 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL, 1825 kpti_ng_pgd_alloc, 0); 1826 } 1827 1828 cpu_install_idmap(); 1829 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA); 1830 cpu_uninstall_idmap(); 1831 1832 if (!cpu) { 1833 free_pages(alloc, order); 1834 arm64_use_ng_mappings = true; 1835 } 1836 1837 return 0; 1838 } 1839 1840 static void __init kpti_install_ng_mappings(void) 1841 { 1842 /* Check whether KPTI is going to be used */ 1843 if (!cpus_have_cap(ARM64_UNMAP_KERNEL_AT_EL0)) 1844 return; 1845 1846 /* 1847 * We don't need to rewrite the page-tables if either we've done 1848 * it already or we have KASLR enabled and therefore have not 1849 * created any global mappings at all. 1850 */ 1851 if (arm64_use_ng_mappings) 1852 return; 1853 1854 stop_machine(__kpti_install_ng_mappings, NULL, cpu_online_mask); 1855 } 1856 1857 #else 1858 static inline void kpti_install_ng_mappings(void) 1859 { 1860 } 1861 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1862 1863 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 1864 { 1865 if (__this_cpu_read(this_cpu_vector) == vectors) { 1866 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1867 1868 __this_cpu_write(this_cpu_vector, v); 1869 } 1870 1871 } 1872 1873 static int __init parse_kpti(char *str) 1874 { 1875 bool enabled; 1876 int ret = kstrtobool(str, &enabled); 1877 1878 if (ret) 1879 return ret; 1880 1881 __kpti_forced = enabled ? 1 : -1; 1882 return 0; 1883 } 1884 early_param("kpti", parse_kpti); 1885 1886 #ifdef CONFIG_ARM64_HW_AFDBM 1887 static struct cpumask dbm_cpus __read_mostly; 1888 1889 static inline void __cpu_enable_hw_dbm(void) 1890 { 1891 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1892 1893 write_sysreg(tcr, tcr_el1); 1894 isb(); 1895 local_flush_tlb_all(); 1896 } 1897 1898 static bool cpu_has_broken_dbm(void) 1899 { 1900 /* List of CPUs which have broken DBM support. */ 1901 static const struct midr_range cpus[] = { 1902 #ifdef CONFIG_ARM64_ERRATUM_1024718 1903 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1904 /* Kryo4xx Silver (rdpe => r1p0) */ 1905 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1906 #endif 1907 #ifdef CONFIG_ARM64_ERRATUM_2051678 1908 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 1909 #endif 1910 {}, 1911 }; 1912 1913 return is_midr_in_range_list(read_cpuid_id(), cpus); 1914 } 1915 1916 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1917 { 1918 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1919 !cpu_has_broken_dbm(); 1920 } 1921 1922 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1923 { 1924 if (cpu_can_use_dbm(cap)) { 1925 __cpu_enable_hw_dbm(); 1926 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 1927 } 1928 } 1929 1930 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1931 int __unused) 1932 { 1933 /* 1934 * DBM is a non-conflicting feature. i.e, the kernel can safely 1935 * run a mix of CPUs with and without the feature. So, we 1936 * unconditionally enable the capability to allow any late CPU 1937 * to use the feature. We only enable the control bits on the 1938 * CPU, if it is supported. 1939 */ 1940 1941 return true; 1942 } 1943 1944 #endif 1945 1946 #ifdef CONFIG_ARM64_AMU_EXTN 1947 1948 /* 1949 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1950 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1951 * information regarding all the events that it supports. When a CPU bit is 1952 * set in the cpumask, the user of this feature can only rely on the presence 1953 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1954 * counters are enabled or access to these counters is enabled by code 1955 * executed at higher exception levels (firmware). 1956 */ 1957 static struct cpumask amu_cpus __read_mostly; 1958 1959 bool cpu_has_amu_feat(int cpu) 1960 { 1961 return cpumask_test_cpu(cpu, &amu_cpus); 1962 } 1963 1964 int get_cpu_with_amu_feat(void) 1965 { 1966 return cpumask_any(&amu_cpus); 1967 } 1968 1969 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1970 { 1971 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1972 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1973 1974 /* 0 reference values signal broken/disabled counters */ 1975 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 1976 update_freq_counters_refs(); 1977 } 1978 } 1979 1980 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1981 int __unused) 1982 { 1983 /* 1984 * The AMU extension is a non-conflicting feature: the kernel can 1985 * safely run a mix of CPUs with and without support for the 1986 * activity monitors extension. Therefore, unconditionally enable 1987 * the capability to allow any late CPU to use the feature. 1988 * 1989 * With this feature unconditionally enabled, the cpu_enable 1990 * function will be called for all CPUs that match the criteria, 1991 * including secondary and hotplugged, marking this feature as 1992 * present on that respective CPU. The enable function will also 1993 * print a detection message. 1994 */ 1995 1996 return true; 1997 } 1998 #else 1999 int get_cpu_with_amu_feat(void) 2000 { 2001 return nr_cpu_ids; 2002 } 2003 #endif 2004 2005 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 2006 { 2007 return is_kernel_in_hyp_mode(); 2008 } 2009 2010 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 2011 { 2012 /* 2013 * Copy register values that aren't redirected by hardware. 2014 * 2015 * Before code patching, we only set tpidr_el1, all CPUs need to copy 2016 * this value to tpidr_el2 before we patch the code. Once we've done 2017 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 2018 * do anything here. 2019 */ 2020 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 2021 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 2022 } 2023 2024 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 2025 int scope) 2026 { 2027 if (kvm_get_mode() != KVM_MODE_NV) 2028 return false; 2029 2030 if (!has_cpuid_feature(cap, scope)) { 2031 pr_warn("unavailable: %s\n", cap->desc); 2032 return false; 2033 } 2034 2035 return true; 2036 } 2037 2038 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2039 int __unused) 2040 { 2041 u64 val; 2042 2043 val = read_sysreg(id_aa64mmfr1_el1); 2044 if (!cpuid_feature_extract_unsigned_field(val, ID_AA64MMFR1_EL1_VH_SHIFT)) 2045 return false; 2046 2047 val = arm64_sw_feature_override.val & arm64_sw_feature_override.mask; 2048 return cpuid_feature_extract_unsigned_field(val, ARM64_SW_FEATURE_OVERRIDE_HVHE); 2049 } 2050 2051 #ifdef CONFIG_ARM64_PAN 2052 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2053 { 2054 /* 2055 * We modify PSTATE. This won't work from irq context as the PSTATE 2056 * is discarded once we return from the exception. 2057 */ 2058 WARN_ON_ONCE(in_interrupt()); 2059 2060 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2061 set_pstate_pan(1); 2062 } 2063 #endif /* CONFIG_ARM64_PAN */ 2064 2065 #ifdef CONFIG_ARM64_RAS_EXTN 2066 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2067 { 2068 /* Firmware may have left a deferred SError in this register. */ 2069 write_sysreg_s(0, SYS_DISR_EL1); 2070 } 2071 #endif /* CONFIG_ARM64_RAS_EXTN */ 2072 2073 #ifdef CONFIG_ARM64_PTR_AUTH 2074 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2075 { 2076 int boot_val, sec_val; 2077 2078 /* We don't expect to be called with SCOPE_SYSTEM */ 2079 WARN_ON(scope == SCOPE_SYSTEM); 2080 /* 2081 * The ptr-auth feature levels are not intercompatible with lower 2082 * levels. Hence we must match ptr-auth feature level of the secondary 2083 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2084 * from the sanitised register whereas direct register read is done for 2085 * the secondary CPUs. 2086 * The sanitised feature state is guaranteed to match that of the 2087 * boot CPU as a mismatched secondary CPU is parked before it gets 2088 * a chance to update the state, with the capability. 2089 */ 2090 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2091 entry->field_pos, entry->sign); 2092 if (scope & SCOPE_BOOT_CPU) 2093 return boot_val >= entry->min_field_value; 2094 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2095 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2096 entry->field_pos, entry->sign); 2097 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2098 } 2099 2100 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2101 int scope) 2102 { 2103 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2104 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2105 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2106 2107 return apa || apa3 || api; 2108 } 2109 2110 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2111 int __unused) 2112 { 2113 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2114 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2115 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2116 2117 return gpa || gpa3 || gpi; 2118 } 2119 #endif /* CONFIG_ARM64_PTR_AUTH */ 2120 2121 #ifdef CONFIG_ARM64_E0PD 2122 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2123 { 2124 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2125 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 2126 } 2127 #endif /* CONFIG_ARM64_E0PD */ 2128 2129 #ifdef CONFIG_ARM64_PSEUDO_NMI 2130 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2131 int scope) 2132 { 2133 /* 2134 * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU 2135 * feature, so will be detected earlier. 2136 */ 2137 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS); 2138 if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS)) 2139 return false; 2140 2141 return enable_pseudo_nmi; 2142 } 2143 2144 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2145 int scope) 2146 { 2147 /* 2148 * If we're not using priority masking then we won't be poking PMR_EL1, 2149 * and there's no need to relax synchronization of writes to it, and 2150 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2151 * that. 2152 * 2153 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2154 * feature, so will be detected earlier. 2155 */ 2156 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2157 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2158 return false; 2159 2160 /* 2161 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2162 * hint for interrupt distribution, a DSB is not necessary when 2163 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2164 * 2165 * Linux itself doesn't use 1:N distribution, so has no need to 2166 * set PMHE. The only reason to have it set is if EL3 requires it 2167 * (and we can't change it). 2168 */ 2169 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2170 } 2171 #endif 2172 2173 #ifdef CONFIG_ARM64_BTI 2174 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2175 { 2176 /* 2177 * Use of X16/X17 for tail-calls and trampolines that jump to 2178 * function entry points using BR is a requirement for 2179 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2180 * So, be strict and forbid other BRs using other registers to 2181 * jump onto a PACIxSP instruction: 2182 */ 2183 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2184 isb(); 2185 } 2186 #endif /* CONFIG_ARM64_BTI */ 2187 2188 #ifdef CONFIG_ARM64_MTE 2189 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2190 { 2191 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2192 2193 mte_cpu_setup(); 2194 2195 /* 2196 * Clear the tags in the zero page. This needs to be done via the 2197 * linear map which has the Tagged attribute. 2198 */ 2199 if (try_page_mte_tagging(ZERO_PAGE(0))) { 2200 mte_clear_page_tags(lm_alias(empty_zero_page)); 2201 set_page_mte_tagged(ZERO_PAGE(0)); 2202 } 2203 2204 kasan_init_hw_tags_cpu(); 2205 } 2206 #endif /* CONFIG_ARM64_MTE */ 2207 2208 static void user_feature_fixup(void) 2209 { 2210 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2211 struct arm64_ftr_reg *regp; 2212 2213 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2214 if (regp) 2215 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2216 } 2217 } 2218 2219 static void elf_hwcap_fixup(void) 2220 { 2221 #ifdef CONFIG_COMPAT 2222 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2223 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2224 #endif /* CONFIG_COMPAT */ 2225 } 2226 2227 #ifdef CONFIG_KVM 2228 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2229 { 2230 return kvm_get_mode() == KVM_MODE_PROTECTED; 2231 } 2232 #endif /* CONFIG_KVM */ 2233 2234 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2235 { 2236 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2237 } 2238 2239 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2240 { 2241 set_pstate_dit(1); 2242 } 2243 2244 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2245 { 2246 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2247 } 2248 2249 /* Internal helper functions to match cpu capability type */ 2250 static bool 2251 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2252 { 2253 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2254 } 2255 2256 static bool 2257 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2258 { 2259 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2260 } 2261 2262 static bool 2263 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2264 { 2265 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2266 } 2267 2268 static const struct arm64_cpu_capabilities arm64_features[] = { 2269 { 2270 .capability = ARM64_ALWAYS_BOOT, 2271 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2272 .matches = has_always, 2273 }, 2274 { 2275 .capability = ARM64_ALWAYS_SYSTEM, 2276 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2277 .matches = has_always, 2278 }, 2279 { 2280 .desc = "GIC system register CPU interface", 2281 .capability = ARM64_HAS_GIC_CPUIF_SYSREGS, 2282 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2283 .matches = has_useable_gicv3_cpuif, 2284 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2285 }, 2286 { 2287 .desc = "Enhanced Counter Virtualization", 2288 .capability = ARM64_HAS_ECV, 2289 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2290 .matches = has_cpuid_feature, 2291 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2292 }, 2293 { 2294 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2295 .capability = ARM64_HAS_ECV_CNTPOFF, 2296 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2297 .matches = has_cpuid_feature, 2298 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2299 }, 2300 #ifdef CONFIG_ARM64_PAN 2301 { 2302 .desc = "Privileged Access Never", 2303 .capability = ARM64_HAS_PAN, 2304 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2305 .matches = has_cpuid_feature, 2306 .cpu_enable = cpu_enable_pan, 2307 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2308 }, 2309 #endif /* CONFIG_ARM64_PAN */ 2310 #ifdef CONFIG_ARM64_EPAN 2311 { 2312 .desc = "Enhanced Privileged Access Never", 2313 .capability = ARM64_HAS_EPAN, 2314 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2315 .matches = has_cpuid_feature, 2316 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2317 }, 2318 #endif /* CONFIG_ARM64_EPAN */ 2319 #ifdef CONFIG_ARM64_LSE_ATOMICS 2320 { 2321 .desc = "LSE atomic instructions", 2322 .capability = ARM64_HAS_LSE_ATOMICS, 2323 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2324 .matches = has_cpuid_feature, 2325 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2326 }, 2327 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2328 { 2329 .desc = "Software prefetching using PRFM", 2330 .capability = ARM64_HAS_NO_HW_PREFETCH, 2331 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2332 .matches = has_no_hw_prefetch, 2333 }, 2334 { 2335 .desc = "Virtualization Host Extensions", 2336 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2337 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2338 .matches = runs_at_el2, 2339 .cpu_enable = cpu_copy_el2regs, 2340 }, 2341 { 2342 .desc = "Nested Virtualization Support", 2343 .capability = ARM64_HAS_NESTED_VIRT, 2344 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2345 .matches = has_nested_virt_support, 2346 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, IMP) 2347 }, 2348 { 2349 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2350 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2351 .matches = has_32bit_el0, 2352 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2353 }, 2354 #ifdef CONFIG_KVM 2355 { 2356 .desc = "32-bit EL1 Support", 2357 .capability = ARM64_HAS_32BIT_EL1, 2358 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2359 .matches = has_cpuid_feature, 2360 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2361 }, 2362 { 2363 .desc = "Protected KVM", 2364 .capability = ARM64_KVM_PROTECTED_MODE, 2365 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2366 .matches = is_kvm_protected_mode, 2367 }, 2368 { 2369 .desc = "HCRX_EL2 register", 2370 .capability = ARM64_HAS_HCX, 2371 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2372 .matches = has_cpuid_feature, 2373 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2374 }, 2375 #endif 2376 { 2377 .desc = "Kernel page table isolation (KPTI)", 2378 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2379 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2380 .cpu_enable = cpu_enable_kpti, 2381 .matches = unmap_kernel_at_el0, 2382 /* 2383 * The ID feature fields below are used to indicate that 2384 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2385 * more details. 2386 */ 2387 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2388 }, 2389 { 2390 .capability = ARM64_HAS_FPSIMD, 2391 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2392 .matches = has_cpuid_feature, 2393 .cpu_enable = cpu_enable_fpsimd, 2394 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2395 }, 2396 #ifdef CONFIG_ARM64_PMEM 2397 { 2398 .desc = "Data cache clean to Point of Persistence", 2399 .capability = ARM64_HAS_DCPOP, 2400 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2401 .matches = has_cpuid_feature, 2402 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2403 }, 2404 { 2405 .desc = "Data cache clean to Point of Deep Persistence", 2406 .capability = ARM64_HAS_DCPODP, 2407 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2408 .matches = has_cpuid_feature, 2409 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2410 }, 2411 #endif 2412 #ifdef CONFIG_ARM64_SVE 2413 { 2414 .desc = "Scalable Vector Extension", 2415 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2416 .capability = ARM64_SVE, 2417 .cpu_enable = cpu_enable_sve, 2418 .matches = has_cpuid_feature, 2419 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2420 }, 2421 #endif /* CONFIG_ARM64_SVE */ 2422 #ifdef CONFIG_ARM64_RAS_EXTN 2423 { 2424 .desc = "RAS Extension Support", 2425 .capability = ARM64_HAS_RAS_EXTN, 2426 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2427 .matches = has_cpuid_feature, 2428 .cpu_enable = cpu_clear_disr, 2429 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2430 }, 2431 #endif /* CONFIG_ARM64_RAS_EXTN */ 2432 #ifdef CONFIG_ARM64_AMU_EXTN 2433 { 2434 .desc = "Activity Monitors Unit (AMU)", 2435 .capability = ARM64_HAS_AMU_EXTN, 2436 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2437 .matches = has_amu, 2438 .cpu_enable = cpu_amu_enable, 2439 .cpus = &amu_cpus, 2440 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2441 }, 2442 #endif /* CONFIG_ARM64_AMU_EXTN */ 2443 { 2444 .desc = "Data cache clean to the PoU not required for I/D coherence", 2445 .capability = ARM64_HAS_CACHE_IDC, 2446 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2447 .matches = has_cache_idc, 2448 .cpu_enable = cpu_emulate_effective_ctr, 2449 }, 2450 { 2451 .desc = "Instruction cache invalidation not required for I/D coherence", 2452 .capability = ARM64_HAS_CACHE_DIC, 2453 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2454 .matches = has_cache_dic, 2455 }, 2456 { 2457 .desc = "Stage-2 Force Write-Back", 2458 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2459 .capability = ARM64_HAS_STAGE2_FWB, 2460 .matches = has_cpuid_feature, 2461 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2462 }, 2463 { 2464 .desc = "ARMv8.4 Translation Table Level", 2465 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2466 .capability = ARM64_HAS_ARMv8_4_TTL, 2467 .matches = has_cpuid_feature, 2468 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2469 }, 2470 { 2471 .desc = "TLB range maintenance instructions", 2472 .capability = ARM64_HAS_TLB_RANGE, 2473 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2474 .matches = has_cpuid_feature, 2475 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2476 }, 2477 #ifdef CONFIG_ARM64_HW_AFDBM 2478 { 2479 .desc = "Hardware dirty bit management", 2480 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2481 .capability = ARM64_HW_DBM, 2482 .matches = has_hw_dbm, 2483 .cpu_enable = cpu_enable_hw_dbm, 2484 .cpus = &dbm_cpus, 2485 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2486 }, 2487 #endif 2488 { 2489 .desc = "CRC32 instructions", 2490 .capability = ARM64_HAS_CRC32, 2491 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2492 .matches = has_cpuid_feature, 2493 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2494 }, 2495 { 2496 .desc = "Speculative Store Bypassing Safe (SSBS)", 2497 .capability = ARM64_SSBS, 2498 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2499 .matches = has_cpuid_feature, 2500 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2501 }, 2502 #ifdef CONFIG_ARM64_CNP 2503 { 2504 .desc = "Common not Private translations", 2505 .capability = ARM64_HAS_CNP, 2506 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2507 .matches = has_useable_cnp, 2508 .cpu_enable = cpu_enable_cnp, 2509 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2510 }, 2511 #endif 2512 { 2513 .desc = "Speculation barrier (SB)", 2514 .capability = ARM64_HAS_SB, 2515 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2516 .matches = has_cpuid_feature, 2517 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2518 }, 2519 #ifdef CONFIG_ARM64_PTR_AUTH 2520 { 2521 .desc = "Address authentication (architected QARMA5 algorithm)", 2522 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2523 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2524 .matches = has_address_auth_cpucap, 2525 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2526 }, 2527 { 2528 .desc = "Address authentication (architected QARMA3 algorithm)", 2529 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2530 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2531 .matches = has_address_auth_cpucap, 2532 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2533 }, 2534 { 2535 .desc = "Address authentication (IMP DEF algorithm)", 2536 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2537 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2538 .matches = has_address_auth_cpucap, 2539 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2540 }, 2541 { 2542 .capability = ARM64_HAS_ADDRESS_AUTH, 2543 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2544 .matches = has_address_auth_metacap, 2545 }, 2546 { 2547 .desc = "Generic authentication (architected QARMA5 algorithm)", 2548 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2549 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2550 .matches = has_cpuid_feature, 2551 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2552 }, 2553 { 2554 .desc = "Generic authentication (architected QARMA3 algorithm)", 2555 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2556 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2557 .matches = has_cpuid_feature, 2558 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2559 }, 2560 { 2561 .desc = "Generic authentication (IMP DEF algorithm)", 2562 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2563 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2564 .matches = has_cpuid_feature, 2565 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2566 }, 2567 { 2568 .capability = ARM64_HAS_GENERIC_AUTH, 2569 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2570 .matches = has_generic_auth, 2571 }, 2572 #endif /* CONFIG_ARM64_PTR_AUTH */ 2573 #ifdef CONFIG_ARM64_PSEUDO_NMI 2574 { 2575 /* 2576 * Depends on having GICv3 2577 */ 2578 .desc = "IRQ priority masking", 2579 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2580 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2581 .matches = can_use_gic_priorities, 2582 }, 2583 { 2584 /* 2585 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2586 */ 2587 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2588 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2589 .matches = has_gic_prio_relaxed_sync, 2590 }, 2591 #endif 2592 #ifdef CONFIG_ARM64_E0PD 2593 { 2594 .desc = "E0PD", 2595 .capability = ARM64_HAS_E0PD, 2596 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2597 .cpu_enable = cpu_enable_e0pd, 2598 .matches = has_cpuid_feature, 2599 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2600 }, 2601 #endif 2602 { 2603 .desc = "Random Number Generator", 2604 .capability = ARM64_HAS_RNG, 2605 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2606 .matches = has_cpuid_feature, 2607 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2608 }, 2609 #ifdef CONFIG_ARM64_BTI 2610 { 2611 .desc = "Branch Target Identification", 2612 .capability = ARM64_BTI, 2613 #ifdef CONFIG_ARM64_BTI_KERNEL 2614 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2615 #else 2616 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2617 #endif 2618 .matches = has_cpuid_feature, 2619 .cpu_enable = bti_enable, 2620 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2621 }, 2622 #endif 2623 #ifdef CONFIG_ARM64_MTE 2624 { 2625 .desc = "Memory Tagging Extension", 2626 .capability = ARM64_MTE, 2627 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2628 .matches = has_cpuid_feature, 2629 .cpu_enable = cpu_enable_mte, 2630 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2631 }, 2632 { 2633 .desc = "Asymmetric MTE Tag Check Fault", 2634 .capability = ARM64_MTE_ASYMM, 2635 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2636 .matches = has_cpuid_feature, 2637 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2638 }, 2639 #endif /* CONFIG_ARM64_MTE */ 2640 { 2641 .desc = "RCpc load-acquire (LDAPR)", 2642 .capability = ARM64_HAS_LDAPR, 2643 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2644 .matches = has_cpuid_feature, 2645 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2646 }, 2647 { 2648 .desc = "Fine Grained Traps", 2649 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2650 .capability = ARM64_HAS_FGT, 2651 .matches = has_cpuid_feature, 2652 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2653 }, 2654 #ifdef CONFIG_ARM64_SME 2655 { 2656 .desc = "Scalable Matrix Extension", 2657 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2658 .capability = ARM64_SME, 2659 .matches = has_cpuid_feature, 2660 .cpu_enable = cpu_enable_sme, 2661 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2662 }, 2663 /* FA64 should be sorted after the base SME capability */ 2664 { 2665 .desc = "FA64", 2666 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2667 .capability = ARM64_SME_FA64, 2668 .matches = has_cpuid_feature, 2669 .cpu_enable = cpu_enable_fa64, 2670 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2671 }, 2672 { 2673 .desc = "SME2", 2674 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2675 .capability = ARM64_SME2, 2676 .matches = has_cpuid_feature, 2677 .cpu_enable = cpu_enable_sme2, 2678 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2679 }, 2680 #endif /* CONFIG_ARM64_SME */ 2681 { 2682 .desc = "WFx with timeout", 2683 .capability = ARM64_HAS_WFXT, 2684 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2685 .matches = has_cpuid_feature, 2686 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 2687 }, 2688 { 2689 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2690 .capability = ARM64_HAS_TIDCP1, 2691 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2692 .matches = has_cpuid_feature, 2693 .cpu_enable = cpu_trap_el0_impdef, 2694 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 2695 }, 2696 { 2697 .desc = "Data independent timing control (DIT)", 2698 .capability = ARM64_HAS_DIT, 2699 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2700 .matches = has_cpuid_feature, 2701 .cpu_enable = cpu_enable_dit, 2702 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 2703 }, 2704 { 2705 .desc = "Memory Copy and Memory Set instructions", 2706 .capability = ARM64_HAS_MOPS, 2707 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2708 .matches = has_cpuid_feature, 2709 .cpu_enable = cpu_enable_mops, 2710 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 2711 }, 2712 { 2713 .capability = ARM64_HAS_TCR2, 2714 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2715 .matches = has_cpuid_feature, 2716 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 2717 }, 2718 { 2719 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 2720 .capability = ARM64_HAS_S1PIE, 2721 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2722 .matches = has_cpuid_feature, 2723 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 2724 }, 2725 { 2726 .desc = "VHE for hypervisor only", 2727 .capability = ARM64_KVM_HVHE, 2728 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2729 .matches = hvhe_possible, 2730 }, 2731 { 2732 .desc = "Enhanced Virtualization Traps", 2733 .capability = ARM64_HAS_EVT, 2734 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2735 .matches = has_cpuid_feature, 2736 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 2737 }, 2738 {}, 2739 }; 2740 2741 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 2742 .matches = has_user_cpuid_feature, \ 2743 ARM64_CPUID_FIELDS(reg, field, min_value) 2744 2745 #define __HWCAP_CAP(name, cap_type, cap) \ 2746 .desc = name, \ 2747 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2748 .hwcap_type = cap_type, \ 2749 .hwcap = cap, \ 2750 2751 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 2752 { \ 2753 __HWCAP_CAP(#cap, cap_type, cap) \ 2754 HWCAP_CPUID_MATCH(reg, field, min_value) \ 2755 } 2756 2757 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2758 { \ 2759 __HWCAP_CAP(#cap, cap_type, cap) \ 2760 .matches = cpucap_multi_entry_cap_matches, \ 2761 .match_list = list, \ 2762 } 2763 2764 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2765 { \ 2766 __HWCAP_CAP(#cap, cap_type, cap) \ 2767 .matches = match, \ 2768 } 2769 2770 #ifdef CONFIG_ARM64_PTR_AUTH 2771 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2772 { 2773 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 2774 }, 2775 { 2776 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 2777 }, 2778 { 2779 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 2780 }, 2781 {}, 2782 }; 2783 2784 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2785 { 2786 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 2787 }, 2788 { 2789 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 2790 }, 2791 { 2792 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 2793 }, 2794 {}, 2795 }; 2796 #endif 2797 2798 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2799 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2800 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 2801 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2802 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2803 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2804 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2805 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2806 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 2807 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2808 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2809 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 2810 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 2811 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2812 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2813 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2814 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2815 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 2816 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 2817 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2818 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2819 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2820 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 2821 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2822 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2823 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2824 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2825 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2826 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2827 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 2828 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2829 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 2830 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 2831 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 2832 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 2833 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2834 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2835 #ifdef CONFIG_ARM64_SVE 2836 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 2837 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 2838 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2839 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2840 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2841 HWCAP_CAP(ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 2842 HWCAP_CAP(ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 2843 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 2844 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 2845 HWCAP_CAP(ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 2846 HWCAP_CAP(ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 2847 HWCAP_CAP(ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 2848 HWCAP_CAP(ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 2849 HWCAP_CAP(ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 2850 #endif 2851 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 2852 #ifdef CONFIG_ARM64_BTI 2853 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 2854 #endif 2855 #ifdef CONFIG_ARM64_PTR_AUTH 2856 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 2857 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 2858 #endif 2859 #ifdef CONFIG_ARM64_MTE 2860 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 2861 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 2862 #endif /* CONFIG_ARM64_MTE */ 2863 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 2864 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 2865 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 2866 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 2867 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 2868 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 2869 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 2870 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 2871 #ifdef CONFIG_ARM64_SME 2872 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 2873 HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 2874 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 2875 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 2876 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 2877 HWCAP_CAP(ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 2878 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 2879 HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 2880 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 2881 HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 2882 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 2883 HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 2884 HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 2885 HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 2886 #endif /* CONFIG_ARM64_SME */ 2887 {}, 2888 }; 2889 2890 #ifdef CONFIG_COMPAT 2891 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 2892 { 2893 /* 2894 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 2895 * in line with that of arm32 as in vfp_init(). We make sure that the 2896 * check is future proof, by making sure value is non-zero. 2897 */ 2898 u32 mvfr1; 2899 2900 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 2901 if (scope == SCOPE_SYSTEM) 2902 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 2903 else 2904 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 2905 2906 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 2907 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 2908 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 2909 } 2910 #endif 2911 2912 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 2913 #ifdef CONFIG_COMPAT 2914 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 2915 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 2916 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 2917 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 2918 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 2919 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 2920 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 2921 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 2922 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 2923 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 2924 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 2925 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 2926 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 2927 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 2928 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 2929 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 2930 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 2931 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 2932 #endif 2933 {}, 2934 }; 2935 2936 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2937 { 2938 switch (cap->hwcap_type) { 2939 case CAP_HWCAP: 2940 cpu_set_feature(cap->hwcap); 2941 break; 2942 #ifdef CONFIG_COMPAT 2943 case CAP_COMPAT_HWCAP: 2944 compat_elf_hwcap |= (u32)cap->hwcap; 2945 break; 2946 case CAP_COMPAT_HWCAP2: 2947 compat_elf_hwcap2 |= (u32)cap->hwcap; 2948 break; 2949 #endif 2950 default: 2951 WARN_ON(1); 2952 break; 2953 } 2954 } 2955 2956 /* Check if we have a particular HWCAP enabled */ 2957 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2958 { 2959 bool rc; 2960 2961 switch (cap->hwcap_type) { 2962 case CAP_HWCAP: 2963 rc = cpu_have_feature(cap->hwcap); 2964 break; 2965 #ifdef CONFIG_COMPAT 2966 case CAP_COMPAT_HWCAP: 2967 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 2968 break; 2969 case CAP_COMPAT_HWCAP2: 2970 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 2971 break; 2972 #endif 2973 default: 2974 WARN_ON(1); 2975 rc = false; 2976 } 2977 2978 return rc; 2979 } 2980 2981 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 2982 { 2983 /* We support emulation of accesses to CPU ID feature registers */ 2984 cpu_set_named_feature(CPUID); 2985 for (; hwcaps->matches; hwcaps++) 2986 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 2987 cap_set_elf_hwcap(hwcaps); 2988 } 2989 2990 static void update_cpu_capabilities(u16 scope_mask) 2991 { 2992 int i; 2993 const struct arm64_cpu_capabilities *caps; 2994 2995 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2996 for (i = 0; i < ARM64_NCAPS; i++) { 2997 caps = cpucap_ptrs[i]; 2998 if (!caps || !(caps->type & scope_mask) || 2999 cpus_have_cap(caps->capability) || 3000 !caps->matches(caps, cpucap_default_scope(caps))) 3001 continue; 3002 3003 if (caps->desc && !caps->cpus) 3004 pr_info("detected: %s\n", caps->desc); 3005 3006 __set_bit(caps->capability, system_cpucaps); 3007 3008 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 3009 set_bit(caps->capability, boot_cpucaps); 3010 } 3011 } 3012 3013 /* 3014 * Enable all the available capabilities on this CPU. The capabilities 3015 * with BOOT_CPU scope are handled separately and hence skipped here. 3016 */ 3017 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3018 { 3019 int i; 3020 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3021 3022 for_each_available_cap(i) { 3023 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3024 3025 if (WARN_ON(!cap)) 3026 continue; 3027 3028 if (!(cap->type & non_boot_scope)) 3029 continue; 3030 3031 if (cap->cpu_enable) 3032 cap->cpu_enable(cap); 3033 } 3034 return 0; 3035 } 3036 3037 /* 3038 * Run through the enabled capabilities and enable() it on all active 3039 * CPUs 3040 */ 3041 static void __init enable_cpu_capabilities(u16 scope_mask) 3042 { 3043 int i; 3044 const struct arm64_cpu_capabilities *caps; 3045 bool boot_scope; 3046 3047 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3048 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3049 3050 for (i = 0; i < ARM64_NCAPS; i++) { 3051 unsigned int num; 3052 3053 caps = cpucap_ptrs[i]; 3054 if (!caps || !(caps->type & scope_mask)) 3055 continue; 3056 num = caps->capability; 3057 if (!cpus_have_cap(num)) 3058 continue; 3059 3060 if (boot_scope && caps->cpu_enable) 3061 /* 3062 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3063 * before any secondary CPU boots. Thus, each secondary 3064 * will enable the capability as appropriate via 3065 * check_local_cpu_capabilities(). The only exception is 3066 * the boot CPU, for which the capability must be 3067 * enabled here. This approach avoids costly 3068 * stop_machine() calls for this case. 3069 */ 3070 caps->cpu_enable(caps); 3071 } 3072 3073 /* 3074 * For all non-boot scope capabilities, use stop_machine() 3075 * as it schedules the work allowing us to modify PSTATE, 3076 * instead of on_each_cpu() which uses an IPI, giving us a 3077 * PSTATE that disappears when we return. 3078 */ 3079 if (!boot_scope) 3080 stop_machine(cpu_enable_non_boot_scope_capabilities, 3081 NULL, cpu_online_mask); 3082 } 3083 3084 /* 3085 * Run through the list of capabilities to check for conflicts. 3086 * If the system has already detected a capability, take necessary 3087 * action on this CPU. 3088 */ 3089 static void verify_local_cpu_caps(u16 scope_mask) 3090 { 3091 int i; 3092 bool cpu_has_cap, system_has_cap; 3093 const struct arm64_cpu_capabilities *caps; 3094 3095 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3096 3097 for (i = 0; i < ARM64_NCAPS; i++) { 3098 caps = cpucap_ptrs[i]; 3099 if (!caps || !(caps->type & scope_mask)) 3100 continue; 3101 3102 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3103 system_has_cap = cpus_have_cap(caps->capability); 3104 3105 if (system_has_cap) { 3106 /* 3107 * Check if the new CPU misses an advertised feature, 3108 * which is not safe to miss. 3109 */ 3110 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3111 break; 3112 /* 3113 * We have to issue cpu_enable() irrespective of 3114 * whether the CPU has it or not, as it is enabeld 3115 * system wide. It is upto the call back to take 3116 * appropriate action on this CPU. 3117 */ 3118 if (caps->cpu_enable) 3119 caps->cpu_enable(caps); 3120 } else { 3121 /* 3122 * Check if the CPU has this capability if it isn't 3123 * safe to have when the system doesn't. 3124 */ 3125 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3126 break; 3127 } 3128 } 3129 3130 if (i < ARM64_NCAPS) { 3131 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3132 smp_processor_id(), caps->capability, 3133 caps->desc, system_has_cap, cpu_has_cap); 3134 3135 if (cpucap_panic_on_conflict(caps)) 3136 cpu_panic_kernel(); 3137 else 3138 cpu_die_early(); 3139 } 3140 } 3141 3142 /* 3143 * Check for CPU features that are used in early boot 3144 * based on the Boot CPU value. 3145 */ 3146 static void check_early_cpu_features(void) 3147 { 3148 verify_cpu_asid_bits(); 3149 3150 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3151 } 3152 3153 static void 3154 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3155 { 3156 3157 for (; caps->matches; caps++) 3158 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3159 pr_crit("CPU%d: missing HWCAP: %s\n", 3160 smp_processor_id(), caps->desc); 3161 cpu_die_early(); 3162 } 3163 } 3164 3165 static void verify_local_elf_hwcaps(void) 3166 { 3167 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3168 3169 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3170 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3171 } 3172 3173 static void verify_sve_features(void) 3174 { 3175 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3176 3177 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3178 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3179 smp_processor_id()); 3180 cpu_die_early(); 3181 } 3182 3183 cpacr_restore(cpacr); 3184 } 3185 3186 static void verify_sme_features(void) 3187 { 3188 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3189 3190 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3191 pr_crit("CPU%d: SME: vector length support mismatch\n", 3192 smp_processor_id()); 3193 cpu_die_early(); 3194 } 3195 3196 cpacr_restore(cpacr); 3197 } 3198 3199 static void verify_hyp_capabilities(void) 3200 { 3201 u64 safe_mmfr1, mmfr0, mmfr1; 3202 int parange, ipa_max; 3203 unsigned int safe_vmid_bits, vmid_bits; 3204 3205 if (!IS_ENABLED(CONFIG_KVM)) 3206 return; 3207 3208 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3209 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 3210 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3211 3212 /* Verify VMID bits */ 3213 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3214 vmid_bits = get_vmid_bits(mmfr1); 3215 if (vmid_bits < safe_vmid_bits) { 3216 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3217 cpu_die_early(); 3218 } 3219 3220 /* Verify IPA range */ 3221 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3222 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3223 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3224 if (ipa_max < get_kvm_ipa_limit()) { 3225 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3226 cpu_die_early(); 3227 } 3228 } 3229 3230 /* 3231 * Run through the enabled system capabilities and enable() it on this CPU. 3232 * The capabilities were decided based on the available CPUs at the boot time. 3233 * Any new CPU should match the system wide status of the capability. If the 3234 * new CPU doesn't have a capability which the system now has enabled, we 3235 * cannot do anything to fix it up and could cause unexpected failures. So 3236 * we park the CPU. 3237 */ 3238 static void verify_local_cpu_capabilities(void) 3239 { 3240 /* 3241 * The capabilities with SCOPE_BOOT_CPU are checked from 3242 * check_early_cpu_features(), as they need to be verified 3243 * on all secondary CPUs. 3244 */ 3245 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3246 verify_local_elf_hwcaps(); 3247 3248 if (system_supports_sve()) 3249 verify_sve_features(); 3250 3251 if (system_supports_sme()) 3252 verify_sme_features(); 3253 3254 if (is_hyp_mode_available()) 3255 verify_hyp_capabilities(); 3256 } 3257 3258 void check_local_cpu_capabilities(void) 3259 { 3260 /* 3261 * All secondary CPUs should conform to the early CPU features 3262 * in use by the kernel based on boot CPU. 3263 */ 3264 check_early_cpu_features(); 3265 3266 /* 3267 * If we haven't finalised the system capabilities, this CPU gets 3268 * a chance to update the errata work arounds and local features. 3269 * Otherwise, this CPU should verify that it has all the system 3270 * advertised capabilities. 3271 */ 3272 if (!system_capabilities_finalized()) 3273 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3274 else 3275 verify_local_cpu_capabilities(); 3276 } 3277 3278 static void __init setup_boot_cpu_capabilities(void) 3279 { 3280 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 3281 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3282 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 3283 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3284 } 3285 3286 bool this_cpu_has_cap(unsigned int n) 3287 { 3288 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3289 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3290 3291 if (cap) 3292 return cap->matches(cap, SCOPE_LOCAL_CPU); 3293 } 3294 3295 return false; 3296 } 3297 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3298 3299 /* 3300 * This helper function is used in a narrow window when, 3301 * - The system wide safe registers are set with all the SMP CPUs and, 3302 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3303 */ 3304 static bool __maybe_unused __system_matches_cap(unsigned int n) 3305 { 3306 if (n < ARM64_NCAPS) { 3307 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3308 3309 if (cap) 3310 return cap->matches(cap, SCOPE_SYSTEM); 3311 } 3312 return false; 3313 } 3314 3315 void cpu_set_feature(unsigned int num) 3316 { 3317 set_bit(num, elf_hwcap); 3318 } 3319 3320 bool cpu_have_feature(unsigned int num) 3321 { 3322 return test_bit(num, elf_hwcap); 3323 } 3324 EXPORT_SYMBOL_GPL(cpu_have_feature); 3325 3326 unsigned long cpu_get_elf_hwcap(void) 3327 { 3328 /* 3329 * We currently only populate the first 32 bits of AT_HWCAP. Please 3330 * note that for userspace compatibility we guarantee that bits 62 3331 * and 63 will always be returned as 0. 3332 */ 3333 return elf_hwcap[0]; 3334 } 3335 3336 unsigned long cpu_get_elf_hwcap2(void) 3337 { 3338 return elf_hwcap[1]; 3339 } 3340 3341 void __init setup_system_features(void) 3342 { 3343 int i; 3344 /* 3345 * The system-wide safe feature feature register values have been 3346 * finalized. Finalize and log the available system capabilities. 3347 */ 3348 update_cpu_capabilities(SCOPE_SYSTEM); 3349 if (IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) && 3350 !cpus_have_cap(ARM64_HAS_PAN)) 3351 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3352 3353 /* 3354 * Enable all the available capabilities which have not been enabled 3355 * already. 3356 */ 3357 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3358 3359 kpti_install_ng_mappings(); 3360 3361 sve_setup(); 3362 sme_setup(); 3363 3364 /* 3365 * Check for sane CTR_EL0.CWG value. 3366 */ 3367 if (!cache_type_cwg()) 3368 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3369 ARCH_DMA_MINALIGN); 3370 3371 for (i = 0; i < ARM64_NCAPS; i++) { 3372 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 3373 3374 if (caps && caps->cpus && caps->desc && 3375 cpumask_any(caps->cpus) < nr_cpu_ids) 3376 pr_info("detected: %s on CPU%*pbl\n", 3377 caps->desc, cpumask_pr_args(caps->cpus)); 3378 } 3379 } 3380 3381 void __init setup_user_features(void) 3382 { 3383 user_feature_fixup(); 3384 3385 setup_elf_hwcaps(arm64_elf_hwcaps); 3386 3387 if (system_supports_32bit_el0()) { 3388 setup_elf_hwcaps(compat_elf_hwcaps); 3389 elf_hwcap_fixup(); 3390 } 3391 3392 minsigstksz_setup(); 3393 } 3394 3395 static int enable_mismatched_32bit_el0(unsigned int cpu) 3396 { 3397 /* 3398 * The first 32-bit-capable CPU we detected and so can no longer 3399 * be offlined by userspace. -1 indicates we haven't yet onlined 3400 * a 32-bit-capable CPU. 3401 */ 3402 static int lucky_winner = -1; 3403 3404 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3405 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); 3406 3407 if (cpu_32bit) { 3408 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3409 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3410 } 3411 3412 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3413 return 0; 3414 3415 if (lucky_winner >= 0) 3416 return 0; 3417 3418 /* 3419 * We've detected a mismatch. We need to keep one of our CPUs with 3420 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3421 * every CPU in the system for a 32-bit task. 3422 */ 3423 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3424 cpu_active_mask); 3425 get_cpu_device(lucky_winner)->offline_disabled = true; 3426 setup_elf_hwcaps(compat_elf_hwcaps); 3427 elf_hwcap_fixup(); 3428 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3429 cpu, lucky_winner); 3430 return 0; 3431 } 3432 3433 static int __init init_32bit_el0_mask(void) 3434 { 3435 if (!allow_mismatched_32bit_el0) 3436 return 0; 3437 3438 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3439 return -ENOMEM; 3440 3441 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3442 "arm64/mismatched_32bit_el0:online", 3443 enable_mismatched_32bit_el0, NULL); 3444 } 3445 subsys_initcall_sync(init_32bit_el0_mask); 3446 3447 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3448 { 3449 cpu_enable_swapper_cnp(); 3450 } 3451 3452 /* 3453 * We emulate only the following system register space. 3454 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 3455 * See Table C5-6 System instruction encodings for System register accesses, 3456 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3457 */ 3458 static inline bool __attribute_const__ is_emulated(u32 id) 3459 { 3460 return (sys_reg_Op0(id) == 0x3 && 3461 sys_reg_CRn(id) == 0x0 && 3462 sys_reg_Op1(id) == 0x0 && 3463 (sys_reg_CRm(id) == 0 || 3464 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 3465 } 3466 3467 /* 3468 * With CRm == 0, reg should be one of : 3469 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3470 */ 3471 static inline int emulate_id_reg(u32 id, u64 *valp) 3472 { 3473 switch (id) { 3474 case SYS_MIDR_EL1: 3475 *valp = read_cpuid_id(); 3476 break; 3477 case SYS_MPIDR_EL1: 3478 *valp = SYS_MPIDR_SAFE_VAL; 3479 break; 3480 case SYS_REVIDR_EL1: 3481 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3482 *valp = 0; 3483 break; 3484 default: 3485 return -EINVAL; 3486 } 3487 3488 return 0; 3489 } 3490 3491 static int emulate_sys_reg(u32 id, u64 *valp) 3492 { 3493 struct arm64_ftr_reg *regp; 3494 3495 if (!is_emulated(id)) 3496 return -EINVAL; 3497 3498 if (sys_reg_CRm(id) == 0) 3499 return emulate_id_reg(id, valp); 3500 3501 regp = get_arm64_ftr_reg_nowarn(id); 3502 if (regp) 3503 *valp = arm64_ftr_reg_user_value(regp); 3504 else 3505 /* 3506 * The untracked registers are either IMPLEMENTATION DEFINED 3507 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3508 */ 3509 *valp = 0; 3510 return 0; 3511 } 3512 3513 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3514 { 3515 int rc; 3516 u64 val; 3517 3518 rc = emulate_sys_reg(sys_reg, &val); 3519 if (!rc) { 3520 pt_regs_write_reg(regs, rt, val); 3521 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3522 } 3523 return rc; 3524 } 3525 3526 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 3527 { 3528 u32 sys_reg, rt; 3529 3530 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 3531 return false; 3532 3533 /* 3534 * sys_reg values are defined as used in mrs/msr instruction. 3535 * shift the imm value to get the encoding. 3536 */ 3537 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 3538 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 3539 return do_emulate_mrs(regs, sys_reg, rt) == 0; 3540 } 3541 3542 enum mitigation_state arm64_get_meltdown_state(void) 3543 { 3544 if (__meltdown_safe) 3545 return SPECTRE_UNAFFECTED; 3546 3547 if (arm64_kernel_unmapped_at_el0()) 3548 return SPECTRE_MITIGATED; 3549 3550 return SPECTRE_VULNERABLE; 3551 } 3552 3553 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 3554 char *buf) 3555 { 3556 switch (arm64_get_meltdown_state()) { 3557 case SPECTRE_UNAFFECTED: 3558 return sprintf(buf, "Not affected\n"); 3559 3560 case SPECTRE_MITIGATED: 3561 return sprintf(buf, "Mitigation: PTI\n"); 3562 3563 default: 3564 return sprintf(buf, "Vulnerable\n"); 3565 } 3566 } 3567