1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Record and handle CPU attributes. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 */ 7 #include <asm/arch_timer.h> 8 #include <asm/cache.h> 9 #include <asm/cpu.h> 10 #include <asm/cputype.h> 11 #include <asm/cpufeature.h> 12 #include <asm/fpsimd.h> 13 14 #include <linux/bitops.h> 15 #include <linux/bug.h> 16 #include <linux/compat.h> 17 #include <linux/elf.h> 18 #include <linux/init.h> 19 #include <linux/kernel.h> 20 #include <linux/personality.h> 21 #include <linux/preempt.h> 22 #include <linux/printk.h> 23 #include <linux/seq_file.h> 24 #include <linux/sched.h> 25 #include <linux/smp.h> 26 #include <linux/delay.h> 27 28 /* 29 * In case the boot CPU is hotpluggable, we record its initial state and 30 * current state separately. Certain system registers may contain different 31 * values depending on configuration at or after reset. 32 */ 33 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); 34 static struct cpuinfo_arm64 boot_cpu_data; 35 36 static char *icache_policy_str[] = { 37 [0 ... ICACHE_POLICY_PIPT] = "RESERVED/UNKNOWN", 38 [ICACHE_POLICY_VIPT] = "VIPT", 39 [ICACHE_POLICY_PIPT] = "PIPT", 40 [ICACHE_POLICY_VPIPT] = "VPIPT", 41 }; 42 43 unsigned long __icache_flags; 44 45 static const char *const hwcap_str[] = { 46 "fp", 47 "asimd", 48 "evtstrm", 49 "aes", 50 "pmull", 51 "sha1", 52 "sha2", 53 "crc32", 54 "atomics", 55 "fphp", 56 "asimdhp", 57 "cpuid", 58 "asimdrdm", 59 "jscvt", 60 "fcma", 61 "lrcpc", 62 "dcpop", 63 "sha3", 64 "sm3", 65 "sm4", 66 "asimddp", 67 "sha512", 68 "sve", 69 "asimdfhm", 70 "dit", 71 "uscat", 72 "ilrcpc", 73 "flagm", 74 "ssbs", 75 "sb", 76 "paca", 77 "pacg", 78 "dcpodp", 79 "sve2", 80 "sveaes", 81 "svepmull", 82 "svebitperm", 83 "svesha3", 84 "svesm4", 85 NULL 86 }; 87 88 #ifdef CONFIG_COMPAT 89 static const char *const compat_hwcap_str[] = { 90 "swp", 91 "half", 92 "thumb", 93 "26bit", 94 "fastmult", 95 "fpa", 96 "vfp", 97 "edsp", 98 "java", 99 "iwmmxt", 100 "crunch", 101 "thumbee", 102 "neon", 103 "vfpv3", 104 "vfpv3d16", 105 "tls", 106 "vfpv4", 107 "idiva", 108 "idivt", 109 "vfpd32", 110 "lpae", 111 "evtstrm", 112 NULL 113 }; 114 115 static const char *const compat_hwcap2_str[] = { 116 "aes", 117 "pmull", 118 "sha1", 119 "sha2", 120 "crc32", 121 NULL 122 }; 123 #endif /* CONFIG_COMPAT */ 124 125 static int c_show(struct seq_file *m, void *v) 126 { 127 int i, j; 128 bool compat = personality(current->personality) == PER_LINUX32; 129 130 for_each_online_cpu(i) { 131 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i); 132 u32 midr = cpuinfo->reg_midr; 133 134 /* 135 * glibc reads /proc/cpuinfo to determine the number of 136 * online processors, looking for lines beginning with 137 * "processor". Give glibc what it expects. 138 */ 139 seq_printf(m, "processor\t: %d\n", i); 140 if (compat) 141 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n", 142 MIDR_REVISION(midr), COMPAT_ELF_PLATFORM); 143 144 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", 145 loops_per_jiffy / (500000UL/HZ), 146 loops_per_jiffy / (5000UL/HZ) % 100); 147 148 /* 149 * Dump out the common processor features in a single line. 150 * Userspace should read the hwcaps with getauxval(AT_HWCAP) 151 * rather than attempting to parse this, but there's a body of 152 * software which does already (at least for 32-bit). 153 */ 154 seq_puts(m, "Features\t:"); 155 if (compat) { 156 #ifdef CONFIG_COMPAT 157 for (j = 0; compat_hwcap_str[j]; j++) 158 if (compat_elf_hwcap & (1 << j)) 159 seq_printf(m, " %s", compat_hwcap_str[j]); 160 161 for (j = 0; compat_hwcap2_str[j]; j++) 162 if (compat_elf_hwcap2 & (1 << j)) 163 seq_printf(m, " %s", compat_hwcap2_str[j]); 164 #endif /* CONFIG_COMPAT */ 165 } else { 166 for (j = 0; hwcap_str[j]; j++) 167 if (cpu_have_feature(j)) 168 seq_printf(m, " %s", hwcap_str[j]); 169 } 170 seq_puts(m, "\n"); 171 172 seq_printf(m, "CPU implementer\t: 0x%02x\n", 173 MIDR_IMPLEMENTOR(midr)); 174 seq_printf(m, "CPU architecture: 8\n"); 175 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr)); 176 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr)); 177 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr)); 178 } 179 180 return 0; 181 } 182 183 static void *c_start(struct seq_file *m, loff_t *pos) 184 { 185 return *pos < 1 ? (void *)1 : NULL; 186 } 187 188 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 189 { 190 ++*pos; 191 return NULL; 192 } 193 194 static void c_stop(struct seq_file *m, void *v) 195 { 196 } 197 198 const struct seq_operations cpuinfo_op = { 199 .start = c_start, 200 .next = c_next, 201 .stop = c_stop, 202 .show = c_show 203 }; 204 205 206 static struct kobj_type cpuregs_kobj_type = { 207 .sysfs_ops = &kobj_sysfs_ops, 208 }; 209 210 /* 211 * The ARM ARM uses the phrase "32-bit register" to describe a register 212 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however 213 * no statement is made as to whether the upper 32 bits will or will not 214 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI 215 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit. 216 * 217 * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit 218 * registers, we expose them both as 64 bit values to cater for possible 219 * future expansion without an ABI break. 220 */ 221 #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj) 222 #define CPUREGS_ATTR_RO(_name, _field) \ 223 static ssize_t _name##_show(struct kobject *kobj, \ 224 struct kobj_attribute *attr, char *buf) \ 225 { \ 226 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \ 227 \ 228 if (info->reg_midr) \ 229 return sprintf(buf, "0x%016x\n", info->reg_##_field); \ 230 else \ 231 return 0; \ 232 } \ 233 static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name) 234 235 CPUREGS_ATTR_RO(midr_el1, midr); 236 CPUREGS_ATTR_RO(revidr_el1, revidr); 237 238 static struct attribute *cpuregs_id_attrs[] = { 239 &cpuregs_attr_midr_el1.attr, 240 &cpuregs_attr_revidr_el1.attr, 241 NULL 242 }; 243 244 static const struct attribute_group cpuregs_attr_group = { 245 .attrs = cpuregs_id_attrs, 246 .name = "identification" 247 }; 248 249 static int cpuid_cpu_online(unsigned int cpu) 250 { 251 int rc; 252 struct device *dev; 253 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 254 255 dev = get_cpu_device(cpu); 256 if (!dev) { 257 rc = -ENODEV; 258 goto out; 259 } 260 rc = kobject_add(&info->kobj, &dev->kobj, "regs"); 261 if (rc) 262 goto out; 263 rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group); 264 if (rc) 265 kobject_del(&info->kobj); 266 out: 267 return rc; 268 } 269 270 static int cpuid_cpu_offline(unsigned int cpu) 271 { 272 struct device *dev; 273 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 274 275 dev = get_cpu_device(cpu); 276 if (!dev) 277 return -ENODEV; 278 if (info->kobj.parent) { 279 sysfs_remove_group(&info->kobj, &cpuregs_attr_group); 280 kobject_del(&info->kobj); 281 } 282 283 return 0; 284 } 285 286 static int __init cpuinfo_regs_init(void) 287 { 288 int cpu, ret; 289 290 for_each_possible_cpu(cpu) { 291 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 292 293 kobject_init(&info->kobj, &cpuregs_kobj_type); 294 } 295 296 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online", 297 cpuid_cpu_online, cpuid_cpu_offline); 298 if (ret < 0) { 299 pr_err("cpuinfo: failed to register hotplug callbacks.\n"); 300 return ret; 301 } 302 return 0; 303 } 304 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) 305 { 306 unsigned int cpu = smp_processor_id(); 307 u32 l1ip = CTR_L1IP(info->reg_ctr); 308 309 switch (l1ip) { 310 case ICACHE_POLICY_PIPT: 311 break; 312 case ICACHE_POLICY_VPIPT: 313 set_bit(ICACHEF_VPIPT, &__icache_flags); 314 break; 315 default: 316 /* Fallthrough */ 317 case ICACHE_POLICY_VIPT: 318 /* Assume aliasing */ 319 set_bit(ICACHEF_ALIASING, &__icache_flags); 320 } 321 322 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu); 323 } 324 325 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 326 { 327 info->reg_cntfrq = arch_timer_get_cntfrq(); 328 /* 329 * Use the effective value of the CTR_EL0 than the raw value 330 * exposed by the CPU. CTR_E0.IDC field value must be interpreted 331 * with the CLIDR_EL1 fields to avoid triggering false warnings 332 * when there is a mismatch across the CPUs. Keep track of the 333 * effective value of the CTR_EL0 in our internal records for 334 * acurate sanity check and feature enablement. 335 */ 336 info->reg_ctr = read_cpuid_effective_cachetype(); 337 info->reg_dczid = read_cpuid(DCZID_EL0); 338 info->reg_midr = read_cpuid_id(); 339 info->reg_revidr = read_cpuid(REVIDR_EL1); 340 341 info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1); 342 info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); 343 info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1); 344 info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1); 345 info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 346 info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 347 info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1); 348 info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1); 349 info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1); 350 info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1); 351 352 /* Update the 32bit ID registers only if AArch32 is implemented */ 353 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 354 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1); 355 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1); 356 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1); 357 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1); 358 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1); 359 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1); 360 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1); 361 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1); 362 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1); 363 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1); 364 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1); 365 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1); 366 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1); 367 368 info->reg_mvfr0 = read_cpuid(MVFR0_EL1); 369 info->reg_mvfr1 = read_cpuid(MVFR1_EL1); 370 info->reg_mvfr2 = read_cpuid(MVFR2_EL1); 371 } 372 373 if (IS_ENABLED(CONFIG_ARM64_SVE) && 374 id_aa64pfr0_sve(info->reg_id_aa64pfr0)) 375 info->reg_zcr = read_zcr_features(); 376 377 cpuinfo_detect_icache_policy(info); 378 } 379 380 void cpuinfo_store_cpu(void) 381 { 382 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data); 383 __cpuinfo_store_cpu(info); 384 update_cpu_features(smp_processor_id(), info, &boot_cpu_data); 385 } 386 387 void __init cpuinfo_store_boot_cpu(void) 388 { 389 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0); 390 __cpuinfo_store_cpu(info); 391 392 boot_cpu_data = *info; 393 init_cpu_features(&boot_cpu_data); 394 } 395 396 device_initcall(cpuinfo_regs_init); 397