1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * VGICv3 MMIO handling functions 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/irqchip/arm-gic-v3.h> 8 #include <linux/kvm.h> 9 #include <linux/kvm_host.h> 10 #include <linux/interrupt.h> 11 #include <kvm/iodev.h> 12 #include <kvm/arm_vgic.h> 13 14 #include <asm/kvm_emulate.h> 15 #include <asm/kvm_arm.h> 16 #include <asm/kvm_mmu.h> 17 18 #include "vgic.h" 19 #include "vgic-mmio.h" 20 21 /* extract @num bytes at @offset bytes offset in data */ 22 unsigned long extract_bytes(u64 data, unsigned int offset, 23 unsigned int num) 24 { 25 return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0); 26 } 27 28 /* allows updates of any half of a 64-bit register (or the whole thing) */ 29 u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len, 30 unsigned long val) 31 { 32 int lower = (offset & 4) * 8; 33 int upper = lower + 8 * len - 1; 34 35 reg &= ~GENMASK_ULL(upper, lower); 36 val &= GENMASK_ULL(len * 8 - 1, 0); 37 38 return reg | ((u64)val << lower); 39 } 40 41 bool vgic_has_its(struct kvm *kvm) 42 { 43 struct vgic_dist *dist = &kvm->arch.vgic; 44 45 if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3) 46 return false; 47 48 return dist->has_its; 49 } 50 51 bool vgic_supports_direct_msis(struct kvm *kvm) 52 { 53 return (kvm_vgic_global_state.has_gicv4_1 || 54 (kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm))); 55 } 56 57 /* 58 * The Revision field in the IIDR have the following meanings: 59 * 60 * Revision 2: Interrupt groups are guest-configurable and signaled using 61 * their configured groups. 62 */ 63 64 static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu, 65 gpa_t addr, unsigned int len) 66 { 67 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic; 68 u32 value = 0; 69 70 switch (addr & 0x0c) { 71 case GICD_CTLR: 72 if (vgic->enabled) 73 value |= GICD_CTLR_ENABLE_SS_G1; 74 value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS; 75 if (vgic->nassgireq) 76 value |= GICD_CTLR_nASSGIreq; 77 break; 78 case GICD_TYPER: 79 value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS; 80 value = (value >> 5) - 1; 81 if (vgic_has_its(vcpu->kvm)) { 82 value |= (INTERRUPT_ID_BITS_ITS - 1) << 19; 83 value |= GICD_TYPER_LPIS; 84 } else { 85 value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19; 86 } 87 break; 88 case GICD_TYPER2: 89 if (kvm_vgic_global_state.has_gicv4_1 && gic_cpuif_has_vsgi()) 90 value = GICD_TYPER2_nASSGIcap; 91 break; 92 case GICD_IIDR: 93 value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) | 94 (vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) | 95 (IMPLEMENTER_ARM << GICD_IIDR_IMPLEMENTER_SHIFT); 96 break; 97 default: 98 return 0; 99 } 100 101 return value; 102 } 103 104 static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu, 105 gpa_t addr, unsigned int len, 106 unsigned long val) 107 { 108 struct vgic_dist *dist = &vcpu->kvm->arch.vgic; 109 110 switch (addr & 0x0c) { 111 case GICD_CTLR: { 112 bool was_enabled, is_hwsgi; 113 114 mutex_lock(&vcpu->kvm->arch.config_lock); 115 116 was_enabled = dist->enabled; 117 is_hwsgi = dist->nassgireq; 118 119 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1; 120 121 /* Not a GICv4.1? No HW SGIs */ 122 if (!kvm_vgic_global_state.has_gicv4_1 || !gic_cpuif_has_vsgi()) 123 val &= ~GICD_CTLR_nASSGIreq; 124 125 /* Dist stays enabled? nASSGIreq is RO */ 126 if (was_enabled && dist->enabled) { 127 val &= ~GICD_CTLR_nASSGIreq; 128 val |= FIELD_PREP(GICD_CTLR_nASSGIreq, is_hwsgi); 129 } 130 131 /* Switching HW SGIs? */ 132 dist->nassgireq = val & GICD_CTLR_nASSGIreq; 133 if (is_hwsgi != dist->nassgireq) 134 vgic_v4_configure_vsgis(vcpu->kvm); 135 136 if (kvm_vgic_global_state.has_gicv4_1 && 137 was_enabled != dist->enabled) 138 kvm_make_all_cpus_request(vcpu->kvm, KVM_REQ_RELOAD_GICv4); 139 else if (!was_enabled && dist->enabled) 140 vgic_kick_vcpus(vcpu->kvm); 141 142 mutex_unlock(&vcpu->kvm->arch.config_lock); 143 break; 144 } 145 case GICD_TYPER: 146 case GICD_TYPER2: 147 case GICD_IIDR: 148 /* This is at best for documentation purposes... */ 149 return; 150 } 151 } 152 153 static int vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu *vcpu, 154 gpa_t addr, unsigned int len, 155 unsigned long val) 156 { 157 struct vgic_dist *dist = &vcpu->kvm->arch.vgic; 158 u32 reg; 159 160 switch (addr & 0x0c) { 161 case GICD_TYPER2: 162 if (val != vgic_mmio_read_v3_misc(vcpu, addr, len)) 163 return -EINVAL; 164 return 0; 165 case GICD_IIDR: 166 reg = vgic_mmio_read_v3_misc(vcpu, addr, len); 167 if ((reg ^ val) & ~GICD_IIDR_REVISION_MASK) 168 return -EINVAL; 169 170 reg = FIELD_GET(GICD_IIDR_REVISION_MASK, reg); 171 switch (reg) { 172 case KVM_VGIC_IMP_REV_2: 173 case KVM_VGIC_IMP_REV_3: 174 dist->implementation_rev = reg; 175 return 0; 176 default: 177 return -EINVAL; 178 } 179 case GICD_CTLR: 180 /* Not a GICv4.1? No HW SGIs */ 181 if (!kvm_vgic_global_state.has_gicv4_1) 182 val &= ~GICD_CTLR_nASSGIreq; 183 184 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1; 185 dist->nassgireq = val & GICD_CTLR_nASSGIreq; 186 return 0; 187 } 188 189 vgic_mmio_write_v3_misc(vcpu, addr, len, val); 190 return 0; 191 } 192 193 static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu, 194 gpa_t addr, unsigned int len) 195 { 196 int intid = VGIC_ADDR_TO_INTID(addr, 64); 197 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid); 198 unsigned long ret = 0; 199 200 if (!irq) 201 return 0; 202 203 /* The upper word is RAZ for us. */ 204 if (!(addr & 4)) 205 ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len); 206 207 vgic_put_irq(vcpu->kvm, irq); 208 return ret; 209 } 210 211 static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu, 212 gpa_t addr, unsigned int len, 213 unsigned long val) 214 { 215 int intid = VGIC_ADDR_TO_INTID(addr, 64); 216 struct vgic_irq *irq; 217 unsigned long flags; 218 219 /* The upper word is WI for us since we don't implement Aff3. */ 220 if (addr & 4) 221 return; 222 223 irq = vgic_get_irq(vcpu->kvm, NULL, intid); 224 225 if (!irq) 226 return; 227 228 raw_spin_lock_irqsave(&irq->irq_lock, flags); 229 230 /* We only care about and preserve Aff0, Aff1 and Aff2. */ 231 irq->mpidr = val & GENMASK(23, 0); 232 irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr); 233 234 raw_spin_unlock_irqrestore(&irq->irq_lock, flags); 235 vgic_put_irq(vcpu->kvm, irq); 236 } 237 238 bool vgic_lpis_enabled(struct kvm_vcpu *vcpu) 239 { 240 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 241 242 return atomic_read(&vgic_cpu->ctlr) == GICR_CTLR_ENABLE_LPIS; 243 } 244 245 static unsigned long vgic_mmio_read_v3r_ctlr(struct kvm_vcpu *vcpu, 246 gpa_t addr, unsigned int len) 247 { 248 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 249 unsigned long val; 250 251 val = atomic_read(&vgic_cpu->ctlr); 252 if (vgic_get_implementation_rev(vcpu) >= KVM_VGIC_IMP_REV_3) 253 val |= GICR_CTLR_IR | GICR_CTLR_CES; 254 255 return val; 256 } 257 258 static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu, 259 gpa_t addr, unsigned int len, 260 unsigned long val) 261 { 262 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 263 u32 ctlr; 264 265 if (!vgic_has_its(vcpu->kvm)) 266 return; 267 268 if (!(val & GICR_CTLR_ENABLE_LPIS)) { 269 /* 270 * Don't disable if RWP is set, as there already an 271 * ongoing disable. Funky guest... 272 */ 273 ctlr = atomic_cmpxchg_acquire(&vgic_cpu->ctlr, 274 GICR_CTLR_ENABLE_LPIS, 275 GICR_CTLR_RWP); 276 if (ctlr != GICR_CTLR_ENABLE_LPIS) 277 return; 278 279 vgic_flush_pending_lpis(vcpu); 280 vgic_its_invalidate_cache(vcpu->kvm); 281 atomic_set_release(&vgic_cpu->ctlr, 0); 282 } else { 283 ctlr = atomic_cmpxchg_acquire(&vgic_cpu->ctlr, 0, 284 GICR_CTLR_ENABLE_LPIS); 285 if (ctlr != 0) 286 return; 287 288 vgic_enable_lpis(vcpu); 289 } 290 } 291 292 static bool vgic_mmio_vcpu_rdist_is_last(struct kvm_vcpu *vcpu) 293 { 294 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic; 295 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 296 struct vgic_redist_region *iter, *rdreg = vgic_cpu->rdreg; 297 298 if (!rdreg) 299 return false; 300 301 if (vgic_cpu->rdreg_index < rdreg->free_index - 1) { 302 return false; 303 } else if (rdreg->count && vgic_cpu->rdreg_index == (rdreg->count - 1)) { 304 struct list_head *rd_regions = &vgic->rd_regions; 305 gpa_t end = rdreg->base + rdreg->count * KVM_VGIC_V3_REDIST_SIZE; 306 307 /* 308 * the rdist is the last one of the redist region, 309 * check whether there is no other contiguous rdist region 310 */ 311 list_for_each_entry(iter, rd_regions, list) { 312 if (iter->base == end && iter->free_index > 0) 313 return false; 314 } 315 } 316 return true; 317 } 318 319 static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu, 320 gpa_t addr, unsigned int len) 321 { 322 unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu); 323 int target_vcpu_id = vcpu->vcpu_id; 324 u64 value; 325 326 value = (u64)(mpidr & GENMASK(23, 0)) << 32; 327 value |= ((target_vcpu_id & 0xffff) << 8); 328 329 if (vgic_has_its(vcpu->kvm)) 330 value |= GICR_TYPER_PLPIS; 331 332 if (vgic_mmio_vcpu_rdist_is_last(vcpu)) 333 value |= GICR_TYPER_LAST; 334 335 return extract_bytes(value, addr & 7, len); 336 } 337 338 static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu, 339 gpa_t addr, unsigned int len) 340 { 341 return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0); 342 } 343 344 static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu, 345 gpa_t addr, unsigned int len) 346 { 347 switch (addr & 0xffff) { 348 case GICD_PIDR2: 349 /* report a GICv3 compliant implementation */ 350 return 0x3b; 351 } 352 353 return 0; 354 } 355 356 static int vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu, 357 gpa_t addr, unsigned int len, 358 unsigned long val) 359 { 360 int ret; 361 362 ret = vgic_uaccess_write_spending(vcpu, addr, len, val); 363 if (ret) 364 return ret; 365 366 return vgic_uaccess_write_cpending(vcpu, addr, len, ~val); 367 } 368 369 /* We want to avoid outer shareable. */ 370 u64 vgic_sanitise_shareability(u64 field) 371 { 372 switch (field) { 373 case GIC_BASER_OuterShareable: 374 return GIC_BASER_InnerShareable; 375 default: 376 return field; 377 } 378 } 379 380 /* Avoid any inner non-cacheable mapping. */ 381 u64 vgic_sanitise_inner_cacheability(u64 field) 382 { 383 switch (field) { 384 case GIC_BASER_CACHE_nCnB: 385 case GIC_BASER_CACHE_nC: 386 return GIC_BASER_CACHE_RaWb; 387 default: 388 return field; 389 } 390 } 391 392 /* Non-cacheable or same-as-inner are OK. */ 393 u64 vgic_sanitise_outer_cacheability(u64 field) 394 { 395 switch (field) { 396 case GIC_BASER_CACHE_SameAsInner: 397 case GIC_BASER_CACHE_nC: 398 return field; 399 default: 400 return GIC_BASER_CACHE_SameAsInner; 401 } 402 } 403 404 u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift, 405 u64 (*sanitise_fn)(u64)) 406 { 407 u64 field = (reg & field_mask) >> field_shift; 408 409 field = sanitise_fn(field) << field_shift; 410 return (reg & ~field_mask) | field; 411 } 412 413 #define PROPBASER_RES0_MASK \ 414 (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5)) 415 #define PENDBASER_RES0_MASK \ 416 (BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \ 417 GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0)) 418 419 static u64 vgic_sanitise_pendbaser(u64 reg) 420 { 421 reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK, 422 GICR_PENDBASER_SHAREABILITY_SHIFT, 423 vgic_sanitise_shareability); 424 reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK, 425 GICR_PENDBASER_INNER_CACHEABILITY_SHIFT, 426 vgic_sanitise_inner_cacheability); 427 reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK, 428 GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT, 429 vgic_sanitise_outer_cacheability); 430 431 reg &= ~PENDBASER_RES0_MASK; 432 433 return reg; 434 } 435 436 static u64 vgic_sanitise_propbaser(u64 reg) 437 { 438 reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK, 439 GICR_PROPBASER_SHAREABILITY_SHIFT, 440 vgic_sanitise_shareability); 441 reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK, 442 GICR_PROPBASER_INNER_CACHEABILITY_SHIFT, 443 vgic_sanitise_inner_cacheability); 444 reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK, 445 GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT, 446 vgic_sanitise_outer_cacheability); 447 448 reg &= ~PROPBASER_RES0_MASK; 449 return reg; 450 } 451 452 static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu, 453 gpa_t addr, unsigned int len) 454 { 455 struct vgic_dist *dist = &vcpu->kvm->arch.vgic; 456 457 return extract_bytes(dist->propbaser, addr & 7, len); 458 } 459 460 static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu, 461 gpa_t addr, unsigned int len, 462 unsigned long val) 463 { 464 struct vgic_dist *dist = &vcpu->kvm->arch.vgic; 465 u64 old_propbaser, propbaser; 466 467 /* Storing a value with LPIs already enabled is undefined */ 468 if (vgic_lpis_enabled(vcpu)) 469 return; 470 471 do { 472 old_propbaser = READ_ONCE(dist->propbaser); 473 propbaser = old_propbaser; 474 propbaser = update_64bit_reg(propbaser, addr & 4, len, val); 475 propbaser = vgic_sanitise_propbaser(propbaser); 476 } while (cmpxchg64(&dist->propbaser, old_propbaser, 477 propbaser) != old_propbaser); 478 } 479 480 static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu, 481 gpa_t addr, unsigned int len) 482 { 483 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 484 u64 value = vgic_cpu->pendbaser; 485 486 value &= ~GICR_PENDBASER_PTZ; 487 488 return extract_bytes(value, addr & 7, len); 489 } 490 491 static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu, 492 gpa_t addr, unsigned int len, 493 unsigned long val) 494 { 495 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 496 u64 old_pendbaser, pendbaser; 497 498 /* Storing a value with LPIs already enabled is undefined */ 499 if (vgic_lpis_enabled(vcpu)) 500 return; 501 502 do { 503 old_pendbaser = READ_ONCE(vgic_cpu->pendbaser); 504 pendbaser = old_pendbaser; 505 pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val); 506 pendbaser = vgic_sanitise_pendbaser(pendbaser); 507 } while (cmpxchg64(&vgic_cpu->pendbaser, old_pendbaser, 508 pendbaser) != old_pendbaser); 509 } 510 511 static unsigned long vgic_mmio_read_sync(struct kvm_vcpu *vcpu, 512 gpa_t addr, unsigned int len) 513 { 514 return !!atomic_read(&vcpu->arch.vgic_cpu.syncr_busy); 515 } 516 517 static void vgic_set_rdist_busy(struct kvm_vcpu *vcpu, bool busy) 518 { 519 if (busy) { 520 atomic_inc(&vcpu->arch.vgic_cpu.syncr_busy); 521 smp_mb__after_atomic(); 522 } else { 523 smp_mb__before_atomic(); 524 atomic_dec(&vcpu->arch.vgic_cpu.syncr_busy); 525 } 526 } 527 528 static void vgic_mmio_write_invlpi(struct kvm_vcpu *vcpu, 529 gpa_t addr, unsigned int len, 530 unsigned long val) 531 { 532 struct vgic_irq *irq; 533 534 /* 535 * If the guest wrote only to the upper 32bit part of the 536 * register, drop the write on the floor, as it is only for 537 * vPEs (which we don't support for obvious reasons). 538 * 539 * Also discard the access if LPIs are not enabled. 540 */ 541 if ((addr & 4) || !vgic_lpis_enabled(vcpu)) 542 return; 543 544 vgic_set_rdist_busy(vcpu, true); 545 546 irq = vgic_get_irq(vcpu->kvm, NULL, lower_32_bits(val)); 547 if (irq) { 548 vgic_its_inv_lpi(vcpu->kvm, irq); 549 vgic_put_irq(vcpu->kvm, irq); 550 } 551 552 vgic_set_rdist_busy(vcpu, false); 553 } 554 555 static void vgic_mmio_write_invall(struct kvm_vcpu *vcpu, 556 gpa_t addr, unsigned int len, 557 unsigned long val) 558 { 559 /* See vgic_mmio_write_invlpi() for the early return rationale */ 560 if ((addr & 4) || !vgic_lpis_enabled(vcpu)) 561 return; 562 563 vgic_set_rdist_busy(vcpu, true); 564 vgic_its_invall(vcpu); 565 vgic_set_rdist_busy(vcpu, false); 566 } 567 568 /* 569 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the 570 * redistributors, while SPIs are covered by registers in the distributor 571 * block. Trying to set private IRQs in this block gets ignored. 572 * We take some special care here to fix the calculation of the register 573 * offset. 574 */ 575 #define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, ur, uw, bpi, acc) \ 576 { \ 577 .reg_offset = off, \ 578 .bits_per_irq = bpi, \ 579 .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \ 580 .access_flags = acc, \ 581 .read = vgic_mmio_read_raz, \ 582 .write = vgic_mmio_write_wi, \ 583 }, { \ 584 .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \ 585 .bits_per_irq = bpi, \ 586 .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8, \ 587 .access_flags = acc, \ 588 .read = rd, \ 589 .write = wr, \ 590 .uaccess_read = ur, \ 591 .uaccess_write = uw, \ 592 } 593 594 static const struct vgic_register_region vgic_v3_dist_registers[] = { 595 REGISTER_DESC_WITH_LENGTH_UACCESS(GICD_CTLR, 596 vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 597 NULL, vgic_mmio_uaccess_write_v3_misc, 598 16, VGIC_ACCESS_32bit), 599 REGISTER_DESC_WITH_LENGTH(GICD_STATUSR, 600 vgic_mmio_read_rao, vgic_mmio_write_wi, 4, 601 VGIC_ACCESS_32bit), 602 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR, 603 vgic_mmio_read_group, vgic_mmio_write_group, NULL, NULL, 1, 604 VGIC_ACCESS_32bit), 605 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER, 606 vgic_mmio_read_enable, vgic_mmio_write_senable, 607 NULL, vgic_uaccess_write_senable, 1, 608 VGIC_ACCESS_32bit), 609 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER, 610 vgic_mmio_read_enable, vgic_mmio_write_cenable, 611 NULL, vgic_uaccess_write_cenable, 1, 612 VGIC_ACCESS_32bit), 613 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR, 614 vgic_mmio_read_pending, vgic_mmio_write_spending, 615 vgic_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1, 616 VGIC_ACCESS_32bit), 617 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR, 618 vgic_mmio_read_pending, vgic_mmio_write_cpending, 619 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 1, 620 VGIC_ACCESS_32bit), 621 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER, 622 vgic_mmio_read_active, vgic_mmio_write_sactive, 623 vgic_uaccess_read_active, vgic_mmio_uaccess_write_sactive, 1, 624 VGIC_ACCESS_32bit), 625 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER, 626 vgic_mmio_read_active, vgic_mmio_write_cactive, 627 vgic_uaccess_read_active, vgic_mmio_uaccess_write_cactive, 628 1, VGIC_ACCESS_32bit), 629 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR, 630 vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL, 631 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), 632 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR, 633 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8, 634 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), 635 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR, 636 vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2, 637 VGIC_ACCESS_32bit), 638 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR, 639 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, 640 VGIC_ACCESS_32bit), 641 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER, 642 vgic_mmio_read_irouter, vgic_mmio_write_irouter, NULL, NULL, 64, 643 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 644 REGISTER_DESC_WITH_LENGTH(GICD_IDREGS, 645 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48, 646 VGIC_ACCESS_32bit), 647 }; 648 649 static const struct vgic_register_region vgic_v3_rd_registers[] = { 650 /* RD_base registers */ 651 REGISTER_DESC_WITH_LENGTH(GICR_CTLR, 652 vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4, 653 VGIC_ACCESS_32bit), 654 REGISTER_DESC_WITH_LENGTH(GICR_STATUSR, 655 vgic_mmio_read_raz, vgic_mmio_write_wi, 4, 656 VGIC_ACCESS_32bit), 657 REGISTER_DESC_WITH_LENGTH(GICR_IIDR, 658 vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4, 659 VGIC_ACCESS_32bit), 660 REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_TYPER, 661 vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 662 NULL, vgic_mmio_uaccess_write_wi, 8, 663 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 664 REGISTER_DESC_WITH_LENGTH(GICR_WAKER, 665 vgic_mmio_read_raz, vgic_mmio_write_wi, 4, 666 VGIC_ACCESS_32bit), 667 REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER, 668 vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8, 669 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 670 REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER, 671 vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8, 672 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 673 REGISTER_DESC_WITH_LENGTH(GICR_INVLPIR, 674 vgic_mmio_read_raz, vgic_mmio_write_invlpi, 8, 675 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 676 REGISTER_DESC_WITH_LENGTH(GICR_INVALLR, 677 vgic_mmio_read_raz, vgic_mmio_write_invall, 8, 678 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 679 REGISTER_DESC_WITH_LENGTH(GICR_SYNCR, 680 vgic_mmio_read_sync, vgic_mmio_write_wi, 4, 681 VGIC_ACCESS_32bit), 682 REGISTER_DESC_WITH_LENGTH(GICR_IDREGS, 683 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48, 684 VGIC_ACCESS_32bit), 685 /* SGI_base registers */ 686 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGROUPR0, 687 vgic_mmio_read_group, vgic_mmio_write_group, 4, 688 VGIC_ACCESS_32bit), 689 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISENABLER0, 690 vgic_mmio_read_enable, vgic_mmio_write_senable, 691 NULL, vgic_uaccess_write_senable, 4, 692 VGIC_ACCESS_32bit), 693 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICENABLER0, 694 vgic_mmio_read_enable, vgic_mmio_write_cenable, 695 NULL, vgic_uaccess_write_cenable, 4, 696 VGIC_ACCESS_32bit), 697 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISPENDR0, 698 vgic_mmio_read_pending, vgic_mmio_write_spending, 699 vgic_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4, 700 VGIC_ACCESS_32bit), 701 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICPENDR0, 702 vgic_mmio_read_pending, vgic_mmio_write_cpending, 703 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 4, 704 VGIC_ACCESS_32bit), 705 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISACTIVER0, 706 vgic_mmio_read_active, vgic_mmio_write_sactive, 707 vgic_uaccess_read_active, vgic_mmio_uaccess_write_sactive, 4, 708 VGIC_ACCESS_32bit), 709 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICACTIVER0, 710 vgic_mmio_read_active, vgic_mmio_write_cactive, 711 vgic_uaccess_read_active, vgic_mmio_uaccess_write_cactive, 4, 712 VGIC_ACCESS_32bit), 713 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IPRIORITYR0, 714 vgic_mmio_read_priority, vgic_mmio_write_priority, 32, 715 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), 716 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ICFGR0, 717 vgic_mmio_read_config, vgic_mmio_write_config, 8, 718 VGIC_ACCESS_32bit), 719 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGRPMODR0, 720 vgic_mmio_read_raz, vgic_mmio_write_wi, 4, 721 VGIC_ACCESS_32bit), 722 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_NSACR, 723 vgic_mmio_read_raz, vgic_mmio_write_wi, 4, 724 VGIC_ACCESS_32bit), 725 }; 726 727 unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev) 728 { 729 dev->regions = vgic_v3_dist_registers; 730 dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers); 731 732 kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops); 733 734 return SZ_64K; 735 } 736 737 /** 738 * vgic_register_redist_iodev - register a single redist iodev 739 * @vcpu: The VCPU to which the redistributor belongs 740 * 741 * Register a KVM iodev for this VCPU's redistributor using the address 742 * provided. 743 * 744 * Return 0 on success, -ERRNO otherwise. 745 */ 746 int vgic_register_redist_iodev(struct kvm_vcpu *vcpu) 747 { 748 struct kvm *kvm = vcpu->kvm; 749 struct vgic_dist *vgic = &kvm->arch.vgic; 750 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 751 struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev; 752 struct vgic_redist_region *rdreg; 753 gpa_t rd_base; 754 int ret = 0; 755 756 lockdep_assert_held(&kvm->slots_lock); 757 mutex_lock(&kvm->arch.config_lock); 758 759 if (!IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr)) 760 goto out_unlock; 761 762 /* 763 * We may be creating VCPUs before having set the base address for the 764 * redistributor region, in which case we will come back to this 765 * function for all VCPUs when the base address is set. Just return 766 * without doing any work for now. 767 */ 768 rdreg = vgic_v3_rdist_free_slot(&vgic->rd_regions); 769 if (!rdreg) 770 goto out_unlock; 771 772 if (!vgic_v3_check_base(kvm)) { 773 ret = -EINVAL; 774 goto out_unlock; 775 } 776 777 vgic_cpu->rdreg = rdreg; 778 vgic_cpu->rdreg_index = rdreg->free_index; 779 780 rd_base = rdreg->base + rdreg->free_index * KVM_VGIC_V3_REDIST_SIZE; 781 782 kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops); 783 rd_dev->base_addr = rd_base; 784 rd_dev->iodev_type = IODEV_REDIST; 785 rd_dev->regions = vgic_v3_rd_registers; 786 rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rd_registers); 787 rd_dev->redist_vcpu = vcpu; 788 789 mutex_unlock(&kvm->arch.config_lock); 790 791 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base, 792 2 * SZ_64K, &rd_dev->dev); 793 if (ret) 794 return ret; 795 796 /* Protected by slots_lock */ 797 rdreg->free_index++; 798 return 0; 799 800 out_unlock: 801 mutex_unlock(&kvm->arch.config_lock); 802 return ret; 803 } 804 805 void vgic_unregister_redist_iodev(struct kvm_vcpu *vcpu) 806 { 807 struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev; 808 809 kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &rd_dev->dev); 810 } 811 812 static int vgic_register_all_redist_iodevs(struct kvm *kvm) 813 { 814 struct kvm_vcpu *vcpu; 815 unsigned long c; 816 int ret = 0; 817 818 lockdep_assert_held(&kvm->slots_lock); 819 820 kvm_for_each_vcpu(c, vcpu, kvm) { 821 ret = vgic_register_redist_iodev(vcpu); 822 if (ret) 823 break; 824 } 825 826 if (ret) { 827 /* The current c failed, so iterate over the previous ones. */ 828 int i; 829 830 for (i = 0; i < c; i++) { 831 vcpu = kvm_get_vcpu(kvm, i); 832 vgic_unregister_redist_iodev(vcpu); 833 } 834 } 835 836 return ret; 837 } 838 839 /** 840 * vgic_v3_alloc_redist_region - Allocate a new redistributor region 841 * 842 * Performs various checks before inserting the rdist region in the list. 843 * Those tests depend on whether the size of the rdist region is known 844 * (ie. count != 0). The list is sorted by rdist region index. 845 * 846 * @kvm: kvm handle 847 * @index: redist region index 848 * @base: base of the new rdist region 849 * @count: number of redistributors the region is made of (0 in the old style 850 * single region, whose size is induced from the number of vcpus) 851 * 852 * Return 0 on success, < 0 otherwise 853 */ 854 static int vgic_v3_alloc_redist_region(struct kvm *kvm, uint32_t index, 855 gpa_t base, uint32_t count) 856 { 857 struct vgic_dist *d = &kvm->arch.vgic; 858 struct vgic_redist_region *rdreg; 859 struct list_head *rd_regions = &d->rd_regions; 860 int nr_vcpus = atomic_read(&kvm->online_vcpus); 861 size_t size = count ? count * KVM_VGIC_V3_REDIST_SIZE 862 : nr_vcpus * KVM_VGIC_V3_REDIST_SIZE; 863 int ret; 864 865 /* cross the end of memory ? */ 866 if (base + size < base) 867 return -EINVAL; 868 869 if (list_empty(rd_regions)) { 870 if (index != 0) 871 return -EINVAL; 872 } else { 873 rdreg = list_last_entry(rd_regions, 874 struct vgic_redist_region, list); 875 876 /* Don't mix single region and discrete redist regions */ 877 if (!count && rdreg->count) 878 return -EINVAL; 879 880 if (!count) 881 return -EEXIST; 882 883 if (index != rdreg->index + 1) 884 return -EINVAL; 885 } 886 887 /* 888 * For legacy single-region redistributor regions (!count), 889 * check that the redistributor region does not overlap with the 890 * distributor's address space. 891 */ 892 if (!count && !IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) && 893 vgic_dist_overlap(kvm, base, size)) 894 return -EINVAL; 895 896 /* collision with any other rdist region? */ 897 if (vgic_v3_rdist_overlap(kvm, base, size)) 898 return -EINVAL; 899 900 rdreg = kzalloc(sizeof(*rdreg), GFP_KERNEL_ACCOUNT); 901 if (!rdreg) 902 return -ENOMEM; 903 904 rdreg->base = VGIC_ADDR_UNDEF; 905 906 ret = vgic_check_iorange(kvm, rdreg->base, base, SZ_64K, size); 907 if (ret) 908 goto free; 909 910 rdreg->base = base; 911 rdreg->count = count; 912 rdreg->free_index = 0; 913 rdreg->index = index; 914 915 list_add_tail(&rdreg->list, rd_regions); 916 return 0; 917 free: 918 kfree(rdreg); 919 return ret; 920 } 921 922 void vgic_v3_free_redist_region(struct vgic_redist_region *rdreg) 923 { 924 list_del(&rdreg->list); 925 kfree(rdreg); 926 } 927 928 int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count) 929 { 930 int ret; 931 932 mutex_lock(&kvm->arch.config_lock); 933 ret = vgic_v3_alloc_redist_region(kvm, index, addr, count); 934 mutex_unlock(&kvm->arch.config_lock); 935 if (ret) 936 return ret; 937 938 /* 939 * Register iodevs for each existing VCPU. Adding more VCPUs 940 * afterwards will register the iodevs when needed. 941 */ 942 ret = vgic_register_all_redist_iodevs(kvm); 943 if (ret) { 944 struct vgic_redist_region *rdreg; 945 946 mutex_lock(&kvm->arch.config_lock); 947 rdreg = vgic_v3_rdist_region_from_index(kvm, index); 948 vgic_v3_free_redist_region(rdreg); 949 mutex_unlock(&kvm->arch.config_lock); 950 return ret; 951 } 952 953 return 0; 954 } 955 956 int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr) 957 { 958 const struct vgic_register_region *region; 959 struct vgic_io_device iodev; 960 struct vgic_reg_attr reg_attr; 961 struct kvm_vcpu *vcpu; 962 gpa_t addr; 963 int ret; 964 965 ret = vgic_v3_parse_attr(dev, attr, ®_attr); 966 if (ret) 967 return ret; 968 969 vcpu = reg_attr.vcpu; 970 addr = reg_attr.addr; 971 972 switch (attr->group) { 973 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: 974 iodev.regions = vgic_v3_dist_registers; 975 iodev.nr_regions = ARRAY_SIZE(vgic_v3_dist_registers); 976 iodev.base_addr = 0; 977 break; 978 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:{ 979 iodev.regions = vgic_v3_rd_registers; 980 iodev.nr_regions = ARRAY_SIZE(vgic_v3_rd_registers); 981 iodev.base_addr = 0; 982 break; 983 } 984 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: 985 return vgic_v3_has_cpu_sysregs_attr(vcpu, attr); 986 default: 987 return -ENXIO; 988 } 989 990 /* We only support aligned 32-bit accesses. */ 991 if (addr & 3) 992 return -ENXIO; 993 994 region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32)); 995 if (!region) 996 return -ENXIO; 997 998 return 0; 999 } 1000 1001 /* 1002 * The ICC_SGI* registers encode the affinity differently from the MPIDR, 1003 * so provide a wrapper to use the existing defines to isolate a certain 1004 * affinity level. 1005 */ 1006 #define SGI_AFFINITY_LEVEL(reg, level) \ 1007 ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \ 1008 >> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level)) 1009 1010 static void vgic_v3_queue_sgi(struct kvm_vcpu *vcpu, u32 sgi, bool allow_group1) 1011 { 1012 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, sgi); 1013 unsigned long flags; 1014 1015 raw_spin_lock_irqsave(&irq->irq_lock, flags); 1016 1017 /* 1018 * An access targeting Group0 SGIs can only generate 1019 * those, while an access targeting Group1 SGIs can 1020 * generate interrupts of either group. 1021 */ 1022 if (!irq->group || allow_group1) { 1023 if (!irq->hw) { 1024 irq->pending_latch = true; 1025 vgic_queue_irq_unlock(vcpu->kvm, irq, flags); 1026 } else { 1027 /* HW SGI? Ask the GIC to inject it */ 1028 int err; 1029 err = irq_set_irqchip_state(irq->host_irq, 1030 IRQCHIP_STATE_PENDING, 1031 true); 1032 WARN_RATELIMIT(err, "IRQ %d", irq->host_irq); 1033 raw_spin_unlock_irqrestore(&irq->irq_lock, flags); 1034 } 1035 } else { 1036 raw_spin_unlock_irqrestore(&irq->irq_lock, flags); 1037 } 1038 1039 vgic_put_irq(vcpu->kvm, irq); 1040 } 1041 1042 /** 1043 * vgic_v3_dispatch_sgi - handle SGI requests from VCPUs 1044 * @vcpu: The VCPU requesting a SGI 1045 * @reg: The value written into ICC_{ASGI1,SGI0,SGI1}R by that VCPU 1046 * @allow_group1: Does the sysreg access allow generation of G1 SGIs 1047 * 1048 * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register. 1049 * This will trap in sys_regs.c and call this function. 1050 * This ICC_SGI1R_EL1 register contains the upper three affinity levels of the 1051 * target processors as well as a bitmask of 16 Aff0 CPUs. 1052 * 1053 * If the interrupt routing mode bit is not set, we iterate over the Aff0 1054 * bits and signal the VCPUs matching the provided Aff{3,2,1}. 1055 * 1056 * If this bit is set, we signal all, but not the calling VCPU. 1057 */ 1058 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1) 1059 { 1060 struct kvm *kvm = vcpu->kvm; 1061 struct kvm_vcpu *c_vcpu; 1062 unsigned long target_cpus; 1063 u64 mpidr; 1064 u32 sgi, aff0; 1065 unsigned long c; 1066 1067 sgi = FIELD_GET(ICC_SGI1R_SGI_ID_MASK, reg); 1068 1069 /* Broadcast */ 1070 if (unlikely(reg & BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT))) { 1071 kvm_for_each_vcpu(c, c_vcpu, kvm) { 1072 /* Don't signal the calling VCPU */ 1073 if (c_vcpu == vcpu) 1074 continue; 1075 1076 vgic_v3_queue_sgi(c_vcpu, sgi, allow_group1); 1077 } 1078 1079 return; 1080 } 1081 1082 /* We iterate over affinities to find the corresponding vcpus */ 1083 mpidr = SGI_AFFINITY_LEVEL(reg, 3); 1084 mpidr |= SGI_AFFINITY_LEVEL(reg, 2); 1085 mpidr |= SGI_AFFINITY_LEVEL(reg, 1); 1086 target_cpus = FIELD_GET(ICC_SGI1R_TARGET_LIST_MASK, reg); 1087 1088 for_each_set_bit(aff0, &target_cpus, hweight_long(ICC_SGI1R_TARGET_LIST_MASK)) { 1089 c_vcpu = kvm_mpidr_to_vcpu(kvm, mpidr | aff0); 1090 if (c_vcpu) 1091 vgic_v3_queue_sgi(c_vcpu, sgi, allow_group1); 1092 } 1093 } 1094 1095 int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write, 1096 int offset, u32 *val) 1097 { 1098 struct vgic_io_device dev = { 1099 .regions = vgic_v3_dist_registers, 1100 .nr_regions = ARRAY_SIZE(vgic_v3_dist_registers), 1101 }; 1102 1103 return vgic_uaccess(vcpu, &dev, is_write, offset, val); 1104 } 1105 1106 int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write, 1107 int offset, u32 *val) 1108 { 1109 struct vgic_io_device rd_dev = { 1110 .regions = vgic_v3_rd_registers, 1111 .nr_regions = ARRAY_SIZE(vgic_v3_rd_registers), 1112 }; 1113 1114 return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val); 1115 } 1116 1117 int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write, 1118 u32 intid, u32 *val) 1119 { 1120 if (intid % 32) 1121 return -EINVAL; 1122 1123 if (is_write) 1124 vgic_write_irq_line_level_info(vcpu, intid, *val); 1125 else 1126 *val = vgic_read_irq_line_level_info(vcpu, intid); 1127 1128 return 0; 1129 } 1130