1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 25291fa98SPhilippe De Muyter /* 35291fa98SPhilippe De Muyter * Bit definitions for the MCF54xx ACR and CACR registers. 45291fa98SPhilippe De Muyter */ 55291fa98SPhilippe De Muyter 65291fa98SPhilippe De Muyter #ifndef m54xxacr_h 75291fa98SPhilippe De Muyter #define m54xxacr_h 85291fa98SPhilippe De Muyter 95291fa98SPhilippe De Muyter /* 105291fa98SPhilippe De Muyter * Define the Cache register flags. 115291fa98SPhilippe De Muyter */ 125291fa98SPhilippe De Muyter #define CACR_DEC 0x80000000 /* Enable data cache */ 135291fa98SPhilippe De Muyter #define CACR_DWP 0x40000000 /* Data write protection */ 145291fa98SPhilippe De Muyter #define CACR_DESB 0x20000000 /* Enable data store buffer */ 155291fa98SPhilippe De Muyter #define CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */ 165291fa98SPhilippe De Muyter #define CACR_DHCLK 0x08000000 /* Half data cache lock mode */ 175291fa98SPhilippe De Muyter #define CACR_DDCM_WT 0x00000000 /* Write through cache*/ 185291fa98SPhilippe De Muyter #define CACR_DDCM_CP 0x02000000 /* Copyback cache */ 195291fa98SPhilippe De Muyter #define CACR_DDCM_P 0x04000000 /* No cache, precise */ 205291fa98SPhilippe De Muyter #define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */ 215291fa98SPhilippe De Muyter #define CACR_DCINVA 0x01000000 /* Invalidate data cache */ 225291fa98SPhilippe De Muyter #define CACR_BEC 0x00080000 /* Enable branch cache */ 235291fa98SPhilippe De Muyter #define CACR_BCINVA 0x00040000 /* Invalidate branch cache */ 245291fa98SPhilippe De Muyter #define CACR_IEC 0x00008000 /* Enable instruction cache */ 255291fa98SPhilippe De Muyter #define CACR_DNFB 0x00002000 /* Inhibited fill buffer */ 265291fa98SPhilippe De Muyter #define CACR_IDPI 0x00001000 /* Disable CPUSHL */ 27efbec135SAdam Buchbinder #define CACR_IHLCK 0x00000800 /* Instruction cache half lock */ 28efbec135SAdam Buchbinder #define CACR_IDCM 0x00000400 /* Instruction cache inhibit */ 295291fa98SPhilippe De Muyter #define CACR_ICINVA 0x00000100 /* Invalidate instr cache */ 301c83af5fSGreg Ungerer #define CACR_EUSP 0x00000020 /* Enable separate user a7 */ 315291fa98SPhilippe De Muyter 325291fa98SPhilippe De Muyter #define ACR_BASE_POS 24 /* Address Base */ 335291fa98SPhilippe De Muyter #define ACR_MASK_POS 16 /* Address Mask */ 345291fa98SPhilippe De Muyter #define ACR_ENABLE 0x00008000 /* Enable address */ 355291fa98SPhilippe De Muyter #define ACR_USER 0x00000000 /* User mode access only */ 365291fa98SPhilippe De Muyter #define ACR_SUPER 0x00002000 /* Supervisor mode only */ 375291fa98SPhilippe De Muyter #define ACR_ANY 0x00004000 /* Match any access mode */ 385291fa98SPhilippe De Muyter #define ACR_CM_WT 0x00000000 /* Write through mode */ 395291fa98SPhilippe De Muyter #define ACR_CM_CP 0x00000020 /* Copyback mode */ 405291fa98SPhilippe De Muyter #define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */ 415291fa98SPhilippe De Muyter #define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */ 425291fa98SPhilippe De Muyter #define ACR_CM 0x00000060 /* Cache mode mask */ 430b0b808bSGreg Ungerer #define ACR_SP 0x00000008 /* Supervisor protect */ 445291fa98SPhilippe De Muyter #define ACR_WPROTECT 0x00000004 /* Write protect */ 455291fa98SPhilippe De Muyter 460b0b808bSGreg Ungerer #define ACR_BA(x) ((x) & 0xff000000) 470b0b808bSGreg Ungerer #define ACR_ADMSK(x) ((((x) - 1) & 0xff000000) >> 8) 480b0b808bSGreg Ungerer 499c68015bSPhilippe De Muyter #if defined(CONFIG_M5407) 509c68015bSPhilippe De Muyter 519c68015bSPhilippe De Muyter #define ICACHE_SIZE 0x4000 /* instruction - 16k */ 529c68015bSPhilippe De Muyter #define DCACHE_SIZE 0x2000 /* data - 8k */ 539c68015bSPhilippe De Muyter 545b2e6555SGreg Ungerer #elif defined(CONFIG_M54xx) 559c68015bSPhilippe De Muyter 569c68015bSPhilippe De Muyter #define ICACHE_SIZE 0x8000 /* instruction - 32k */ 579c68015bSPhilippe De Muyter #define DCACHE_SIZE 0x8000 /* data - 32k */ 589c68015bSPhilippe De Muyter 59bea8bcb1SSteven King #elif defined(CONFIG_M5441x) 60bea8bcb1SSteven King 61bea8bcb1SSteven King #define ICACHE_SIZE 0x2000 /* instruction - 8k */ 62bea8bcb1SSteven King #define DCACHE_SIZE 0x2000 /* data - 8k */ 639c68015bSPhilippe De Muyter #endif 649c68015bSPhilippe De Muyter 659c68015bSPhilippe De Muyter #define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ 669c68015bSPhilippe De Muyter #define CACHE_WAYS 4 /* 4 ways */ 679c68015bSPhilippe De Muyter 680b0b808bSGreg Ungerer #define ICACHE_SET_MASK ((ICACHE_SIZE / 64 - 1) << CACHE_WAYS) 690b0b808bSGreg Ungerer #define DCACHE_SET_MASK ((DCACHE_SIZE / 64 - 1) << CACHE_WAYS) 700b0b808bSGreg Ungerer #define ICACHE_MAX_ADDR ICACHE_SET_MASK 710b0b808bSGreg Ungerer #define DCACHE_MAX_ADDR DCACHE_SET_MASK 720b0b808bSGreg Ungerer 739c68015bSPhilippe De Muyter /* 749c68015bSPhilippe De Muyter * Version 4 cores have a true harvard style separate instruction 759c68015bSPhilippe De Muyter * and data cache. Enable data and instruction caches, also enable write 769c68015bSPhilippe De Muyter * buffers and branch accelerator. 779c68015bSPhilippe De Muyter */ 789c68015bSPhilippe De Muyter /* attention : enabling CACR_DESB requires a "nop" to flush the store buffer */ 799c68015bSPhilippe De Muyter /* use '+' instead of '|' for assembler's sake */ 809c68015bSPhilippe De Muyter 819c68015bSPhilippe De Muyter /* Enable data cache */ 829c68015bSPhilippe De Muyter /* Enable data store buffer */ 839c68015bSPhilippe De Muyter /* outside ACRs : No cache, precise */ 849c68015bSPhilippe De Muyter /* Enable instruction+branch caches */ 851c83af5fSGreg Ungerer #if defined(CONFIG_M5407) 869c68015bSPhilippe De Muyter #define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC) 871c83af5fSGreg Ungerer #else 881c83af5fSGreg Ungerer #define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP) 891c83af5fSGreg Ungerer #endif 900b0b808bSGreg Ungerer #define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) 910b0b808bSGreg Ungerer 920b0b808bSGreg Ungerer #if defined(CONFIG_MMU) 930b0b808bSGreg Ungerer /* 940b0b808bSGreg Ungerer * If running with the MMU enabled then we need to map the internal 950b0b808bSGreg Ungerer * register region as non-cacheable. And then we map all our RAM as 960b0b808bSGreg Ungerer * cacheable and supervisor access only. 970b0b808bSGreg Ungerer */ 988cf4a973SGreg Ungerer #define ACR0_MODE (ACR_BA(IOMEMBASE)+ACR_ADMSK(IOMEMSIZE)+ \ 990b0b808bSGreg Ungerer ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP) 100a4eff487SStany MARCEL #if defined(CONFIG_CACHE_COPYBACK) 1010b0b808bSGreg Ungerer #define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ 102a4eff487SStany MARCEL ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_CP) 103a4eff487SStany MARCEL #else 104a4eff487SStany MARCEL #define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ 105a4eff487SStany MARCEL ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_WT) 106a4eff487SStany MARCEL #endif 1070b0b808bSGreg Ungerer #define ACR2_MODE 0 1080b0b808bSGreg Ungerer #define ACR3_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ 1090b0b808bSGreg Ungerer ACR_ENABLE+ACR_SUPER+ACR_SP) 1100b0b808bSGreg Ungerer 1110b0b808bSGreg Ungerer #else 1120b0b808bSGreg Ungerer 1130b0b808bSGreg Ungerer /* 1140b0b808bSGreg Ungerer * For the non-MMU enabled case we map all of RAM as cacheable. 1150b0b808bSGreg Ungerer */ 1164a5bae41SGreg Ungerer #if defined(CONFIG_CACHE_COPYBACK) 1174a5bae41SGreg Ungerer #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_CP) 1184a5bae41SGreg Ungerer #else 1199c68015bSPhilippe De Muyter #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT) 1204a5bae41SGreg Ungerer #endif 1219c68015bSPhilippe De Muyter #define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY) 1229c68015bSPhilippe De Muyter 1238ce877a8SGreg Ungerer #define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) 12407ffee59SGreg Ungerer #define CACHE_INVALIDATEI (CACHE_MODE+CACR_BCINVA+CACR_ICINVA) 12507ffee59SGreg Ungerer #define CACHE_INVALIDATED (CACHE_MODE+CACR_DCINVA) 1268ce877a8SGreg Ungerer #define ACR0_MODE (0x000f0000+DATA_CACHE_MODE) 1278ce877a8SGreg Ungerer #define ACR1_MODE 0 1288ce877a8SGreg Ungerer #define ACR2_MODE (0x000f0000+INSN_CACHE_MODE) 1298ce877a8SGreg Ungerer #define ACR3_MODE 0 1308ce877a8SGreg Ungerer 1319c68015bSPhilippe De Muyter #if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP) 132d475e3e4SGreg Ungerer /* Copyback cache mode must push dirty cache lines first */ 133d475e3e4SGreg Ungerer #define CACHE_PUSH 1349c68015bSPhilippe De Muyter #endif 135b3d75b09SPhilippe De Muyter 1360b0b808bSGreg Ungerer #endif /* CONFIG_MMU */ 1375291fa98SPhilippe De Muyter #endif /* m54xxacr_h */ 138