15291fa98SPhilippe De Muyter /* 25291fa98SPhilippe De Muyter * Bit definitions for the MCF54xx ACR and CACR registers. 35291fa98SPhilippe De Muyter */ 45291fa98SPhilippe De Muyter 55291fa98SPhilippe De Muyter #ifndef m54xxacr_h 65291fa98SPhilippe De Muyter #define m54xxacr_h 75291fa98SPhilippe De Muyter 85291fa98SPhilippe De Muyter /* 95291fa98SPhilippe De Muyter * Define the Cache register flags. 105291fa98SPhilippe De Muyter */ 115291fa98SPhilippe De Muyter #define CACR_DEC 0x80000000 /* Enable data cache */ 125291fa98SPhilippe De Muyter #define CACR_DWP 0x40000000 /* Data write protection */ 135291fa98SPhilippe De Muyter #define CACR_DESB 0x20000000 /* Enable data store buffer */ 145291fa98SPhilippe De Muyter #define CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */ 155291fa98SPhilippe De Muyter #define CACR_DHCLK 0x08000000 /* Half data cache lock mode */ 165291fa98SPhilippe De Muyter #define CACR_DDCM_WT 0x00000000 /* Write through cache*/ 175291fa98SPhilippe De Muyter #define CACR_DDCM_CP 0x02000000 /* Copyback cache */ 185291fa98SPhilippe De Muyter #define CACR_DDCM_P 0x04000000 /* No cache, precise */ 195291fa98SPhilippe De Muyter #define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */ 205291fa98SPhilippe De Muyter #define CACR_DCINVA 0x01000000 /* Invalidate data cache */ 215291fa98SPhilippe De Muyter #define CACR_BEC 0x00080000 /* Enable branch cache */ 225291fa98SPhilippe De Muyter #define CACR_BCINVA 0x00040000 /* Invalidate branch cache */ 235291fa98SPhilippe De Muyter #define CACR_IEC 0x00008000 /* Enable instruction cache */ 245291fa98SPhilippe De Muyter #define CACR_DNFB 0x00002000 /* Inhibited fill buffer */ 255291fa98SPhilippe De Muyter #define CACR_IDPI 0x00001000 /* Disable CPUSHL */ 265291fa98SPhilippe De Muyter #define CACR_IHLCK 0x00000800 /* Intruction cache half lock */ 275291fa98SPhilippe De Muyter #define CACR_IDCM 0x00000400 /* Intruction cache inhibit */ 285291fa98SPhilippe De Muyter #define CACR_ICINVA 0x00000100 /* Invalidate instr cache */ 295291fa98SPhilippe De Muyter 305291fa98SPhilippe De Muyter #define ACR_BASE_POS 24 /* Address Base */ 315291fa98SPhilippe De Muyter #define ACR_MASK_POS 16 /* Address Mask */ 325291fa98SPhilippe De Muyter #define ACR_ENABLE 0x00008000 /* Enable address */ 335291fa98SPhilippe De Muyter #define ACR_USER 0x00000000 /* User mode access only */ 345291fa98SPhilippe De Muyter #define ACR_SUPER 0x00002000 /* Supervisor mode only */ 355291fa98SPhilippe De Muyter #define ACR_ANY 0x00004000 /* Match any access mode */ 365291fa98SPhilippe De Muyter #define ACR_CM_WT 0x00000000 /* Write through mode */ 375291fa98SPhilippe De Muyter #define ACR_CM_CP 0x00000020 /* Copyback mode */ 385291fa98SPhilippe De Muyter #define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */ 395291fa98SPhilippe De Muyter #define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */ 405291fa98SPhilippe De Muyter #define ACR_CM 0x00000060 /* Cache mode mask */ 415291fa98SPhilippe De Muyter #define ACR_WPROTECT 0x00000004 /* Write protect */ 425291fa98SPhilippe De Muyter 439c68015bSPhilippe De Muyter #if defined(CONFIG_M5407) 449c68015bSPhilippe De Muyter 459c68015bSPhilippe De Muyter #define ICACHE_SIZE 0x4000 /* instruction - 16k */ 469c68015bSPhilippe De Muyter #define DCACHE_SIZE 0x2000 /* data - 8k */ 479c68015bSPhilippe De Muyter 48*5b2e6555SGreg Ungerer #elif defined(CONFIG_M54xx) 499c68015bSPhilippe De Muyter 509c68015bSPhilippe De Muyter #define ICACHE_SIZE 0x8000 /* instruction - 32k */ 519c68015bSPhilippe De Muyter #define DCACHE_SIZE 0x8000 /* data - 32k */ 529c68015bSPhilippe De Muyter 539c68015bSPhilippe De Muyter #endif 549c68015bSPhilippe De Muyter 559c68015bSPhilippe De Muyter #define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ 569c68015bSPhilippe De Muyter #define CACHE_WAYS 4 /* 4 ways */ 579c68015bSPhilippe De Muyter 589c68015bSPhilippe De Muyter /* 599c68015bSPhilippe De Muyter * Version 4 cores have a true harvard style separate instruction 609c68015bSPhilippe De Muyter * and data cache. Enable data and instruction caches, also enable write 619c68015bSPhilippe De Muyter * buffers and branch accelerator. 629c68015bSPhilippe De Muyter */ 639c68015bSPhilippe De Muyter /* attention : enabling CACR_DESB requires a "nop" to flush the store buffer */ 649c68015bSPhilippe De Muyter /* use '+' instead of '|' for assembler's sake */ 659c68015bSPhilippe De Muyter 669c68015bSPhilippe De Muyter /* Enable data cache */ 679c68015bSPhilippe De Muyter /* Enable data store buffer */ 689c68015bSPhilippe De Muyter /* outside ACRs : No cache, precise */ 699c68015bSPhilippe De Muyter /* Enable instruction+branch caches */ 709c68015bSPhilippe De Muyter #define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC) 719c68015bSPhilippe De Muyter 729c68015bSPhilippe De Muyter #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT) 739c68015bSPhilippe De Muyter 749c68015bSPhilippe De Muyter #define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY) 759c68015bSPhilippe De Muyter 76b3d75b09SPhilippe De Muyter #ifndef __ASSEMBLY__ 77b3d75b09SPhilippe De Muyter 789c68015bSPhilippe De Muyter #if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_WT) 799c68015bSPhilippe De Muyter #define flush_dcache_range(a, l) do { asm("nop"); } while (0) 809c68015bSPhilippe De Muyter #endif 819c68015bSPhilippe De Muyter 82b3d75b09SPhilippe De Muyter static inline void __m54xx_flush_cache_all(void) 83b3d75b09SPhilippe De Muyter { 849c68015bSPhilippe De Muyter __asm__ __volatile__ ( 859c68015bSPhilippe De Muyter #if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP) 86b3d75b09SPhilippe De Muyter /* 87b3d75b09SPhilippe De Muyter * Use cpushl to push and invalidate all cache lines. 88b3d75b09SPhilippe De Muyter * Gas doesn't seem to know how to generate the ColdFire 89b3d75b09SPhilippe De Muyter * cpushl instruction... Oh well, bit stuff it for now. 90b3d75b09SPhilippe De Muyter */ 91b3d75b09SPhilippe De Muyter "clrl %%d0\n\t" 92b3d75b09SPhilippe De Muyter "1:\n\t" 93b3d75b09SPhilippe De Muyter "movel %%d0,%%a0\n\t" 94b3d75b09SPhilippe De Muyter "2:\n\t" 95b3d75b09SPhilippe De Muyter ".word 0xf468\n\t" 969c68015bSPhilippe De Muyter "addl %0,%%a0\n\t" 979c68015bSPhilippe De Muyter "cmpl %1,%%a0\n\t" 98b3d75b09SPhilippe De Muyter "blt 2b\n\t" 99b3d75b09SPhilippe De Muyter "addql #1,%%d0\n\t" 1009c68015bSPhilippe De Muyter "cmpil %2,%%d0\n\t" 101b3d75b09SPhilippe De Muyter "bne 1b\n\t" 1029c68015bSPhilippe De Muyter #endif 1039c68015bSPhilippe De Muyter "movel %3,%%d0\n\t" 104b3d75b09SPhilippe De Muyter "movec %%d0,%%CACR\n\t" 1059c68015bSPhilippe De Muyter "nop\n\t" /* forces flush of Store Buffer */ 1069c68015bSPhilippe De Muyter : /* No output */ 1079c68015bSPhilippe De Muyter : "i" (CACHE_LINE_SIZE), 1089c68015bSPhilippe De Muyter "i" (DCACHE_SIZE / CACHE_WAYS), 1099c68015bSPhilippe De Muyter "i" (CACHE_WAYS), 1109c68015bSPhilippe De Muyter "i" (CACHE_MODE|CACR_DCINVA|CACR_BCINVA|CACR_ICINVA) 1119c68015bSPhilippe De Muyter : "d0", "a0" ); 112b3d75b09SPhilippe De Muyter } 113b3d75b09SPhilippe De Muyter 114b3d75b09SPhilippe De Muyter #define __flush_cache_all() __m54xx_flush_cache_all() 115b3d75b09SPhilippe De Muyter 116b3d75b09SPhilippe De Muyter #endif /* __ASSEMBLY__ */ 117b3d75b09SPhilippe De Muyter 1185291fa98SPhilippe De Muyter #endif /* m54xxacr_h */ 119