15291fa98SPhilippe De Muyter /* 25291fa98SPhilippe De Muyter * Bit definitions for the MCF54xx ACR and CACR registers. 35291fa98SPhilippe De Muyter */ 45291fa98SPhilippe De Muyter 55291fa98SPhilippe De Muyter #ifndef m54xxacr_h 65291fa98SPhilippe De Muyter #define m54xxacr_h 75291fa98SPhilippe De Muyter 85291fa98SPhilippe De Muyter /* 95291fa98SPhilippe De Muyter * Define the Cache register flags. 105291fa98SPhilippe De Muyter */ 115291fa98SPhilippe De Muyter #define CACR_DEC 0x80000000 /* Enable data cache */ 125291fa98SPhilippe De Muyter #define CACR_DWP 0x40000000 /* Data write protection */ 135291fa98SPhilippe De Muyter #define CACR_DESB 0x20000000 /* Enable data store buffer */ 145291fa98SPhilippe De Muyter #define CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */ 155291fa98SPhilippe De Muyter #define CACR_DHCLK 0x08000000 /* Half data cache lock mode */ 165291fa98SPhilippe De Muyter #define CACR_DDCM_WT 0x00000000 /* Write through cache*/ 175291fa98SPhilippe De Muyter #define CACR_DDCM_CP 0x02000000 /* Copyback cache */ 185291fa98SPhilippe De Muyter #define CACR_DDCM_P 0x04000000 /* No cache, precise */ 195291fa98SPhilippe De Muyter #define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */ 205291fa98SPhilippe De Muyter #define CACR_DCINVA 0x01000000 /* Invalidate data cache */ 215291fa98SPhilippe De Muyter #define CACR_BEC 0x00080000 /* Enable branch cache */ 225291fa98SPhilippe De Muyter #define CACR_BCINVA 0x00040000 /* Invalidate branch cache */ 235291fa98SPhilippe De Muyter #define CACR_IEC 0x00008000 /* Enable instruction cache */ 245291fa98SPhilippe De Muyter #define CACR_DNFB 0x00002000 /* Inhibited fill buffer */ 255291fa98SPhilippe De Muyter #define CACR_IDPI 0x00001000 /* Disable CPUSHL */ 265291fa98SPhilippe De Muyter #define CACR_IHLCK 0x00000800 /* Intruction cache half lock */ 275291fa98SPhilippe De Muyter #define CACR_IDCM 0x00000400 /* Intruction cache inhibit */ 285291fa98SPhilippe De Muyter #define CACR_ICINVA 0x00000100 /* Invalidate instr cache */ 291c83af5fSGreg Ungerer #define CACR_EUSP 0x00000020 /* Enable separate user a7 */ 305291fa98SPhilippe De Muyter 315291fa98SPhilippe De Muyter #define ACR_BASE_POS 24 /* Address Base */ 325291fa98SPhilippe De Muyter #define ACR_MASK_POS 16 /* Address Mask */ 335291fa98SPhilippe De Muyter #define ACR_ENABLE 0x00008000 /* Enable address */ 345291fa98SPhilippe De Muyter #define ACR_USER 0x00000000 /* User mode access only */ 355291fa98SPhilippe De Muyter #define ACR_SUPER 0x00002000 /* Supervisor mode only */ 365291fa98SPhilippe De Muyter #define ACR_ANY 0x00004000 /* Match any access mode */ 375291fa98SPhilippe De Muyter #define ACR_CM_WT 0x00000000 /* Write through mode */ 385291fa98SPhilippe De Muyter #define ACR_CM_CP 0x00000020 /* Copyback mode */ 395291fa98SPhilippe De Muyter #define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */ 405291fa98SPhilippe De Muyter #define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */ 415291fa98SPhilippe De Muyter #define ACR_CM 0x00000060 /* Cache mode mask */ 420b0b808bSGreg Ungerer #define ACR_SP 0x00000008 /* Supervisor protect */ 435291fa98SPhilippe De Muyter #define ACR_WPROTECT 0x00000004 /* Write protect */ 445291fa98SPhilippe De Muyter 450b0b808bSGreg Ungerer #define ACR_BA(x) ((x) & 0xff000000) 460b0b808bSGreg Ungerer #define ACR_ADMSK(x) ((((x) - 1) & 0xff000000) >> 8) 470b0b808bSGreg Ungerer 489c68015bSPhilippe De Muyter #if defined(CONFIG_M5407) 499c68015bSPhilippe De Muyter 509c68015bSPhilippe De Muyter #define ICACHE_SIZE 0x4000 /* instruction - 16k */ 519c68015bSPhilippe De Muyter #define DCACHE_SIZE 0x2000 /* data - 8k */ 529c68015bSPhilippe De Muyter 535b2e6555SGreg Ungerer #elif defined(CONFIG_M54xx) 549c68015bSPhilippe De Muyter 559c68015bSPhilippe De Muyter #define ICACHE_SIZE 0x8000 /* instruction - 32k */ 569c68015bSPhilippe De Muyter #define DCACHE_SIZE 0x8000 /* data - 32k */ 579c68015bSPhilippe De Muyter 58bea8bcb1SSteven King #elif defined(CONFIG_M5441x) 59bea8bcb1SSteven King 60bea8bcb1SSteven King #define ICACHE_SIZE 0x2000 /* instruction - 8k */ 61bea8bcb1SSteven King #define DCACHE_SIZE 0x2000 /* data - 8k */ 629c68015bSPhilippe De Muyter #endif 639c68015bSPhilippe De Muyter 649c68015bSPhilippe De Muyter #define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ 659c68015bSPhilippe De Muyter #define CACHE_WAYS 4 /* 4 ways */ 669c68015bSPhilippe De Muyter 670b0b808bSGreg Ungerer #define ICACHE_SET_MASK ((ICACHE_SIZE / 64 - 1) << CACHE_WAYS) 680b0b808bSGreg Ungerer #define DCACHE_SET_MASK ((DCACHE_SIZE / 64 - 1) << CACHE_WAYS) 690b0b808bSGreg Ungerer #define ICACHE_MAX_ADDR ICACHE_SET_MASK 700b0b808bSGreg Ungerer #define DCACHE_MAX_ADDR DCACHE_SET_MASK 710b0b808bSGreg Ungerer 729c68015bSPhilippe De Muyter /* 739c68015bSPhilippe De Muyter * Version 4 cores have a true harvard style separate instruction 749c68015bSPhilippe De Muyter * and data cache. Enable data and instruction caches, also enable write 759c68015bSPhilippe De Muyter * buffers and branch accelerator. 769c68015bSPhilippe De Muyter */ 779c68015bSPhilippe De Muyter /* attention : enabling CACR_DESB requires a "nop" to flush the store buffer */ 789c68015bSPhilippe De Muyter /* use '+' instead of '|' for assembler's sake */ 799c68015bSPhilippe De Muyter 809c68015bSPhilippe De Muyter /* Enable data cache */ 819c68015bSPhilippe De Muyter /* Enable data store buffer */ 829c68015bSPhilippe De Muyter /* outside ACRs : No cache, precise */ 839c68015bSPhilippe De Muyter /* Enable instruction+branch caches */ 841c83af5fSGreg Ungerer #if defined(CONFIG_M5407) 859c68015bSPhilippe De Muyter #define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC) 861c83af5fSGreg Ungerer #else 871c83af5fSGreg Ungerer #define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP) 881c83af5fSGreg Ungerer #endif 890b0b808bSGreg Ungerer #define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) 900b0b808bSGreg Ungerer 910b0b808bSGreg Ungerer #if defined(CONFIG_MMU) 920b0b808bSGreg Ungerer /* 930b0b808bSGreg Ungerer * If running with the MMU enabled then we need to map the internal 940b0b808bSGreg Ungerer * register region as non-cacheable. And then we map all our RAM as 950b0b808bSGreg Ungerer * cacheable and supervisor access only. 960b0b808bSGreg Ungerer */ 970b0b808bSGreg Ungerer #define ACR0_MODE (ACR_BA(CONFIG_MBAR)+ACR_ADMSK(0x1000000)+ \ 980b0b808bSGreg Ungerer ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP) 99*a4eff487SStany MARCEL #if defined(CONFIG_CACHE_COPYBACK) 1000b0b808bSGreg Ungerer #define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ 101*a4eff487SStany MARCEL ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_CP) 102*a4eff487SStany MARCEL #else 103*a4eff487SStany MARCEL #define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ 104*a4eff487SStany MARCEL ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_WT) 105*a4eff487SStany MARCEL #endif 1060b0b808bSGreg Ungerer #define ACR2_MODE 0 1070b0b808bSGreg Ungerer #define ACR3_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ 1080b0b808bSGreg Ungerer ACR_ENABLE+ACR_SUPER+ACR_SP) 1090b0b808bSGreg Ungerer 1100b0b808bSGreg Ungerer #else 1110b0b808bSGreg Ungerer 1120b0b808bSGreg Ungerer /* 1130b0b808bSGreg Ungerer * For the non-MMU enabled case we map all of RAM as cacheable. 1140b0b808bSGreg Ungerer */ 1154a5bae41SGreg Ungerer #if defined(CONFIG_CACHE_COPYBACK) 1164a5bae41SGreg Ungerer #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_CP) 1174a5bae41SGreg Ungerer #else 1189c68015bSPhilippe De Muyter #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT) 1194a5bae41SGreg Ungerer #endif 1209c68015bSPhilippe De Muyter #define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY) 1219c68015bSPhilippe De Muyter 1228ce877a8SGreg Ungerer #define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) 12307ffee59SGreg Ungerer #define CACHE_INVALIDATEI (CACHE_MODE+CACR_BCINVA+CACR_ICINVA) 12407ffee59SGreg Ungerer #define CACHE_INVALIDATED (CACHE_MODE+CACR_DCINVA) 1258ce877a8SGreg Ungerer #define ACR0_MODE (0x000f0000+DATA_CACHE_MODE) 1268ce877a8SGreg Ungerer #define ACR1_MODE 0 1278ce877a8SGreg Ungerer #define ACR2_MODE (0x000f0000+INSN_CACHE_MODE) 1288ce877a8SGreg Ungerer #define ACR3_MODE 0 1298ce877a8SGreg Ungerer 1309c68015bSPhilippe De Muyter #if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP) 131d475e3e4SGreg Ungerer /* Copyback cache mode must push dirty cache lines first */ 132d475e3e4SGreg Ungerer #define CACHE_PUSH 1339c68015bSPhilippe De Muyter #endif 134b3d75b09SPhilippe De Muyter 1350b0b808bSGreg Ungerer #endif /* CONFIG_MMU */ 1365291fa98SPhilippe De Muyter #endif /* m54xxacr_h */ 137