149148020SSam Ravnborg /* SPDX-License-Identifier: GPL-2.0 */ 249148020SSam Ravnborg /* 349148020SSam Ravnborg * I/O Processor (IOP) defines and structures, mostly snagged from A/UX 449148020SSam Ravnborg * header files. 549148020SSam Ravnborg * 649148020SSam Ravnborg * The original header from which this was taken is copyrighted. I've done some 749148020SSam Ravnborg * rewriting (in fact my changes make this a bit more readable, IMHO) but some 849148020SSam Ravnborg * more should be done. 949148020SSam Ravnborg */ 1049148020SSam Ravnborg 1149148020SSam Ravnborg /* 1249148020SSam Ravnborg * This is the base address of the IOPs. Use this as the address of 1349148020SSam Ravnborg * a "struct iop" (see below) to see where the actual registers fall. 1449148020SSam Ravnborg */ 1549148020SSam Ravnborg 1649148020SSam Ravnborg #define SCC_IOP_BASE_IIFX (0x50F04000) 1749148020SSam Ravnborg #define ISM_IOP_BASE_IIFX (0x50F12000) 1849148020SSam Ravnborg 1949148020SSam Ravnborg #define SCC_IOP_BASE_QUADRA (0x50F0C000) 2049148020SSam Ravnborg #define ISM_IOP_BASE_QUADRA (0x50F1E000) 2149148020SSam Ravnborg 2249148020SSam Ravnborg /* IOP status/control register bits: */ 2349148020SSam Ravnborg 2449148020SSam Ravnborg #define IOP_BYPASS 0x01 /* bypass-mode hardware access */ 2549148020SSam Ravnborg #define IOP_AUTOINC 0x02 /* allow autoincrement of ramhi/lo */ 2649148020SSam Ravnborg #define IOP_RUN 0x04 /* set to 0 to reset IOP chip */ 2749148020SSam Ravnborg #define IOP_IRQ 0x08 /* generate IRQ to IOP if 1 */ 2849148020SSam Ravnborg #define IOP_INT0 0x10 /* intr priority from IOP to host */ 2949148020SSam Ravnborg #define IOP_INT1 0x20 /* intr priority from IOP to host */ 3049148020SSam Ravnborg #define IOP_HWINT 0x40 /* IRQ from hardware; bypass mode only */ 3149148020SSam Ravnborg #define IOP_DMAINACTIVE 0x80 /* no DMA request active; bypass mode only */ 3249148020SSam Ravnborg 3349148020SSam Ravnborg #define NUM_IOPS 2 3449148020SSam Ravnborg #define NUM_IOP_CHAN 7 3549148020SSam Ravnborg #define NUM_IOP_MSGS NUM_IOP_CHAN*8 3649148020SSam Ravnborg #define IOP_MSG_LEN 32 3749148020SSam Ravnborg 3849148020SSam Ravnborg /* IOP reference numbers, used by the globally-visible iop_xxx functions */ 3949148020SSam Ravnborg 4049148020SSam Ravnborg #define IOP_NUM_SCC 0 4149148020SSam Ravnborg #define IOP_NUM_ISM 1 4249148020SSam Ravnborg 4349148020SSam Ravnborg /* IOP channel states */ 4449148020SSam Ravnborg 4549148020SSam Ravnborg #define IOP_MSG_IDLE 0 /* idle */ 4649148020SSam Ravnborg #define IOP_MSG_NEW 1 /* new message sent */ 4749148020SSam Ravnborg #define IOP_MSG_RCVD 2 /* message received; processing */ 4849148020SSam Ravnborg #define IOP_MSG_COMPLETE 3 /* message processing complete */ 4949148020SSam Ravnborg 5049148020SSam Ravnborg /* IOP message status codes */ 51efbec135SAdam Buchbinder 5249148020SSam Ravnborg #define IOP_MSGSTATUS_UNUSED 0 /* Unused message structure */ 5349148020SSam Ravnborg #define IOP_MSGSTATUS_WAITING 1 /* waiting for channel */ 5449148020SSam Ravnborg #define IOP_MSGSTATUS_SENT 2 /* message sent, awaiting reply */ 5549148020SSam Ravnborg #define IOP_MSGSTATUS_COMPLETE 3 /* message complete and reply rcvd */ 5649148020SSam Ravnborg #define IOP_MSGSTATUS_UNSOL 6 /* message is unsolicited */ 5749148020SSam Ravnborg 5849148020SSam Ravnborg /* IOP memory addresses of the members of the mac_iop_kernel structure. */ 5949148020SSam Ravnborg 6049148020SSam Ravnborg #define IOP_ADDR_MAX_SEND_CHAN 0x0200 6149148020SSam Ravnborg #define IOP_ADDR_SEND_STATE 0x0201 6249148020SSam Ravnborg #define IOP_ADDR_PATCH_CTRL 0x021F 6349148020SSam Ravnborg #define IOP_ADDR_SEND_MSG 0x0220 6449148020SSam Ravnborg #define IOP_ADDR_MAX_RECV_CHAN 0x0300 6549148020SSam Ravnborg #define IOP_ADDR_RECV_STATE 0x0301 6649148020SSam Ravnborg #define IOP_ADDR_ALIVE 0x031F 6749148020SSam Ravnborg #define IOP_ADDR_RECV_MSG 0x0320 6849148020SSam Ravnborg 6949148020SSam Ravnborg #ifndef __ASSEMBLY__ 7049148020SSam Ravnborg 7149148020SSam Ravnborg /* 7249148020SSam Ravnborg * IOP Control registers, staggered because in usual Apple style they were 7349148020SSam Ravnborg * too lazy to decode the A0 bit. This structure is assumed to begin at 7449148020SSam Ravnborg * one of the xxx_IOP_BASE addresses given above. 7549148020SSam Ravnborg */ 7649148020SSam Ravnborg 7749148020SSam Ravnborg struct mac_iop { 7849148020SSam Ravnborg __u8 ram_addr_hi; /* shared RAM address hi byte */ 7949148020SSam Ravnborg __u8 pad0; 8049148020SSam Ravnborg __u8 ram_addr_lo; /* shared RAM address lo byte */ 8149148020SSam Ravnborg __u8 pad1; 8249148020SSam Ravnborg __u8 status_ctrl; /* status/control register */ 8349148020SSam Ravnborg __u8 pad2[3]; 8449148020SSam Ravnborg __u8 ram_data; /* RAM data byte at ramhi/lo */ 8549148020SSam Ravnborg 8649148020SSam Ravnborg __u8 pad3[23]; 8749148020SSam Ravnborg 8849148020SSam Ravnborg /* Bypass-mode hardware access registers */ 8949148020SSam Ravnborg 9049148020SSam Ravnborg union { 9149148020SSam Ravnborg struct { /* SCC registers */ 9249148020SSam Ravnborg __u8 sccb_cmd; /* SCC B command reg */ 9349148020SSam Ravnborg __u8 pad4; 9449148020SSam Ravnborg __u8 scca_cmd; /* SCC A command reg */ 9549148020SSam Ravnborg __u8 pad5; 9649148020SSam Ravnborg __u8 sccb_data; /* SCC B data */ 9749148020SSam Ravnborg __u8 pad6; 9849148020SSam Ravnborg __u8 scca_data; /* SCC A data */ 9949148020SSam Ravnborg } scc_regs; 10049148020SSam Ravnborg 10149148020SSam Ravnborg struct { /* ISM registers */ 10249148020SSam Ravnborg __u8 wdata; /* write a data byte */ 10349148020SSam Ravnborg __u8 pad7; 10449148020SSam Ravnborg __u8 wmark; /* write a mark byte */ 10549148020SSam Ravnborg __u8 pad8; 10649148020SSam Ravnborg __u8 wcrc; /* write 2-byte crc to disk */ 10749148020SSam Ravnborg __u8 pad9; 10849148020SSam Ravnborg __u8 wparams; /* write the param regs */ 10949148020SSam Ravnborg __u8 pad10; 11049148020SSam Ravnborg __u8 wphase; /* write the phase states & dirs */ 11149148020SSam Ravnborg __u8 pad11; 11249148020SSam Ravnborg __u8 wsetup; /* write the setup register */ 11349148020SSam Ravnborg __u8 pad12; 11449148020SSam Ravnborg __u8 wzeroes; /* mode reg: 1's clr bits, 0's are x */ 11549148020SSam Ravnborg __u8 pad13; 11649148020SSam Ravnborg __u8 wones; /* mode reg: 1's set bits, 0's are x */ 11749148020SSam Ravnborg __u8 pad14; 11849148020SSam Ravnborg __u8 rdata; /* read a data byte */ 11949148020SSam Ravnborg __u8 pad15; 12049148020SSam Ravnborg __u8 rmark; /* read a mark byte */ 12149148020SSam Ravnborg __u8 pad16; 12249148020SSam Ravnborg __u8 rerror; /* read the error register */ 12349148020SSam Ravnborg __u8 pad17; 12449148020SSam Ravnborg __u8 rparams; /* read the param regs */ 12549148020SSam Ravnborg __u8 pad18; 12649148020SSam Ravnborg __u8 rphase; /* read the phase states & dirs */ 12749148020SSam Ravnborg __u8 pad19; 12849148020SSam Ravnborg __u8 rsetup; /* read the setup register */ 12949148020SSam Ravnborg __u8 pad20; 13049148020SSam Ravnborg __u8 rmode; /* read the mode register */ 13149148020SSam Ravnborg __u8 pad21; 13249148020SSam Ravnborg __u8 rhandshake; /* read the handshake register */ 13349148020SSam Ravnborg } ism_regs; 13449148020SSam Ravnborg } b; 13549148020SSam Ravnborg }; 13649148020SSam Ravnborg 13749148020SSam Ravnborg /* This structure is used to track IOP messages in the Linux kernel */ 13849148020SSam Ravnborg 13949148020SSam Ravnborg struct iop_msg { 14049148020SSam Ravnborg struct iop_msg *next; /* next message in queue or NULL */ 14149148020SSam Ravnborg uint iop_num; /* IOP number */ 14249148020SSam Ravnborg uint channel; /* channel number */ 14349148020SSam Ravnborg void *caller_priv; /* caller private data */ 14449148020SSam Ravnborg int status; /* status of this message */ 14549148020SSam Ravnborg __u8 message[IOP_MSG_LEN]; /* the message being sent/received */ 14649148020SSam Ravnborg __u8 reply[IOP_MSG_LEN]; /* the reply to the message */ 14749148020SSam Ravnborg void (*handler)(struct iop_msg *); 14849148020SSam Ravnborg /* function to call when reply recvd */ 14949148020SSam Ravnborg }; 15049148020SSam Ravnborg 15149148020SSam Ravnborg extern int iop_scc_present,iop_ism_present; 15249148020SSam Ravnborg 15349148020SSam Ravnborg extern int iop_listen(uint, uint, 15449148020SSam Ravnborg void (*handler)(struct iop_msg *), 15549148020SSam Ravnborg const char *); 15649148020SSam Ravnborg extern int iop_send_message(uint, uint, void *, uint, __u8 *, 15749148020SSam Ravnborg void (*)(struct iop_msg *)); 15849148020SSam Ravnborg extern void iop_complete_message(struct iop_msg *); 15949148020SSam Ravnborg extern void iop_upload_code(uint, __u8 *, uint, __u16); 16049148020SSam Ravnborg extern void iop_download_code(uint, __u8 *, uint, __u16); 161*92178fcaSFinn Thain extern __u8 *iop_compare_code(uint, __u8 *, uint, __u16); 16249148020SSam Ravnborg extern void iop_ism_irq_poll(uint); 163ed04c97dSFinn Thain 164ed04c97dSFinn Thain extern void iop_register_interrupts(void); 16549148020SSam Ravnborg 166 #endif /* __ASSEMBLY__ */ 167