1*384740dcSRalf Baechle /* 2*384740dcSRalf Baechle * IDT RC32434 specific CPU feature overrides 3*384740dcSRalf Baechle * 4*384740dcSRalf Baechle * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org> 5*384740dcSRalf Baechle * 6*384740dcSRalf Baechle * This file was derived from: include/asm-mips/cpu-features.h 7*384740dcSRalf Baechle * Copyright (C) 2003, 2004 Ralf Baechle 8*384740dcSRalf Baechle * Copyright (C) 2004 Maciej W. Rozycki 9*384740dcSRalf Baechle * 10*384740dcSRalf Baechle * This program is free software; you can redistribute it and/or 11*384740dcSRalf Baechle * modify it under the terms of the GNU General Public License 12*384740dcSRalf Baechle * as published by the Free Software Foundation; either version 2 13*384740dcSRalf Baechle * of the License, or (at your option) any later version. 14*384740dcSRalf Baechle * 15*384740dcSRalf Baechle * This program is distributed in the hope that it will be useful, 16*384740dcSRalf Baechle * but WITHOUT ANY WARRANTY; without even the implied warranty of 17*384740dcSRalf Baechle * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18*384740dcSRalf Baechle * GNU General Public License for more details. 19*384740dcSRalf Baechle * 20*384740dcSRalf Baechle * You should have received a copy of the GNU General Public License 21*384740dcSRalf Baechle * along with this program; if not, write to the 22*384740dcSRalf Baechle * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, 23*384740dcSRalf Baechle * Boston, MA 02110-1301, USA. 24*384740dcSRalf Baechle */ 25*384740dcSRalf Baechle #ifndef __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H 26*384740dcSRalf Baechle #define __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H 27*384740dcSRalf Baechle 28*384740dcSRalf Baechle /* 29*384740dcSRalf Baechle * The IDT RC32434 SOC has a built-in MIPS 4Kc core. 30*384740dcSRalf Baechle */ 31*384740dcSRalf Baechle #define cpu_has_tlb 1 32*384740dcSRalf Baechle #define cpu_has_4kex 1 33*384740dcSRalf Baechle #define cpu_has_3k_cache 0 34*384740dcSRalf Baechle #define cpu_has_4k_cache 1 35*384740dcSRalf Baechle #define cpu_has_tx39_cache 0 36*384740dcSRalf Baechle #define cpu_has_sb1_cache 0 37*384740dcSRalf Baechle #define cpu_has_fpu 0 38*384740dcSRalf Baechle #define cpu_has_32fpr 0 39*384740dcSRalf Baechle #define cpu_has_counter 1 40*384740dcSRalf Baechle #define cpu_has_watch 1 41*384740dcSRalf Baechle #define cpu_has_divec 1 42*384740dcSRalf Baechle #define cpu_has_vce 0 43*384740dcSRalf Baechle #define cpu_has_cache_cdex_p 0 44*384740dcSRalf Baechle #define cpu_has_cache_cdex_s 0 45*384740dcSRalf Baechle #define cpu_has_prefetch 1 46*384740dcSRalf Baechle #define cpu_has_mcheck 1 47*384740dcSRalf Baechle #define cpu_has_ejtag 1 48*384740dcSRalf Baechle #define cpu_has_llsc 1 49*384740dcSRalf Baechle 50*384740dcSRalf Baechle #define cpu_has_mips16 0 51*384740dcSRalf Baechle #define cpu_has_mdmx 0 52*384740dcSRalf Baechle #define cpu_has_mips3d 0 53*384740dcSRalf Baechle #define cpu_has_smartmips 0 54*384740dcSRalf Baechle 55*384740dcSRalf Baechle #define cpu_has_vtag_icache 0 56*384740dcSRalf Baechle /* #define cpu_has_dc_aliases ? */ 57*384740dcSRalf Baechle /* #define cpu_has_ic_fills_f_dc ? */ 58*384740dcSRalf Baechle /* #define cpu_has_pindexed_dcache ? */ 59*384740dcSRalf Baechle 60*384740dcSRalf Baechle /* #define cpu_icache_snoops_remote_store ? */ 61*384740dcSRalf Baechle 62*384740dcSRalf Baechle #define cpu_has_mips32r1 1 63*384740dcSRalf Baechle #define cpu_has_mips32r2 0 64*384740dcSRalf Baechle #define cpu_has_mips64r1 0 65*384740dcSRalf Baechle #define cpu_has_mips64r2 0 66*384740dcSRalf Baechle 67*384740dcSRalf Baechle #define cpu_has_dsp 0 68*384740dcSRalf Baechle #define cpu_has_mipsmt 0 69*384740dcSRalf Baechle 70*384740dcSRalf Baechle /* #define cpu_has_nofpuex ? */ 71*384740dcSRalf Baechle #define cpu_has_64bits 0 72*384740dcSRalf Baechle #define cpu_has_64bit_zero_reg 0 73*384740dcSRalf Baechle #define cpu_has_64bit_gp_regs 0 74*384740dcSRalf Baechle #define cpu_has_64bit_addresses 0 75*384740dcSRalf Baechle 76*384740dcSRalf Baechle #define cpu_has_inclusive_pcaches 0 77*384740dcSRalf Baechle 78*384740dcSRalf Baechle #define cpu_dcache_line_size() 16 79*384740dcSRalf Baechle #define cpu_icache_line_size() 16 80*384740dcSRalf Baechle 81*384740dcSRalf Baechle #endif /* __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H */ 82