1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org) 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 9 */ 10 #include <linux/cpu_pm.h> 11 #include <linux/hardirq.h> 12 #include <linux/init.h> 13 #include <linux/highmem.h> 14 #include <linux/kernel.h> 15 #include <linux/linkage.h> 16 #include <linux/preempt.h> 17 #include <linux/sched.h> 18 #include <linux/smp.h> 19 #include <linux/mm.h> 20 #include <linux/export.h> 21 #include <linux/bitops.h> 22 23 #include <asm/bcache.h> 24 #include <asm/bootinfo.h> 25 #include <asm/cache.h> 26 #include <asm/cacheops.h> 27 #include <asm/cpu.h> 28 #include <asm/cpu-features.h> 29 #include <asm/cpu-type.h> 30 #include <asm/io.h> 31 #include <asm/page.h> 32 #include <asm/pgtable.h> 33 #include <asm/r4kcache.h> 34 #include <asm/sections.h> 35 #include <asm/mmu_context.h> 36 #include <asm/war.h> 37 #include <asm/cacheflush.h> /* for run_uncached() */ 38 #include <asm/traps.h> 39 #include <asm/dma-coherence.h> 40 #include <asm/mips-cps.h> 41 42 /* 43 * Bits describing what cache ops an SMP callback function may perform. 44 * 45 * R4K_HIT - Virtual user or kernel address based cache operations. The 46 * active_mm must be checked before using user addresses, falling 47 * back to kmap. 48 * R4K_INDEX - Index based cache operations. 49 */ 50 51 #define R4K_HIT BIT(0) 52 #define R4K_INDEX BIT(1) 53 54 /** 55 * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core. 56 * @type: Type of cache operations (R4K_HIT or R4K_INDEX). 57 * 58 * Decides whether a cache op needs to be performed on every core in the system. 59 * This may change depending on the @type of cache operation, as well as the set 60 * of online CPUs, so preemption should be disabled by the caller to prevent CPU 61 * hotplug from changing the result. 62 * 63 * Returns: 1 if the cache operation @type should be done on every core in 64 * the system. 65 * 0 if the cache operation @type is globalized and only needs to 66 * be performed on a simple CPU. 67 */ 68 static inline bool r4k_op_needs_ipi(unsigned int type) 69 { 70 /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */ 71 if (type == R4K_HIT && mips_cm_present()) 72 return false; 73 74 /* 75 * Hardware doesn't globalize the required cache ops, so SMP calls may 76 * be needed, but only if there are foreign CPUs (non-siblings with 77 * separate caches). 78 */ 79 /* cpu_foreign_map[] undeclared when !CONFIG_SMP */ 80 #ifdef CONFIG_SMP 81 return !cpumask_empty(&cpu_foreign_map[0]); 82 #else 83 return false; 84 #endif 85 } 86 87 /* 88 * Special Variant of smp_call_function for use by cache functions: 89 * 90 * o No return value 91 * o collapses to normal function call on UP kernels 92 * o collapses to normal function call on systems with a single shared 93 * primary cache. 94 * o doesn't disable interrupts on the local CPU 95 */ 96 static inline void r4k_on_each_cpu(unsigned int type, 97 void (*func)(void *info), void *info) 98 { 99 preempt_disable(); 100 if (r4k_op_needs_ipi(type)) 101 smp_call_function_many(&cpu_foreign_map[smp_processor_id()], 102 func, info, 1); 103 func(info); 104 preempt_enable(); 105 } 106 107 /* 108 * Must die. 109 */ 110 static unsigned long icache_size __read_mostly; 111 static unsigned long dcache_size __read_mostly; 112 static unsigned long vcache_size __read_mostly; 113 static unsigned long scache_size __read_mostly; 114 115 /* 116 * Dummy cache handling routines for machines without boardcaches 117 */ 118 static void cache_noop(void) {} 119 120 static struct bcache_ops no_sc_ops = { 121 .bc_enable = (void *)cache_noop, 122 .bc_disable = (void *)cache_noop, 123 .bc_wback_inv = (void *)cache_noop, 124 .bc_inv = (void *)cache_noop 125 }; 126 127 struct bcache_ops *bcops = &no_sc_ops; 128 129 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) 130 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) 131 132 #define R4600_HIT_CACHEOP_WAR_IMPL \ 133 do { \ 134 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \ 135 *(volatile unsigned long *)CKSEG1; \ 136 if (R4600_V1_HIT_CACHEOP_WAR) \ 137 __asm__ __volatile__("nop;nop;nop;nop"); \ 138 } while (0) 139 140 static void (*r4k_blast_dcache_page)(unsigned long addr); 141 142 static inline void r4k_blast_dcache_page_dc32(unsigned long addr) 143 { 144 R4600_HIT_CACHEOP_WAR_IMPL; 145 blast_dcache32_page(addr); 146 } 147 148 static inline void r4k_blast_dcache_page_dc64(unsigned long addr) 149 { 150 blast_dcache64_page(addr); 151 } 152 153 static inline void r4k_blast_dcache_page_dc128(unsigned long addr) 154 { 155 blast_dcache128_page(addr); 156 } 157 158 static void r4k_blast_dcache_page_setup(void) 159 { 160 unsigned long dc_lsize = cpu_dcache_line_size(); 161 162 switch (dc_lsize) { 163 case 0: 164 r4k_blast_dcache_page = (void *)cache_noop; 165 break; 166 case 16: 167 r4k_blast_dcache_page = blast_dcache16_page; 168 break; 169 case 32: 170 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; 171 break; 172 case 64: 173 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64; 174 break; 175 case 128: 176 r4k_blast_dcache_page = r4k_blast_dcache_page_dc128; 177 break; 178 default: 179 break; 180 } 181 } 182 183 #ifndef CONFIG_EVA 184 #define r4k_blast_dcache_user_page r4k_blast_dcache_page 185 #else 186 187 static void (*r4k_blast_dcache_user_page)(unsigned long addr); 188 189 static void r4k_blast_dcache_user_page_setup(void) 190 { 191 unsigned long dc_lsize = cpu_dcache_line_size(); 192 193 if (dc_lsize == 0) 194 r4k_blast_dcache_user_page = (void *)cache_noop; 195 else if (dc_lsize == 16) 196 r4k_blast_dcache_user_page = blast_dcache16_user_page; 197 else if (dc_lsize == 32) 198 r4k_blast_dcache_user_page = blast_dcache32_user_page; 199 else if (dc_lsize == 64) 200 r4k_blast_dcache_user_page = blast_dcache64_user_page; 201 } 202 203 #endif 204 205 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr); 206 207 static void r4k_blast_dcache_page_indexed_setup(void) 208 { 209 unsigned long dc_lsize = cpu_dcache_line_size(); 210 211 if (dc_lsize == 0) 212 r4k_blast_dcache_page_indexed = (void *)cache_noop; 213 else if (dc_lsize == 16) 214 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; 215 else if (dc_lsize == 32) 216 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; 217 else if (dc_lsize == 64) 218 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed; 219 else if (dc_lsize == 128) 220 r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed; 221 } 222 223 void (* r4k_blast_dcache)(void); 224 EXPORT_SYMBOL(r4k_blast_dcache); 225 226 static void r4k_blast_dcache_setup(void) 227 { 228 unsigned long dc_lsize = cpu_dcache_line_size(); 229 230 if (dc_lsize == 0) 231 r4k_blast_dcache = (void *)cache_noop; 232 else if (dc_lsize == 16) 233 r4k_blast_dcache = blast_dcache16; 234 else if (dc_lsize == 32) 235 r4k_blast_dcache = blast_dcache32; 236 else if (dc_lsize == 64) 237 r4k_blast_dcache = blast_dcache64; 238 else if (dc_lsize == 128) 239 r4k_blast_dcache = blast_dcache128; 240 } 241 242 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */ 243 #define JUMP_TO_ALIGN(order) \ 244 __asm__ __volatile__( \ 245 "b\t1f\n\t" \ 246 ".align\t" #order "\n\t" \ 247 "1:\n\t" \ 248 ) 249 #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */ 250 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11) 251 252 static inline void blast_r4600_v1_icache32(void) 253 { 254 unsigned long flags; 255 256 local_irq_save(flags); 257 blast_icache32(); 258 local_irq_restore(flags); 259 } 260 261 static inline void tx49_blast_icache32(void) 262 { 263 unsigned long start = INDEX_BASE; 264 unsigned long end = start + current_cpu_data.icache.waysize; 265 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; 266 unsigned long ws_end = current_cpu_data.icache.ways << 267 current_cpu_data.icache.waybit; 268 unsigned long ws, addr; 269 270 CACHE32_UNROLL32_ALIGN2; 271 /* I'm in even chunk. blast odd chunks */ 272 for (ws = 0; ws < ws_end; ws += ws_inc) 273 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 274 cache32_unroll32(addr|ws, Index_Invalidate_I); 275 CACHE32_UNROLL32_ALIGN; 276 /* I'm in odd chunk. blast even chunks */ 277 for (ws = 0; ws < ws_end; ws += ws_inc) 278 for (addr = start; addr < end; addr += 0x400 * 2) 279 cache32_unroll32(addr|ws, Index_Invalidate_I); 280 } 281 282 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) 283 { 284 unsigned long flags; 285 286 local_irq_save(flags); 287 blast_icache32_page_indexed(page); 288 local_irq_restore(flags); 289 } 290 291 static inline void tx49_blast_icache32_page_indexed(unsigned long page) 292 { 293 unsigned long indexmask = current_cpu_data.icache.waysize - 1; 294 unsigned long start = INDEX_BASE + (page & indexmask); 295 unsigned long end = start + PAGE_SIZE; 296 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; 297 unsigned long ws_end = current_cpu_data.icache.ways << 298 current_cpu_data.icache.waybit; 299 unsigned long ws, addr; 300 301 CACHE32_UNROLL32_ALIGN2; 302 /* I'm in even chunk. blast odd chunks */ 303 for (ws = 0; ws < ws_end; ws += ws_inc) 304 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 305 cache32_unroll32(addr|ws, Index_Invalidate_I); 306 CACHE32_UNROLL32_ALIGN; 307 /* I'm in odd chunk. blast even chunks */ 308 for (ws = 0; ws < ws_end; ws += ws_inc) 309 for (addr = start; addr < end; addr += 0x400 * 2) 310 cache32_unroll32(addr|ws, Index_Invalidate_I); 311 } 312 313 static void (* r4k_blast_icache_page)(unsigned long addr); 314 315 static void r4k_blast_icache_page_setup(void) 316 { 317 unsigned long ic_lsize = cpu_icache_line_size(); 318 319 if (ic_lsize == 0) 320 r4k_blast_icache_page = (void *)cache_noop; 321 else if (ic_lsize == 16) 322 r4k_blast_icache_page = blast_icache16_page; 323 else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2) 324 r4k_blast_icache_page = loongson2_blast_icache32_page; 325 else if (ic_lsize == 32) 326 r4k_blast_icache_page = blast_icache32_page; 327 else if (ic_lsize == 64) 328 r4k_blast_icache_page = blast_icache64_page; 329 else if (ic_lsize == 128) 330 r4k_blast_icache_page = blast_icache128_page; 331 } 332 333 #ifndef CONFIG_EVA 334 #define r4k_blast_icache_user_page r4k_blast_icache_page 335 #else 336 337 static void (*r4k_blast_icache_user_page)(unsigned long addr); 338 339 static void r4k_blast_icache_user_page_setup(void) 340 { 341 unsigned long ic_lsize = cpu_icache_line_size(); 342 343 if (ic_lsize == 0) 344 r4k_blast_icache_user_page = (void *)cache_noop; 345 else if (ic_lsize == 16) 346 r4k_blast_icache_user_page = blast_icache16_user_page; 347 else if (ic_lsize == 32) 348 r4k_blast_icache_user_page = blast_icache32_user_page; 349 else if (ic_lsize == 64) 350 r4k_blast_icache_user_page = blast_icache64_user_page; 351 } 352 353 #endif 354 355 static void (* r4k_blast_icache_page_indexed)(unsigned long addr); 356 357 static void r4k_blast_icache_page_indexed_setup(void) 358 { 359 unsigned long ic_lsize = cpu_icache_line_size(); 360 361 if (ic_lsize == 0) 362 r4k_blast_icache_page_indexed = (void *)cache_noop; 363 else if (ic_lsize == 16) 364 r4k_blast_icache_page_indexed = blast_icache16_page_indexed; 365 else if (ic_lsize == 32) { 366 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) 367 r4k_blast_icache_page_indexed = 368 blast_icache32_r4600_v1_page_indexed; 369 else if (TX49XX_ICACHE_INDEX_INV_WAR) 370 r4k_blast_icache_page_indexed = 371 tx49_blast_icache32_page_indexed; 372 else if (current_cpu_type() == CPU_LOONGSON2) 373 r4k_blast_icache_page_indexed = 374 loongson2_blast_icache32_page_indexed; 375 else 376 r4k_blast_icache_page_indexed = 377 blast_icache32_page_indexed; 378 } else if (ic_lsize == 64) 379 r4k_blast_icache_page_indexed = blast_icache64_page_indexed; 380 } 381 382 void (* r4k_blast_icache)(void); 383 EXPORT_SYMBOL(r4k_blast_icache); 384 385 static void r4k_blast_icache_setup(void) 386 { 387 unsigned long ic_lsize = cpu_icache_line_size(); 388 389 if (ic_lsize == 0) 390 r4k_blast_icache = (void *)cache_noop; 391 else if (ic_lsize == 16) 392 r4k_blast_icache = blast_icache16; 393 else if (ic_lsize == 32) { 394 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) 395 r4k_blast_icache = blast_r4600_v1_icache32; 396 else if (TX49XX_ICACHE_INDEX_INV_WAR) 397 r4k_blast_icache = tx49_blast_icache32; 398 else if (current_cpu_type() == CPU_LOONGSON2) 399 r4k_blast_icache = loongson2_blast_icache32; 400 else 401 r4k_blast_icache = blast_icache32; 402 } else if (ic_lsize == 64) 403 r4k_blast_icache = blast_icache64; 404 else if (ic_lsize == 128) 405 r4k_blast_icache = blast_icache128; 406 } 407 408 static void (* r4k_blast_scache_page)(unsigned long addr); 409 410 static void r4k_blast_scache_page_setup(void) 411 { 412 unsigned long sc_lsize = cpu_scache_line_size(); 413 414 if (scache_size == 0) 415 r4k_blast_scache_page = (void *)cache_noop; 416 else if (sc_lsize == 16) 417 r4k_blast_scache_page = blast_scache16_page; 418 else if (sc_lsize == 32) 419 r4k_blast_scache_page = blast_scache32_page; 420 else if (sc_lsize == 64) 421 r4k_blast_scache_page = blast_scache64_page; 422 else if (sc_lsize == 128) 423 r4k_blast_scache_page = blast_scache128_page; 424 } 425 426 static void (* r4k_blast_scache_page_indexed)(unsigned long addr); 427 428 static void r4k_blast_scache_page_indexed_setup(void) 429 { 430 unsigned long sc_lsize = cpu_scache_line_size(); 431 432 if (scache_size == 0) 433 r4k_blast_scache_page_indexed = (void *)cache_noop; 434 else if (sc_lsize == 16) 435 r4k_blast_scache_page_indexed = blast_scache16_page_indexed; 436 else if (sc_lsize == 32) 437 r4k_blast_scache_page_indexed = blast_scache32_page_indexed; 438 else if (sc_lsize == 64) 439 r4k_blast_scache_page_indexed = blast_scache64_page_indexed; 440 else if (sc_lsize == 128) 441 r4k_blast_scache_page_indexed = blast_scache128_page_indexed; 442 } 443 444 static void (* r4k_blast_scache)(void); 445 446 static void r4k_blast_scache_setup(void) 447 { 448 unsigned long sc_lsize = cpu_scache_line_size(); 449 450 if (scache_size == 0) 451 r4k_blast_scache = (void *)cache_noop; 452 else if (sc_lsize == 16) 453 r4k_blast_scache = blast_scache16; 454 else if (sc_lsize == 32) 455 r4k_blast_scache = blast_scache32; 456 else if (sc_lsize == 64) 457 r4k_blast_scache = blast_scache64; 458 else if (sc_lsize == 128) 459 r4k_blast_scache = blast_scache128; 460 } 461 462 static void (*r4k_blast_scache_node)(long node); 463 464 static void r4k_blast_scache_node_setup(void) 465 { 466 unsigned long sc_lsize = cpu_scache_line_size(); 467 468 if (current_cpu_type() != CPU_LOONGSON3) 469 r4k_blast_scache_node = (void *)cache_noop; 470 else if (sc_lsize == 16) 471 r4k_blast_scache_node = blast_scache16_node; 472 else if (sc_lsize == 32) 473 r4k_blast_scache_node = blast_scache32_node; 474 else if (sc_lsize == 64) 475 r4k_blast_scache_node = blast_scache64_node; 476 else if (sc_lsize == 128) 477 r4k_blast_scache_node = blast_scache128_node; 478 } 479 480 static inline void local_r4k___flush_cache_all(void * args) 481 { 482 switch (current_cpu_type()) { 483 case CPU_LOONGSON2: 484 case CPU_R4000SC: 485 case CPU_R4000MC: 486 case CPU_R4400SC: 487 case CPU_R4400MC: 488 case CPU_R10000: 489 case CPU_R12000: 490 case CPU_R14000: 491 case CPU_R16000: 492 /* 493 * These caches are inclusive caches, that is, if something 494 * is not cached in the S-cache, we know it also won't be 495 * in one of the primary caches. 496 */ 497 r4k_blast_scache(); 498 break; 499 500 case CPU_LOONGSON3: 501 /* Use get_ebase_cpunum() for both NUMA=y/n */ 502 r4k_blast_scache_node(get_ebase_cpunum() >> 2); 503 break; 504 505 case CPU_BMIPS5000: 506 r4k_blast_scache(); 507 __sync(); 508 break; 509 510 default: 511 r4k_blast_dcache(); 512 r4k_blast_icache(); 513 break; 514 } 515 } 516 517 static void r4k___flush_cache_all(void) 518 { 519 r4k_on_each_cpu(R4K_INDEX, local_r4k___flush_cache_all, NULL); 520 } 521 522 /** 523 * has_valid_asid() - Determine if an mm already has an ASID. 524 * @mm: Memory map. 525 * @type: R4K_HIT or R4K_INDEX, type of cache op. 526 * 527 * Determines whether @mm already has an ASID on any of the CPUs which cache ops 528 * of type @type within an r4k_on_each_cpu() call will affect. If 529 * r4k_on_each_cpu() does an SMP call to a single VPE in each core, then the 530 * scope of the operation is confined to sibling CPUs, otherwise all online CPUs 531 * will need to be checked. 532 * 533 * Must be called in non-preemptive context. 534 * 535 * Returns: 1 if the CPUs affected by @type cache ops have an ASID for @mm. 536 * 0 otherwise. 537 */ 538 static inline int has_valid_asid(const struct mm_struct *mm, unsigned int type) 539 { 540 unsigned int i; 541 const cpumask_t *mask = cpu_present_mask; 542 543 if (cpu_has_mmid) 544 return cpu_context(0, mm) != 0; 545 546 /* cpu_sibling_map[] undeclared when !CONFIG_SMP */ 547 #ifdef CONFIG_SMP 548 /* 549 * If r4k_on_each_cpu does SMP calls, it does them to a single VPE in 550 * each foreign core, so we only need to worry about siblings. 551 * Otherwise we need to worry about all present CPUs. 552 */ 553 if (r4k_op_needs_ipi(type)) 554 mask = &cpu_sibling_map[smp_processor_id()]; 555 #endif 556 for_each_cpu(i, mask) 557 if (cpu_context(i, mm)) 558 return 1; 559 return 0; 560 } 561 562 static void r4k__flush_cache_vmap(void) 563 { 564 r4k_blast_dcache(); 565 } 566 567 static void r4k__flush_cache_vunmap(void) 568 { 569 r4k_blast_dcache(); 570 } 571 572 /* 573 * Note: flush_tlb_range() assumes flush_cache_range() sufficiently flushes 574 * whole caches when vma is executable. 575 */ 576 static inline void local_r4k_flush_cache_range(void * args) 577 { 578 struct vm_area_struct *vma = args; 579 int exec = vma->vm_flags & VM_EXEC; 580 581 if (!has_valid_asid(vma->vm_mm, R4K_INDEX)) 582 return; 583 584 /* 585 * If dcache can alias, we must blast it since mapping is changing. 586 * If executable, we must ensure any dirty lines are written back far 587 * enough to be visible to icache. 588 */ 589 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) 590 r4k_blast_dcache(); 591 /* If executable, blast stale lines from icache */ 592 if (exec) 593 r4k_blast_icache(); 594 } 595 596 static void r4k_flush_cache_range(struct vm_area_struct *vma, 597 unsigned long start, unsigned long end) 598 { 599 int exec = vma->vm_flags & VM_EXEC; 600 601 if (cpu_has_dc_aliases || exec) 602 r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_range, vma); 603 } 604 605 static inline void local_r4k_flush_cache_mm(void * args) 606 { 607 struct mm_struct *mm = args; 608 609 if (!has_valid_asid(mm, R4K_INDEX)) 610 return; 611 612 /* 613 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we 614 * only flush the primary caches but R1x000 behave sane ... 615 * R4000SC and R4400SC indexed S-cache ops also invalidate primary 616 * caches, so we can bail out early. 617 */ 618 if (current_cpu_type() == CPU_R4000SC || 619 current_cpu_type() == CPU_R4000MC || 620 current_cpu_type() == CPU_R4400SC || 621 current_cpu_type() == CPU_R4400MC) { 622 r4k_blast_scache(); 623 return; 624 } 625 626 r4k_blast_dcache(); 627 } 628 629 static void r4k_flush_cache_mm(struct mm_struct *mm) 630 { 631 if (!cpu_has_dc_aliases) 632 return; 633 634 r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_mm, mm); 635 } 636 637 struct flush_cache_page_args { 638 struct vm_area_struct *vma; 639 unsigned long addr; 640 unsigned long pfn; 641 }; 642 643 static inline void local_r4k_flush_cache_page(void *args) 644 { 645 struct flush_cache_page_args *fcp_args = args; 646 struct vm_area_struct *vma = fcp_args->vma; 647 unsigned long addr = fcp_args->addr; 648 struct page *page = pfn_to_page(fcp_args->pfn); 649 int exec = vma->vm_flags & VM_EXEC; 650 struct mm_struct *mm = vma->vm_mm; 651 int map_coherent = 0; 652 pgd_t *pgdp; 653 pud_t *pudp; 654 pmd_t *pmdp; 655 pte_t *ptep; 656 void *vaddr; 657 658 /* 659 * If owns no valid ASID yet, cannot possibly have gotten 660 * this page into the cache. 661 */ 662 if (!has_valid_asid(mm, R4K_HIT)) 663 return; 664 665 addr &= PAGE_MASK; 666 pgdp = pgd_offset(mm, addr); 667 pudp = pud_offset(pgdp, addr); 668 pmdp = pmd_offset(pudp, addr); 669 ptep = pte_offset(pmdp, addr); 670 671 /* 672 * If the page isn't marked valid, the page cannot possibly be 673 * in the cache. 674 */ 675 if (!(pte_present(*ptep))) 676 return; 677 678 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) 679 vaddr = NULL; 680 else { 681 /* 682 * Use kmap_coherent or kmap_atomic to do flushes for 683 * another ASID than the current one. 684 */ 685 map_coherent = (cpu_has_dc_aliases && 686 page_mapcount(page) && 687 !Page_dcache_dirty(page)); 688 if (map_coherent) 689 vaddr = kmap_coherent(page, addr); 690 else 691 vaddr = kmap_atomic(page); 692 addr = (unsigned long)vaddr; 693 } 694 695 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { 696 vaddr ? r4k_blast_dcache_page(addr) : 697 r4k_blast_dcache_user_page(addr); 698 if (exec && !cpu_icache_snoops_remote_store) 699 r4k_blast_scache_page(addr); 700 } 701 if (exec) { 702 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { 703 drop_mmu_context(mm); 704 } else 705 vaddr ? r4k_blast_icache_page(addr) : 706 r4k_blast_icache_user_page(addr); 707 } 708 709 if (vaddr) { 710 if (map_coherent) 711 kunmap_coherent(); 712 else 713 kunmap_atomic(vaddr); 714 } 715 } 716 717 static void r4k_flush_cache_page(struct vm_area_struct *vma, 718 unsigned long addr, unsigned long pfn) 719 { 720 struct flush_cache_page_args args; 721 722 args.vma = vma; 723 args.addr = addr; 724 args.pfn = pfn; 725 726 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_page, &args); 727 } 728 729 static inline void local_r4k_flush_data_cache_page(void * addr) 730 { 731 r4k_blast_dcache_page((unsigned long) addr); 732 } 733 734 static void r4k_flush_data_cache_page(unsigned long addr) 735 { 736 if (in_atomic()) 737 local_r4k_flush_data_cache_page((void *)addr); 738 else 739 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_data_cache_page, 740 (void *) addr); 741 } 742 743 struct flush_icache_range_args { 744 unsigned long start; 745 unsigned long end; 746 unsigned int type; 747 bool user; 748 }; 749 750 static inline void __local_r4k_flush_icache_range(unsigned long start, 751 unsigned long end, 752 unsigned int type, 753 bool user) 754 { 755 if (!cpu_has_ic_fills_f_dc) { 756 if (type == R4K_INDEX || 757 (type & R4K_INDEX && end - start >= dcache_size)) { 758 r4k_blast_dcache(); 759 } else { 760 R4600_HIT_CACHEOP_WAR_IMPL; 761 if (user) 762 protected_blast_dcache_range(start, end); 763 else 764 blast_dcache_range(start, end); 765 } 766 } 767 768 if (type == R4K_INDEX || 769 (type & R4K_INDEX && end - start > icache_size)) 770 r4k_blast_icache(); 771 else { 772 switch (boot_cpu_type()) { 773 case CPU_LOONGSON2: 774 protected_loongson2_blast_icache_range(start, end); 775 break; 776 777 default: 778 if (user) 779 protected_blast_icache_range(start, end); 780 else 781 blast_icache_range(start, end); 782 break; 783 } 784 } 785 } 786 787 static inline void local_r4k_flush_icache_range(unsigned long start, 788 unsigned long end) 789 { 790 __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, false); 791 } 792 793 static inline void local_r4k_flush_icache_user_range(unsigned long start, 794 unsigned long end) 795 { 796 __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, true); 797 } 798 799 static inline void local_r4k_flush_icache_range_ipi(void *args) 800 { 801 struct flush_icache_range_args *fir_args = args; 802 unsigned long start = fir_args->start; 803 unsigned long end = fir_args->end; 804 unsigned int type = fir_args->type; 805 bool user = fir_args->user; 806 807 __local_r4k_flush_icache_range(start, end, type, user); 808 } 809 810 static void __r4k_flush_icache_range(unsigned long start, unsigned long end, 811 bool user) 812 { 813 struct flush_icache_range_args args; 814 unsigned long size, cache_size; 815 816 args.start = start; 817 args.end = end; 818 args.type = R4K_HIT | R4K_INDEX; 819 args.user = user; 820 821 /* 822 * Indexed cache ops require an SMP call. 823 * Consider if that can or should be avoided. 824 */ 825 preempt_disable(); 826 if (r4k_op_needs_ipi(R4K_INDEX) && !r4k_op_needs_ipi(R4K_HIT)) { 827 /* 828 * If address-based cache ops don't require an SMP call, then 829 * use them exclusively for small flushes. 830 */ 831 size = end - start; 832 cache_size = icache_size; 833 if (!cpu_has_ic_fills_f_dc) { 834 size *= 2; 835 cache_size += dcache_size; 836 } 837 if (size <= cache_size) 838 args.type &= ~R4K_INDEX; 839 } 840 r4k_on_each_cpu(args.type, local_r4k_flush_icache_range_ipi, &args); 841 preempt_enable(); 842 instruction_hazard(); 843 } 844 845 static void r4k_flush_icache_range(unsigned long start, unsigned long end) 846 { 847 return __r4k_flush_icache_range(start, end, false); 848 } 849 850 static void r4k_flush_icache_user_range(unsigned long start, unsigned long end) 851 { 852 return __r4k_flush_icache_range(start, end, true); 853 } 854 855 #ifdef CONFIG_DMA_NONCOHERENT 856 857 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) 858 { 859 /* Catch bad driver code */ 860 if (WARN_ON(size == 0)) 861 return; 862 863 preempt_disable(); 864 if (cpu_has_inclusive_pcaches) { 865 if (size >= scache_size) { 866 if (current_cpu_type() != CPU_LOONGSON3) 867 r4k_blast_scache(); 868 else 869 r4k_blast_scache_node(pa_to_nid(addr)); 870 } else { 871 blast_scache_range(addr, addr + size); 872 } 873 preempt_enable(); 874 __sync(); 875 return; 876 } 877 878 /* 879 * Either no secondary cache or the available caches don't have the 880 * subset property so we have to flush the primary caches 881 * explicitly. 882 * If we would need IPI to perform an INDEX-type operation, then 883 * we have to use the HIT-type alternative as IPI cannot be used 884 * here due to interrupts possibly being disabled. 885 */ 886 if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) { 887 r4k_blast_dcache(); 888 } else { 889 R4600_HIT_CACHEOP_WAR_IMPL; 890 blast_dcache_range(addr, addr + size); 891 } 892 preempt_enable(); 893 894 bc_wback_inv(addr, size); 895 __sync(); 896 } 897 898 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) 899 { 900 /* Catch bad driver code */ 901 if (WARN_ON(size == 0)) 902 return; 903 904 preempt_disable(); 905 if (cpu_has_inclusive_pcaches) { 906 if (size >= scache_size) { 907 if (current_cpu_type() != CPU_LOONGSON3) 908 r4k_blast_scache(); 909 else 910 r4k_blast_scache_node(pa_to_nid(addr)); 911 } else { 912 /* 913 * There is no clearly documented alignment requirement 914 * for the cache instruction on MIPS processors and 915 * some processors, among them the RM5200 and RM7000 916 * QED processors will throw an address error for cache 917 * hit ops with insufficient alignment. Solved by 918 * aligning the address to cache line size. 919 */ 920 blast_inv_scache_range(addr, addr + size); 921 } 922 preempt_enable(); 923 __sync(); 924 return; 925 } 926 927 if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) { 928 r4k_blast_dcache(); 929 } else { 930 R4600_HIT_CACHEOP_WAR_IMPL; 931 blast_inv_dcache_range(addr, addr + size); 932 } 933 preempt_enable(); 934 935 bc_inv(addr, size); 936 __sync(); 937 } 938 #endif /* CONFIG_DMA_NONCOHERENT */ 939 940 static void r4k_flush_icache_all(void) 941 { 942 if (cpu_has_vtag_icache) 943 r4k_blast_icache(); 944 } 945 946 struct flush_kernel_vmap_range_args { 947 unsigned long vaddr; 948 int size; 949 }; 950 951 static inline void local_r4k_flush_kernel_vmap_range_index(void *args) 952 { 953 /* 954 * Aliases only affect the primary caches so don't bother with 955 * S-caches or T-caches. 956 */ 957 r4k_blast_dcache(); 958 } 959 960 static inline void local_r4k_flush_kernel_vmap_range(void *args) 961 { 962 struct flush_kernel_vmap_range_args *vmra = args; 963 unsigned long vaddr = vmra->vaddr; 964 int size = vmra->size; 965 966 /* 967 * Aliases only affect the primary caches so don't bother with 968 * S-caches or T-caches. 969 */ 970 R4600_HIT_CACHEOP_WAR_IMPL; 971 blast_dcache_range(vaddr, vaddr + size); 972 } 973 974 static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size) 975 { 976 struct flush_kernel_vmap_range_args args; 977 978 args.vaddr = (unsigned long) vaddr; 979 args.size = size; 980 981 if (size >= dcache_size) 982 r4k_on_each_cpu(R4K_INDEX, 983 local_r4k_flush_kernel_vmap_range_index, NULL); 984 else 985 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_kernel_vmap_range, 986 &args); 987 } 988 989 static inline void rm7k_erratum31(void) 990 { 991 const unsigned long ic_lsize = 32; 992 unsigned long addr; 993 994 /* RM7000 erratum #31. The icache is screwed at startup. */ 995 write_c0_taglo(0); 996 write_c0_taghi(0); 997 998 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) { 999 __asm__ __volatile__ ( 1000 ".set push\n\t" 1001 ".set noreorder\n\t" 1002 ".set mips3\n\t" 1003 "cache\t%1, 0(%0)\n\t" 1004 "cache\t%1, 0x1000(%0)\n\t" 1005 "cache\t%1, 0x2000(%0)\n\t" 1006 "cache\t%1, 0x3000(%0)\n\t" 1007 "cache\t%2, 0(%0)\n\t" 1008 "cache\t%2, 0x1000(%0)\n\t" 1009 "cache\t%2, 0x2000(%0)\n\t" 1010 "cache\t%2, 0x3000(%0)\n\t" 1011 "cache\t%1, 0(%0)\n\t" 1012 "cache\t%1, 0x1000(%0)\n\t" 1013 "cache\t%1, 0x2000(%0)\n\t" 1014 "cache\t%1, 0x3000(%0)\n\t" 1015 ".set pop\n" 1016 : 1017 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill)); 1018 } 1019 } 1020 1021 static inline int alias_74k_erratum(struct cpuinfo_mips *c) 1022 { 1023 unsigned int imp = c->processor_id & PRID_IMP_MASK; 1024 unsigned int rev = c->processor_id & PRID_REV_MASK; 1025 int present = 0; 1026 1027 /* 1028 * Early versions of the 74K do not update the cache tags on a 1029 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG 1030 * aliases. In this case it is better to treat the cache as always 1031 * having aliases. Also disable the synonym tag update feature 1032 * where available. In this case no opportunistic tag update will 1033 * happen where a load causes a virtual address miss but a physical 1034 * address hit during a D-cache look-up. 1035 */ 1036 switch (imp) { 1037 case PRID_IMP_74K: 1038 if (rev <= PRID_REV_ENCODE_332(2, 4, 0)) 1039 present = 1; 1040 if (rev == PRID_REV_ENCODE_332(2, 4, 0)) 1041 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); 1042 break; 1043 case PRID_IMP_1074K: 1044 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) { 1045 present = 1; 1046 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); 1047 } 1048 break; 1049 default: 1050 BUG(); 1051 } 1052 1053 return present; 1054 } 1055 1056 static void b5k_instruction_hazard(void) 1057 { 1058 __sync(); 1059 __sync(); 1060 __asm__ __volatile__( 1061 " nop; nop; nop; nop; nop; nop; nop; nop\n" 1062 " nop; nop; nop; nop; nop; nop; nop; nop\n" 1063 " nop; nop; nop; nop; nop; nop; nop; nop\n" 1064 " nop; nop; nop; nop; nop; nop; nop; nop\n" 1065 : : : "memory"); 1066 } 1067 1068 static char *way_string[] = { NULL, "direct mapped", "2-way", 1069 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way", 1070 "9-way", "10-way", "11-way", "12-way", 1071 "13-way", "14-way", "15-way", "16-way", 1072 }; 1073 1074 static void probe_pcache(void) 1075 { 1076 struct cpuinfo_mips *c = ¤t_cpu_data; 1077 unsigned int config = read_c0_config(); 1078 unsigned int prid = read_c0_prid(); 1079 int has_74k_erratum = 0; 1080 unsigned long config1; 1081 unsigned int lsize; 1082 1083 switch (current_cpu_type()) { 1084 case CPU_R4600: /* QED style two way caches? */ 1085 case CPU_R4700: 1086 case CPU_R5000: 1087 case CPU_NEVADA: 1088 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1089 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1090 c->icache.ways = 2; 1091 c->icache.waybit = __ffs(icache_size/2); 1092 1093 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1094 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1095 c->dcache.ways = 2; 1096 c->dcache.waybit= __ffs(dcache_size/2); 1097 1098 c->options |= MIPS_CPU_CACHE_CDEX_P; 1099 break; 1100 1101 case CPU_R5500: 1102 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1103 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1104 c->icache.ways = 2; 1105 c->icache.waybit= 0; 1106 1107 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1108 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1109 c->dcache.ways = 2; 1110 c->dcache.waybit = 0; 1111 1112 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; 1113 break; 1114 1115 case CPU_TX49XX: 1116 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1117 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1118 c->icache.ways = 4; 1119 c->icache.waybit= 0; 1120 1121 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1122 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1123 c->dcache.ways = 4; 1124 c->dcache.waybit = 0; 1125 1126 c->options |= MIPS_CPU_CACHE_CDEX_P; 1127 c->options |= MIPS_CPU_PREFETCH; 1128 break; 1129 1130 case CPU_R4000PC: 1131 case CPU_R4000SC: 1132 case CPU_R4000MC: 1133 case CPU_R4400PC: 1134 case CPU_R4400SC: 1135 case CPU_R4400MC: 1136 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1137 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1138 c->icache.ways = 1; 1139 c->icache.waybit = 0; /* doesn't matter */ 1140 1141 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1142 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1143 c->dcache.ways = 1; 1144 c->dcache.waybit = 0; /* does not matter */ 1145 1146 c->options |= MIPS_CPU_CACHE_CDEX_P; 1147 break; 1148 1149 case CPU_R10000: 1150 case CPU_R12000: 1151 case CPU_R14000: 1152 case CPU_R16000: 1153 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); 1154 c->icache.linesz = 64; 1155 c->icache.ways = 2; 1156 c->icache.waybit = 0; 1157 1158 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26)); 1159 c->dcache.linesz = 32; 1160 c->dcache.ways = 2; 1161 c->dcache.waybit = 0; 1162 1163 c->options |= MIPS_CPU_PREFETCH; 1164 break; 1165 1166 case CPU_VR4133: 1167 write_c0_config(config & ~VR41_CONF_P4K); 1168 /* fall through */ 1169 case CPU_VR4131: 1170 /* Workaround for cache instruction bug of VR4131 */ 1171 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || 1172 c->processor_id == 0x0c82U) { 1173 config |= 0x00400000U; 1174 if (c->processor_id == 0x0c80U) 1175 config |= VR41_CONF_BP; 1176 write_c0_config(config); 1177 } else 1178 c->options |= MIPS_CPU_CACHE_CDEX_P; 1179 1180 icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); 1181 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1182 c->icache.ways = 2; 1183 c->icache.waybit = __ffs(icache_size/2); 1184 1185 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); 1186 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1187 c->dcache.ways = 2; 1188 c->dcache.waybit = __ffs(dcache_size/2); 1189 break; 1190 1191 case CPU_VR41XX: 1192 case CPU_VR4111: 1193 case CPU_VR4121: 1194 case CPU_VR4122: 1195 case CPU_VR4181: 1196 case CPU_VR4181A: 1197 icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); 1198 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1199 c->icache.ways = 1; 1200 c->icache.waybit = 0; /* doesn't matter */ 1201 1202 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); 1203 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1204 c->dcache.ways = 1; 1205 c->dcache.waybit = 0; /* does not matter */ 1206 1207 c->options |= MIPS_CPU_CACHE_CDEX_P; 1208 break; 1209 1210 case CPU_RM7000: 1211 rm7k_erratum31(); 1212 1213 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1214 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1215 c->icache.ways = 4; 1216 c->icache.waybit = __ffs(icache_size / c->icache.ways); 1217 1218 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1219 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1220 c->dcache.ways = 4; 1221 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); 1222 1223 c->options |= MIPS_CPU_CACHE_CDEX_P; 1224 c->options |= MIPS_CPU_PREFETCH; 1225 break; 1226 1227 case CPU_LOONGSON2: 1228 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1229 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1230 if (prid & 0x3) 1231 c->icache.ways = 4; 1232 else 1233 c->icache.ways = 2; 1234 c->icache.waybit = 0; 1235 1236 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1237 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1238 if (prid & 0x3) 1239 c->dcache.ways = 4; 1240 else 1241 c->dcache.ways = 2; 1242 c->dcache.waybit = 0; 1243 break; 1244 1245 case CPU_LOONGSON3: 1246 config1 = read_c0_config1(); 1247 lsize = (config1 >> 19) & 7; 1248 if (lsize) 1249 c->icache.linesz = 2 << lsize; 1250 else 1251 c->icache.linesz = 0; 1252 c->icache.sets = 64 << ((config1 >> 22) & 7); 1253 c->icache.ways = 1 + ((config1 >> 16) & 7); 1254 icache_size = c->icache.sets * 1255 c->icache.ways * 1256 c->icache.linesz; 1257 c->icache.waybit = 0; 1258 1259 lsize = (config1 >> 10) & 7; 1260 if (lsize) 1261 c->dcache.linesz = 2 << lsize; 1262 else 1263 c->dcache.linesz = 0; 1264 c->dcache.sets = 64 << ((config1 >> 13) & 7); 1265 c->dcache.ways = 1 + ((config1 >> 7) & 7); 1266 dcache_size = c->dcache.sets * 1267 c->dcache.ways * 1268 c->dcache.linesz; 1269 c->dcache.waybit = 0; 1270 if ((prid & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2_0) 1271 c->options |= MIPS_CPU_PREFETCH; 1272 break; 1273 1274 case CPU_CAVIUM_OCTEON3: 1275 /* For now lie about the number of ways. */ 1276 c->icache.linesz = 128; 1277 c->icache.sets = 16; 1278 c->icache.ways = 8; 1279 c->icache.flags |= MIPS_CACHE_VTAG; 1280 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; 1281 1282 c->dcache.linesz = 128; 1283 c->dcache.ways = 8; 1284 c->dcache.sets = 8; 1285 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; 1286 c->options |= MIPS_CPU_PREFETCH; 1287 break; 1288 1289 default: 1290 if (!(config & MIPS_CONF_M)) 1291 panic("Don't know how to probe P-caches on this cpu."); 1292 1293 /* 1294 * So we seem to be a MIPS32 or MIPS64 CPU 1295 * So let's probe the I-cache ... 1296 */ 1297 config1 = read_c0_config1(); 1298 1299 lsize = (config1 >> 19) & 7; 1300 1301 /* IL == 7 is reserved */ 1302 if (lsize == 7) 1303 panic("Invalid icache line size"); 1304 1305 c->icache.linesz = lsize ? 2 << lsize : 0; 1306 1307 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); 1308 c->icache.ways = 1 + ((config1 >> 16) & 7); 1309 1310 icache_size = c->icache.sets * 1311 c->icache.ways * 1312 c->icache.linesz; 1313 c->icache.waybit = __ffs(icache_size/c->icache.ways); 1314 1315 if (config & MIPS_CONF_VI) 1316 c->icache.flags |= MIPS_CACHE_VTAG; 1317 1318 /* 1319 * Now probe the MIPS32 / MIPS64 data cache. 1320 */ 1321 c->dcache.flags = 0; 1322 1323 lsize = (config1 >> 10) & 7; 1324 1325 /* DL == 7 is reserved */ 1326 if (lsize == 7) 1327 panic("Invalid dcache line size"); 1328 1329 c->dcache.linesz = lsize ? 2 << lsize : 0; 1330 1331 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); 1332 c->dcache.ways = 1 + ((config1 >> 7) & 7); 1333 1334 dcache_size = c->dcache.sets * 1335 c->dcache.ways * 1336 c->dcache.linesz; 1337 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways); 1338 1339 c->options |= MIPS_CPU_PREFETCH; 1340 break; 1341 } 1342 1343 /* 1344 * Processor configuration sanity check for the R4000SC erratum 1345 * #5. With page sizes larger than 32kB there is no possibility 1346 * to get a VCE exception anymore so we don't care about this 1347 * misconfiguration. The case is rather theoretical anyway; 1348 * presumably no vendor is shipping his hardware in the "bad" 1349 * configuration. 1350 */ 1351 if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 && 1352 (prid & PRID_REV_MASK) < PRID_REV_R4400 && 1353 !(config & CONF_SC) && c->icache.linesz != 16 && 1354 PAGE_SIZE <= 0x8000) 1355 panic("Improper R4000SC processor configuration detected"); 1356 1357 /* compute a couple of other cache variables */ 1358 c->icache.waysize = icache_size / c->icache.ways; 1359 c->dcache.waysize = dcache_size / c->dcache.ways; 1360 1361 c->icache.sets = c->icache.linesz ? 1362 icache_size / (c->icache.linesz * c->icache.ways) : 0; 1363 c->dcache.sets = c->dcache.linesz ? 1364 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; 1365 1366 /* 1367 * R1x000 P-caches are odd in a positive way. They're 32kB 2-way 1368 * virtually indexed so normally would suffer from aliases. So 1369 * normally they'd suffer from aliases but magic in the hardware deals 1370 * with that for us so we don't need to take care ourselves. 1371 */ 1372 switch (current_cpu_type()) { 1373 case CPU_20KC: 1374 case CPU_25KF: 1375 case CPU_I6400: 1376 case CPU_I6500: 1377 case CPU_SB1: 1378 case CPU_SB1A: 1379 case CPU_XLR: 1380 c->dcache.flags |= MIPS_CACHE_PINDEX; 1381 break; 1382 1383 case CPU_R10000: 1384 case CPU_R12000: 1385 case CPU_R14000: 1386 case CPU_R16000: 1387 break; 1388 1389 case CPU_74K: 1390 case CPU_1074K: 1391 has_74k_erratum = alias_74k_erratum(c); 1392 /* Fall through. */ 1393 case CPU_M14KC: 1394 case CPU_M14KEC: 1395 case CPU_24K: 1396 case CPU_34K: 1397 case CPU_1004K: 1398 case CPU_INTERAPTIV: 1399 case CPU_P5600: 1400 case CPU_PROAPTIV: 1401 case CPU_M5150: 1402 case CPU_QEMU_GENERIC: 1403 case CPU_P6600: 1404 case CPU_M6250: 1405 if (!(read_c0_config7() & MIPS_CONF7_IAR) && 1406 (c->icache.waysize > PAGE_SIZE)) 1407 c->icache.flags |= MIPS_CACHE_ALIASES; 1408 if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) { 1409 /* 1410 * Effectively physically indexed dcache, 1411 * thus no virtual aliases. 1412 */ 1413 c->dcache.flags |= MIPS_CACHE_PINDEX; 1414 break; 1415 } 1416 /* fall through */ 1417 default: 1418 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE) 1419 c->dcache.flags |= MIPS_CACHE_ALIASES; 1420 } 1421 1422 /* Physically indexed caches don't suffer from virtual aliasing */ 1423 if (c->dcache.flags & MIPS_CACHE_PINDEX) 1424 c->dcache.flags &= ~MIPS_CACHE_ALIASES; 1425 1426 /* 1427 * In systems with CM the icache fills from L2 or closer caches, and 1428 * thus sees remote stores without needing to write them back any 1429 * further than that. 1430 */ 1431 if (mips_cm_present()) 1432 c->icache.flags |= MIPS_IC_SNOOPS_REMOTE; 1433 1434 switch (current_cpu_type()) { 1435 case CPU_20KC: 1436 /* 1437 * Some older 20Kc chips doesn't have the 'VI' bit in 1438 * the config register. 1439 */ 1440 c->icache.flags |= MIPS_CACHE_VTAG; 1441 break; 1442 1443 case CPU_ALCHEMY: 1444 case CPU_I6400: 1445 case CPU_I6500: 1446 c->icache.flags |= MIPS_CACHE_IC_F_DC; 1447 break; 1448 1449 case CPU_BMIPS5000: 1450 c->icache.flags |= MIPS_CACHE_IC_F_DC; 1451 /* Cache aliases are handled in hardware; allow HIGHMEM */ 1452 c->dcache.flags &= ~MIPS_CACHE_ALIASES; 1453 break; 1454 1455 case CPU_LOONGSON2: 1456 /* 1457 * LOONGSON2 has 4 way icache, but when using indexed cache op, 1458 * one op will act on all 4 ways 1459 */ 1460 c->icache.ways = 1; 1461 } 1462 1463 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", 1464 icache_size >> 10, 1465 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", 1466 way_string[c->icache.ways], c->icache.linesz); 1467 1468 printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", 1469 dcache_size >> 10, way_string[c->dcache.ways], 1470 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", 1471 (c->dcache.flags & MIPS_CACHE_ALIASES) ? 1472 "cache aliases" : "no aliases", 1473 c->dcache.linesz); 1474 } 1475 1476 static void probe_vcache(void) 1477 { 1478 struct cpuinfo_mips *c = ¤t_cpu_data; 1479 unsigned int config2, lsize; 1480 1481 if (current_cpu_type() != CPU_LOONGSON3) 1482 return; 1483 1484 config2 = read_c0_config2(); 1485 if ((lsize = ((config2 >> 20) & 15))) 1486 c->vcache.linesz = 2 << lsize; 1487 else 1488 c->vcache.linesz = lsize; 1489 1490 c->vcache.sets = 64 << ((config2 >> 24) & 15); 1491 c->vcache.ways = 1 + ((config2 >> 16) & 15); 1492 1493 vcache_size = c->vcache.sets * c->vcache.ways * c->vcache.linesz; 1494 1495 c->vcache.waybit = 0; 1496 c->vcache.waysize = vcache_size / c->vcache.ways; 1497 1498 pr_info("Unified victim cache %ldkB %s, linesize %d bytes.\n", 1499 vcache_size >> 10, way_string[c->vcache.ways], c->vcache.linesz); 1500 } 1501 1502 /* 1503 * If you even _breathe_ on this function, look at the gcc output and make sure 1504 * it does not pop things on and off the stack for the cache sizing loop that 1505 * executes in KSEG1 space or else you will crash and burn badly. You have 1506 * been warned. 1507 */ 1508 static int probe_scache(void) 1509 { 1510 unsigned long flags, addr, begin, end, pow2; 1511 unsigned int config = read_c0_config(); 1512 struct cpuinfo_mips *c = ¤t_cpu_data; 1513 1514 if (config & CONF_SC) 1515 return 0; 1516 1517 begin = (unsigned long) &_stext; 1518 begin &= ~((4 * 1024 * 1024) - 1); 1519 end = begin + (4 * 1024 * 1024); 1520 1521 /* 1522 * This is such a bitch, you'd think they would make it easy to do 1523 * this. Away you daemons of stupidity! 1524 */ 1525 local_irq_save(flags); 1526 1527 /* Fill each size-multiple cache line with a valid tag. */ 1528 pow2 = (64 * 1024); 1529 for (addr = begin; addr < end; addr = (begin + pow2)) { 1530 unsigned long *p = (unsigned long *) addr; 1531 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ 1532 pow2 <<= 1; 1533 } 1534 1535 /* Load first line with zero (therefore invalid) tag. */ 1536 write_c0_taglo(0); 1537 write_c0_taghi(0); 1538 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ 1539 cache_op(Index_Store_Tag_I, begin); 1540 cache_op(Index_Store_Tag_D, begin); 1541 cache_op(Index_Store_Tag_SD, begin); 1542 1543 /* Now search for the wrap around point. */ 1544 pow2 = (128 * 1024); 1545 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) { 1546 cache_op(Index_Load_Tag_SD, addr); 1547 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ 1548 if (!read_c0_taglo()) 1549 break; 1550 pow2 <<= 1; 1551 } 1552 local_irq_restore(flags); 1553 addr -= begin; 1554 1555 scache_size = addr; 1556 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22); 1557 c->scache.ways = 1; 1558 c->scache.waybit = 0; /* does not matter */ 1559 1560 return 1; 1561 } 1562 1563 static void __init loongson2_sc_init(void) 1564 { 1565 struct cpuinfo_mips *c = ¤t_cpu_data; 1566 1567 scache_size = 512*1024; 1568 c->scache.linesz = 32; 1569 c->scache.ways = 4; 1570 c->scache.waybit = 0; 1571 c->scache.waysize = scache_size / (c->scache.ways); 1572 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); 1573 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", 1574 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); 1575 1576 c->options |= MIPS_CPU_INCLUSIVE_CACHES; 1577 } 1578 1579 static void __init loongson3_sc_init(void) 1580 { 1581 struct cpuinfo_mips *c = ¤t_cpu_data; 1582 unsigned int config2, lsize; 1583 1584 config2 = read_c0_config2(); 1585 lsize = (config2 >> 4) & 15; 1586 if (lsize) 1587 c->scache.linesz = 2 << lsize; 1588 else 1589 c->scache.linesz = 0; 1590 c->scache.sets = 64 << ((config2 >> 8) & 15); 1591 c->scache.ways = 1 + (config2 & 15); 1592 1593 scache_size = c->scache.sets * 1594 c->scache.ways * 1595 c->scache.linesz; 1596 /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */ 1597 scache_size *= 4; 1598 c->scache.waybit = 0; 1599 c->scache.waysize = scache_size / c->scache.ways; 1600 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", 1601 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); 1602 if (scache_size) 1603 c->options |= MIPS_CPU_INCLUSIVE_CACHES; 1604 return; 1605 } 1606 1607 extern int r5k_sc_init(void); 1608 extern int rm7k_sc_init(void); 1609 extern int mips_sc_init(void); 1610 1611 static void setup_scache(void) 1612 { 1613 struct cpuinfo_mips *c = ¤t_cpu_data; 1614 unsigned int config = read_c0_config(); 1615 int sc_present = 0; 1616 1617 /* 1618 * Do the probing thing on R4000SC and R4400SC processors. Other 1619 * processors don't have a S-cache that would be relevant to the 1620 * Linux memory management. 1621 */ 1622 switch (current_cpu_type()) { 1623 case CPU_R4000SC: 1624 case CPU_R4000MC: 1625 case CPU_R4400SC: 1626 case CPU_R4400MC: 1627 sc_present = run_uncached(probe_scache); 1628 if (sc_present) 1629 c->options |= MIPS_CPU_CACHE_CDEX_S; 1630 break; 1631 1632 case CPU_R10000: 1633 case CPU_R12000: 1634 case CPU_R14000: 1635 case CPU_R16000: 1636 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); 1637 c->scache.linesz = 64 << ((config >> 13) & 1); 1638 c->scache.ways = 2; 1639 c->scache.waybit= 0; 1640 sc_present = 1; 1641 break; 1642 1643 case CPU_R5000: 1644 case CPU_NEVADA: 1645 #ifdef CONFIG_R5000_CPU_SCACHE 1646 r5k_sc_init(); 1647 #endif 1648 return; 1649 1650 case CPU_RM7000: 1651 #ifdef CONFIG_RM7000_CPU_SCACHE 1652 rm7k_sc_init(); 1653 #endif 1654 return; 1655 1656 case CPU_LOONGSON2: 1657 loongson2_sc_init(); 1658 return; 1659 1660 case CPU_LOONGSON3: 1661 loongson3_sc_init(); 1662 return; 1663 1664 case CPU_CAVIUM_OCTEON3: 1665 case CPU_XLP: 1666 /* don't need to worry about L2, fully coherent */ 1667 return; 1668 1669 default: 1670 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | 1671 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 | 1672 MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) { 1673 #ifdef CONFIG_MIPS_CPU_SCACHE 1674 if (mips_sc_init ()) { 1675 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; 1676 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", 1677 scache_size >> 10, 1678 way_string[c->scache.ways], c->scache.linesz); 1679 } 1680 #else 1681 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) 1682 panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); 1683 #endif 1684 return; 1685 } 1686 sc_present = 0; 1687 } 1688 1689 if (!sc_present) 1690 return; 1691 1692 /* compute a couple of other cache variables */ 1693 c->scache.waysize = scache_size / c->scache.ways; 1694 1695 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); 1696 1697 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", 1698 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); 1699 1700 c->options |= MIPS_CPU_INCLUSIVE_CACHES; 1701 } 1702 1703 void au1x00_fixup_config_od(void) 1704 { 1705 /* 1706 * c0_config.od (bit 19) was write only (and read as 0) 1707 * on the early revisions of Alchemy SOCs. It disables the bus 1708 * transaction overlapping and needs to be set to fix various errata. 1709 */ 1710 switch (read_c0_prid()) { 1711 case 0x00030100: /* Au1000 DA */ 1712 case 0x00030201: /* Au1000 HA */ 1713 case 0x00030202: /* Au1000 HB */ 1714 case 0x01030200: /* Au1500 AB */ 1715 /* 1716 * Au1100 errata actually keeps silence about this bit, so we set it 1717 * just in case for those revisions that require it to be set according 1718 * to the (now gone) cpu table. 1719 */ 1720 case 0x02030200: /* Au1100 AB */ 1721 case 0x02030201: /* Au1100 BA */ 1722 case 0x02030202: /* Au1100 BC */ 1723 set_c0_config(1 << 19); 1724 break; 1725 } 1726 } 1727 1728 /* CP0 hazard avoidance. */ 1729 #define NXP_BARRIER() \ 1730 __asm__ __volatile__( \ 1731 ".set noreorder\n\t" \ 1732 "nop; nop; nop; nop; nop; nop;\n\t" \ 1733 ".set reorder\n\t") 1734 1735 static void nxp_pr4450_fixup_config(void) 1736 { 1737 unsigned long config0; 1738 1739 config0 = read_c0_config(); 1740 1741 /* clear all three cache coherency fields */ 1742 config0 &= ~(0x7 | (7 << 25) | (7 << 28)); 1743 config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) | 1744 ((_page_cachable_default >> _CACHE_SHIFT) << 25) | 1745 ((_page_cachable_default >> _CACHE_SHIFT) << 28)); 1746 write_c0_config(config0); 1747 NXP_BARRIER(); 1748 } 1749 1750 static int cca = -1; 1751 1752 static int __init cca_setup(char *str) 1753 { 1754 get_option(&str, &cca); 1755 1756 return 0; 1757 } 1758 1759 early_param("cca", cca_setup); 1760 1761 static void coherency_setup(void) 1762 { 1763 if (cca < 0 || cca > 7) 1764 cca = read_c0_config() & CONF_CM_CMASK; 1765 _page_cachable_default = cca << _CACHE_SHIFT; 1766 1767 pr_debug("Using cache attribute %d\n", cca); 1768 change_c0_config(CONF_CM_CMASK, cca); 1769 1770 /* 1771 * c0_status.cu=0 specifies that updates by the sc instruction use 1772 * the coherency mode specified by the TLB; 1 means cachable 1773 * coherent update on write will be used. Not all processors have 1774 * this bit and; some wire it to zero, others like Toshiba had the 1775 * silly idea of putting something else there ... 1776 */ 1777 switch (current_cpu_type()) { 1778 case CPU_R4000PC: 1779 case CPU_R4000SC: 1780 case CPU_R4000MC: 1781 case CPU_R4400PC: 1782 case CPU_R4400SC: 1783 case CPU_R4400MC: 1784 clear_c0_config(CONF_CU); 1785 break; 1786 /* 1787 * We need to catch the early Alchemy SOCs with 1788 * the write-only co_config.od bit and set it back to one on: 1789 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB 1790 */ 1791 case CPU_ALCHEMY: 1792 au1x00_fixup_config_od(); 1793 break; 1794 1795 case PRID_IMP_PR4450: 1796 nxp_pr4450_fixup_config(); 1797 break; 1798 } 1799 } 1800 1801 static void r4k_cache_error_setup(void) 1802 { 1803 extern char __weak except_vec2_generic; 1804 extern char __weak except_vec2_sb1; 1805 1806 switch (current_cpu_type()) { 1807 case CPU_SB1: 1808 case CPU_SB1A: 1809 set_uncached_handler(0x100, &except_vec2_sb1, 0x80); 1810 break; 1811 1812 default: 1813 set_uncached_handler(0x100, &except_vec2_generic, 0x80); 1814 break; 1815 } 1816 } 1817 1818 void r4k_cache_init(void) 1819 { 1820 extern void build_clear_page(void); 1821 extern void build_copy_page(void); 1822 struct cpuinfo_mips *c = ¤t_cpu_data; 1823 1824 probe_pcache(); 1825 probe_vcache(); 1826 setup_scache(); 1827 1828 r4k_blast_dcache_page_setup(); 1829 r4k_blast_dcache_page_indexed_setup(); 1830 r4k_blast_dcache_setup(); 1831 r4k_blast_icache_page_setup(); 1832 r4k_blast_icache_page_indexed_setup(); 1833 r4k_blast_icache_setup(); 1834 r4k_blast_scache_page_setup(); 1835 r4k_blast_scache_page_indexed_setup(); 1836 r4k_blast_scache_setup(); 1837 r4k_blast_scache_node_setup(); 1838 #ifdef CONFIG_EVA 1839 r4k_blast_dcache_user_page_setup(); 1840 r4k_blast_icache_user_page_setup(); 1841 #endif 1842 1843 /* 1844 * Some MIPS32 and MIPS64 processors have physically indexed caches. 1845 * This code supports virtually indexed processors and will be 1846 * unnecessarily inefficient on physically indexed processors. 1847 */ 1848 if (c->dcache.linesz && cpu_has_dc_aliases) 1849 shm_align_mask = max_t( unsigned long, 1850 c->dcache.sets * c->dcache.linesz - 1, 1851 PAGE_SIZE - 1); 1852 else 1853 shm_align_mask = PAGE_SIZE-1; 1854 1855 __flush_cache_vmap = r4k__flush_cache_vmap; 1856 __flush_cache_vunmap = r4k__flush_cache_vunmap; 1857 1858 flush_cache_all = cache_noop; 1859 __flush_cache_all = r4k___flush_cache_all; 1860 flush_cache_mm = r4k_flush_cache_mm; 1861 flush_cache_page = r4k_flush_cache_page; 1862 flush_cache_range = r4k_flush_cache_range; 1863 1864 __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range; 1865 1866 flush_icache_all = r4k_flush_icache_all; 1867 local_flush_data_cache_page = local_r4k_flush_data_cache_page; 1868 flush_data_cache_page = r4k_flush_data_cache_page; 1869 flush_icache_range = r4k_flush_icache_range; 1870 local_flush_icache_range = local_r4k_flush_icache_range; 1871 __flush_icache_user_range = r4k_flush_icache_user_range; 1872 __local_flush_icache_user_range = local_r4k_flush_icache_user_range; 1873 1874 #ifdef CONFIG_DMA_NONCOHERENT 1875 #ifdef CONFIG_DMA_MAYBE_COHERENT 1876 if (coherentio == IO_COHERENCE_ENABLED || 1877 (coherentio == IO_COHERENCE_DEFAULT && hw_coherentio)) { 1878 _dma_cache_wback_inv = (void *)cache_noop; 1879 _dma_cache_wback = (void *)cache_noop; 1880 _dma_cache_inv = (void *)cache_noop; 1881 } else 1882 #endif /* CONFIG_DMA_MAYBE_COHERENT */ 1883 { 1884 _dma_cache_wback_inv = r4k_dma_cache_wback_inv; 1885 _dma_cache_wback = r4k_dma_cache_wback_inv; 1886 _dma_cache_inv = r4k_dma_cache_inv; 1887 } 1888 #endif /* CONFIG_DMA_NONCOHERENT */ 1889 1890 build_clear_page(); 1891 build_copy_page(); 1892 1893 /* 1894 * We want to run CMP kernels on core with and without coherent 1895 * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether 1896 * or not to flush caches. 1897 */ 1898 local_r4k___flush_cache_all(NULL); 1899 1900 coherency_setup(); 1901 board_cache_error_setup = r4k_cache_error_setup; 1902 1903 /* 1904 * Per-CPU overrides 1905 */ 1906 switch (current_cpu_type()) { 1907 case CPU_BMIPS4350: 1908 case CPU_BMIPS4380: 1909 /* No IPI is needed because all CPUs share the same D$ */ 1910 flush_data_cache_page = r4k_blast_dcache_page; 1911 break; 1912 case CPU_BMIPS5000: 1913 /* We lose our superpowers if L2 is disabled */ 1914 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT) 1915 break; 1916 1917 /* I$ fills from D$ just by emptying the write buffers */ 1918 flush_cache_page = (void *)b5k_instruction_hazard; 1919 flush_cache_range = (void *)b5k_instruction_hazard; 1920 local_flush_data_cache_page = (void *)b5k_instruction_hazard; 1921 flush_data_cache_page = (void *)b5k_instruction_hazard; 1922 flush_icache_range = (void *)b5k_instruction_hazard; 1923 local_flush_icache_range = (void *)b5k_instruction_hazard; 1924 1925 1926 /* Optimization: an L2 flush implicitly flushes the L1 */ 1927 current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES; 1928 break; 1929 case CPU_LOONGSON3: 1930 /* Loongson-3 maintains cache coherency by hardware */ 1931 __flush_cache_all = cache_noop; 1932 __flush_cache_vmap = cache_noop; 1933 __flush_cache_vunmap = cache_noop; 1934 __flush_kernel_vmap_range = (void *)cache_noop; 1935 flush_cache_mm = (void *)cache_noop; 1936 flush_cache_page = (void *)cache_noop; 1937 flush_cache_range = (void *)cache_noop; 1938 flush_icache_all = (void *)cache_noop; 1939 flush_data_cache_page = (void *)cache_noop; 1940 local_flush_data_cache_page = (void *)cache_noop; 1941 break; 1942 } 1943 } 1944 1945 static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd, 1946 void *v) 1947 { 1948 switch (cmd) { 1949 case CPU_PM_ENTER_FAILED: 1950 case CPU_PM_EXIT: 1951 coherency_setup(); 1952 break; 1953 } 1954 1955 return NOTIFY_OK; 1956 } 1957 1958 static struct notifier_block r4k_cache_pm_notifier_block = { 1959 .notifier_call = r4k_cache_pm_notifier, 1960 }; 1961 1962 int __init r4k_cache_init_pm(void) 1963 { 1964 return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block); 1965 } 1966 arch_initcall(r4k_cache_init_pm); 1967