1*b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0
21da177e4SLinus Torvalds /*
31da177e4SLinus Torvalds * sc-rm7k.c: RM7000 cache management functions.
41da177e4SLinus Torvalds *
51da177e4SLinus Torvalds * Copyright (C) 1997, 2001, 2003, 2004 Ralf Baechle (ralf@linux-mips.org)
61da177e4SLinus Torvalds */
71da177e4SLinus Torvalds
81da177e4SLinus Torvalds #undef DEBUG
91da177e4SLinus Torvalds
101da177e4SLinus Torvalds #include <linux/kernel.h>
111da177e4SLinus Torvalds #include <linux/mm.h>
1237caa934SAtsushi Nemoto #include <linux/bitops.h>
131da177e4SLinus Torvalds
141da177e4SLinus Torvalds #include <asm/addrspace.h>
151da177e4SLinus Torvalds #include <asm/bcache.h>
161da177e4SLinus Torvalds #include <asm/cacheops.h>
171da177e4SLinus Torvalds #include <asm/mipsregs.h>
181da177e4SLinus Torvalds #include <asm/processor.h>
19745aef5dSRicardo Mendoza #include <asm/sections.h>
20ba5187dbSThiemo Seufer #include <asm/cacheflush.h> /* for run_uncached() */
211da177e4SLinus Torvalds
221da177e4SLinus Torvalds /* Primary cache parameters. */
231da177e4SLinus Torvalds #define sc_lsize 32
241da177e4SLinus Torvalds #define tc_pagesize (32*128)
251da177e4SLinus Torvalds
261da177e4SLinus Torvalds /* Secondary cache parameters. */
271da177e4SLinus Torvalds #define scache_size (256*1024) /* Fixed to 256KiB on RM7000 */
281da177e4SLinus Torvalds
29745aef5dSRicardo Mendoza /* Tertiary cache parameters */
30745aef5dSRicardo Mendoza #define tc_lsize 32
31745aef5dSRicardo Mendoza
321da177e4SLinus Torvalds extern unsigned long icache_way_size, dcache_way_size;
33543001f8SRicardo Mendoza static unsigned long tcache_size;
341da177e4SLinus Torvalds
351da177e4SLinus Torvalds #include <asm/r4kcache.h>
361da177e4SLinus Torvalds
37745aef5dSRicardo Mendoza static int rm7k_tcache_init;
381da177e4SLinus Torvalds
391da177e4SLinus Torvalds /*
401da177e4SLinus Torvalds * Writeback and invalidate the primary cache dcache before DMA.
411da177e4SLinus Torvalds * (XXX These need to be fixed ...)
421da177e4SLinus Torvalds */
rm7k_sc_wback_inv(unsigned long addr,unsigned long size)431da177e4SLinus Torvalds static void rm7k_sc_wback_inv(unsigned long addr, unsigned long size)
441da177e4SLinus Torvalds {
451da177e4SLinus Torvalds unsigned long end, a;
461da177e4SLinus Torvalds
471da177e4SLinus Torvalds pr_debug("rm7k_sc_wback_inv[%08lx,%08lx]", addr, size);
481da177e4SLinus Torvalds
491da177e4SLinus Torvalds /* Catch bad driver code */
501da177e4SLinus Torvalds BUG_ON(size == 0);
511da177e4SLinus Torvalds
5237caa934SAtsushi Nemoto blast_scache_range(addr, addr + size);
531da177e4SLinus Torvalds
54745aef5dSRicardo Mendoza if (!rm7k_tcache_init)
551da177e4SLinus Torvalds return;
561da177e4SLinus Torvalds
571da177e4SLinus Torvalds a = addr & ~(tc_pagesize - 1);
581da177e4SLinus Torvalds end = (addr + size - 1) & ~(tc_pagesize - 1);
591da177e4SLinus Torvalds while(1) {
601da177e4SLinus Torvalds invalidate_tcache_page(a); /* Page_Invalidate_T */
611da177e4SLinus Torvalds if (a == end)
621da177e4SLinus Torvalds break;
631da177e4SLinus Torvalds a += tc_pagesize;
641da177e4SLinus Torvalds }
651da177e4SLinus Torvalds }
661da177e4SLinus Torvalds
rm7k_sc_inv(unsigned long addr,unsigned long size)671da177e4SLinus Torvalds static void rm7k_sc_inv(unsigned long addr, unsigned long size)
681da177e4SLinus Torvalds {
691da177e4SLinus Torvalds unsigned long end, a;
701da177e4SLinus Torvalds
711da177e4SLinus Torvalds pr_debug("rm7k_sc_inv[%08lx,%08lx]", addr, size);
721da177e4SLinus Torvalds
731da177e4SLinus Torvalds /* Catch bad driver code */
741da177e4SLinus Torvalds BUG_ON(size == 0);
751da177e4SLinus Torvalds
7637caa934SAtsushi Nemoto blast_inv_scache_range(addr, addr + size);
771da177e4SLinus Torvalds
78745aef5dSRicardo Mendoza if (!rm7k_tcache_init)
791da177e4SLinus Torvalds return;
801da177e4SLinus Torvalds
811da177e4SLinus Torvalds a = addr & ~(tc_pagesize - 1);
821da177e4SLinus Torvalds end = (addr + size - 1) & ~(tc_pagesize - 1);
831da177e4SLinus Torvalds while(1) {
841da177e4SLinus Torvalds invalidate_tcache_page(a); /* Page_Invalidate_T */
851da177e4SLinus Torvalds if (a == end)
861da177e4SLinus Torvalds break;
871da177e4SLinus Torvalds a += tc_pagesize;
881da177e4SLinus Torvalds }
891da177e4SLinus Torvalds }
901da177e4SLinus Torvalds
blast_rm7k_tcache(void)91745aef5dSRicardo Mendoza static void blast_rm7k_tcache(void)
92745aef5dSRicardo Mendoza {
93745aef5dSRicardo Mendoza unsigned long start = CKSEG0ADDR(0);
94745aef5dSRicardo Mendoza unsigned long end = start + tcache_size;
95745aef5dSRicardo Mendoza
96745aef5dSRicardo Mendoza write_c0_taglo(0);
97745aef5dSRicardo Mendoza
98745aef5dSRicardo Mendoza while (start < end) {
99745aef5dSRicardo Mendoza cache_op(Page_Invalidate_T, start);
100745aef5dSRicardo Mendoza start += tc_pagesize;
101745aef5dSRicardo Mendoza }
102745aef5dSRicardo Mendoza }
103745aef5dSRicardo Mendoza
104745aef5dSRicardo Mendoza /*
105745aef5dSRicardo Mendoza * This function is executed in uncached address space.
106745aef5dSRicardo Mendoza */
__rm7k_tc_enable(void)107078a55fcSPaul Gortmaker static void __rm7k_tc_enable(void)
108745aef5dSRicardo Mendoza {
109745aef5dSRicardo Mendoza int i;
110745aef5dSRicardo Mendoza
111745aef5dSRicardo Mendoza set_c0_config(RM7K_CONF_TE);
112745aef5dSRicardo Mendoza
113745aef5dSRicardo Mendoza write_c0_taglo(0);
114745aef5dSRicardo Mendoza write_c0_taghi(0);
115745aef5dSRicardo Mendoza
116745aef5dSRicardo Mendoza for (i = 0; i < tcache_size; i += tc_lsize)
117745aef5dSRicardo Mendoza cache_op(Index_Store_Tag_T, CKSEG0ADDR(i));
118745aef5dSRicardo Mendoza }
119745aef5dSRicardo Mendoza
rm7k_tc_enable(void)120078a55fcSPaul Gortmaker static void rm7k_tc_enable(void)
121745aef5dSRicardo Mendoza {
122745aef5dSRicardo Mendoza if (read_c0_config() & RM7K_CONF_TE)
123745aef5dSRicardo Mendoza return;
124745aef5dSRicardo Mendoza
125745aef5dSRicardo Mendoza BUG_ON(tcache_size == 0);
126745aef5dSRicardo Mendoza
127745aef5dSRicardo Mendoza run_uncached(__rm7k_tc_enable);
128745aef5dSRicardo Mendoza }
129745aef5dSRicardo Mendoza
1301da177e4SLinus Torvalds /*
131ba5187dbSThiemo Seufer * This function is executed in uncached address space.
1321da177e4SLinus Torvalds */
__rm7k_sc_enable(void)133078a55fcSPaul Gortmaker static void __rm7k_sc_enable(void)
1341da177e4SLinus Torvalds {
1351da177e4SLinus Torvalds int i;
1361da177e4SLinus Torvalds
137c6ad7b7dSMaciej W. Rozycki set_c0_config(RM7K_CONF_SE);
1381da177e4SLinus Torvalds
1391da177e4SLinus Torvalds write_c0_taglo(0);
1401da177e4SLinus Torvalds write_c0_taghi(0);
1411da177e4SLinus Torvalds
14258a6d451SRicardo Mendoza for (i = 0; i < scache_size; i += sc_lsize)
14358a6d451SRicardo Mendoza cache_op(Index_Store_Tag_SD, CKSEG0ADDR(i));
1441da177e4SLinus Torvalds }
1451da177e4SLinus Torvalds
rm7k_sc_enable(void)146078a55fcSPaul Gortmaker static void rm7k_sc_enable(void)
1471da177e4SLinus Torvalds {
148c6ad7b7dSMaciej W. Rozycki if (read_c0_config() & RM7K_CONF_SE)
1491da177e4SLinus Torvalds return;
1501da177e4SLinus Torvalds
151745aef5dSRicardo Mendoza pr_info("Enabling secondary cache...\n");
152ba5187dbSThiemo Seufer run_uncached(__rm7k_sc_enable);
153745aef5dSRicardo Mendoza
154745aef5dSRicardo Mendoza if (rm7k_tcache_init)
155745aef5dSRicardo Mendoza rm7k_tc_enable();
156745aef5dSRicardo Mendoza }
157745aef5dSRicardo Mendoza
rm7k_tc_disable(void)158745aef5dSRicardo Mendoza static void rm7k_tc_disable(void)
159745aef5dSRicardo Mendoza {
160745aef5dSRicardo Mendoza unsigned long flags;
161745aef5dSRicardo Mendoza
162745aef5dSRicardo Mendoza local_irq_save(flags);
163745aef5dSRicardo Mendoza blast_rm7k_tcache();
164745aef5dSRicardo Mendoza clear_c0_config(RM7K_CONF_TE);
16558a7e1c1SDan Carpenter local_irq_restore(flags);
1661da177e4SLinus Torvalds }
1671da177e4SLinus Torvalds
rm7k_sc_disable(void)1681da177e4SLinus Torvalds static void rm7k_sc_disable(void)
1691da177e4SLinus Torvalds {
170c6ad7b7dSMaciej W. Rozycki clear_c0_config(RM7K_CONF_SE);
171745aef5dSRicardo Mendoza
172745aef5dSRicardo Mendoza if (rm7k_tcache_init)
173745aef5dSRicardo Mendoza rm7k_tc_disable();
1741da177e4SLinus Torvalds }
1751da177e4SLinus Torvalds
1761291417eSDmitri Vorobiev static struct bcache_ops rm7k_sc_ops = {
1771da177e4SLinus Torvalds .bc_enable = rm7k_sc_enable,
1781da177e4SLinus Torvalds .bc_disable = rm7k_sc_disable,
1791da177e4SLinus Torvalds .bc_wback_inv = rm7k_sc_wback_inv,
1801da177e4SLinus Torvalds .bc_inv = rm7k_sc_inv
1811da177e4SLinus Torvalds };
1821da177e4SLinus Torvalds
183745aef5dSRicardo Mendoza /*
184745aef5dSRicardo Mendoza * This is a probing function like the one found in c-r4k.c, we look for the
185745aef5dSRicardo Mendoza * wrap around point with different addresses.
186745aef5dSRicardo Mendoza */
__probe_tcache(void)187078a55fcSPaul Gortmaker static void __probe_tcache(void)
188745aef5dSRicardo Mendoza {
189745aef5dSRicardo Mendoza unsigned long flags, addr, begin, end, pow2;
190745aef5dSRicardo Mendoza
191745aef5dSRicardo Mendoza begin = (unsigned long) &_stext;
192745aef5dSRicardo Mendoza begin &= ~((8 * 1024 * 1024) - 1);
193745aef5dSRicardo Mendoza end = begin + (8 * 1024 * 1024);
194745aef5dSRicardo Mendoza
195745aef5dSRicardo Mendoza local_irq_save(flags);
196745aef5dSRicardo Mendoza
197745aef5dSRicardo Mendoza set_c0_config(RM7K_CONF_TE);
198745aef5dSRicardo Mendoza
199745aef5dSRicardo Mendoza /* Fill size-multiple lines with a valid tag */
200745aef5dSRicardo Mendoza pow2 = (256 * 1024);
201745aef5dSRicardo Mendoza for (addr = begin; addr <= end; addr = (begin + pow2)) {
202745aef5dSRicardo Mendoza unsigned long *p = (unsigned long *) addr;
203745aef5dSRicardo Mendoza __asm__ __volatile__("nop" : : "r" (*p));
204745aef5dSRicardo Mendoza pow2 <<= 1;
205745aef5dSRicardo Mendoza }
206745aef5dSRicardo Mendoza
207745aef5dSRicardo Mendoza /* Load first line with a 0 tag, to check after */
208745aef5dSRicardo Mendoza write_c0_taglo(0);
209745aef5dSRicardo Mendoza write_c0_taghi(0);
210745aef5dSRicardo Mendoza cache_op(Index_Store_Tag_T, begin);
211745aef5dSRicardo Mendoza
212745aef5dSRicardo Mendoza /* Look for the wrap-around */
213745aef5dSRicardo Mendoza pow2 = (512 * 1024);
214745aef5dSRicardo Mendoza for (addr = begin + (512 * 1024); addr <= end; addr = begin + pow2) {
215745aef5dSRicardo Mendoza cache_op(Index_Load_Tag_T, addr);
216745aef5dSRicardo Mendoza if (!read_c0_taglo())
217745aef5dSRicardo Mendoza break;
218745aef5dSRicardo Mendoza pow2 <<= 1;
219745aef5dSRicardo Mendoza }
220745aef5dSRicardo Mendoza
221745aef5dSRicardo Mendoza addr -= begin;
222745aef5dSRicardo Mendoza tcache_size = addr;
223745aef5dSRicardo Mendoza
224745aef5dSRicardo Mendoza clear_c0_config(RM7K_CONF_TE);
225745aef5dSRicardo Mendoza
226745aef5dSRicardo Mendoza local_irq_restore(flags);
227745aef5dSRicardo Mendoza }
228745aef5dSRicardo Mendoza
rm7k_sc_init(void)229078a55fcSPaul Gortmaker void rm7k_sc_init(void)
2301da177e4SLinus Torvalds {
23137caa934SAtsushi Nemoto struct cpuinfo_mips *c = ¤t_cpu_data;
2321da177e4SLinus Torvalds unsigned int config = read_c0_config();
2331da177e4SLinus Torvalds
234c6ad7b7dSMaciej W. Rozycki if ((config & RM7K_CONF_SC))
2351da177e4SLinus Torvalds return;
2361da177e4SLinus Torvalds
23737caa934SAtsushi Nemoto c->scache.linesz = sc_lsize;
23837caa934SAtsushi Nemoto c->scache.ways = 4;
2393c68da79SAtsushi Nemoto c->scache.waybit= __ffs(scache_size / c->scache.ways);
24037caa934SAtsushi Nemoto c->scache.waysize = scache_size / c->scache.ways;
24137caa934SAtsushi Nemoto c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
2421da177e4SLinus Torvalds printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n",
2431da177e4SLinus Torvalds (scache_size >> 10), sc_lsize);
2441da177e4SLinus Torvalds
245c6ad7b7dSMaciej W. Rozycki if (!(config & RM7K_CONF_SE))
2461da177e4SLinus Torvalds rm7k_sc_enable();
2471da177e4SLinus Torvalds
248745aef5dSRicardo Mendoza bcops = &rm7k_sc_ops;
249745aef5dSRicardo Mendoza
2501da177e4SLinus Torvalds /*
2511da177e4SLinus Torvalds * While we're at it let's deal with the tertiary cache.
2521da177e4SLinus Torvalds */
253745aef5dSRicardo Mendoza
254745aef5dSRicardo Mendoza rm7k_tcache_init = 0;
255745aef5dSRicardo Mendoza tcache_size = 0;
256745aef5dSRicardo Mendoza
257745aef5dSRicardo Mendoza if (config & RM7K_CONF_TC)
258745aef5dSRicardo Mendoza return;
2591da177e4SLinus Torvalds
2601da177e4SLinus Torvalds /*
261745aef5dSRicardo Mendoza * No efficient way to ask the hardware for the size of the tcache,
262745aef5dSRicardo Mendoza * so must probe for it.
2631da177e4SLinus Torvalds */
264745aef5dSRicardo Mendoza run_uncached(__probe_tcache);
265745aef5dSRicardo Mendoza rm7k_tc_enable();
266745aef5dSRicardo Mendoza rm7k_tcache_init = 1;
267745aef5dSRicardo Mendoza c->tcache.linesz = tc_lsize;
268745aef5dSRicardo Mendoza c->tcache.ways = 1;
269745aef5dSRicardo Mendoza pr_info("Tertiary cache size %ldK.\n", (tcache_size >> 10));
2701da177e4SLinus Torvalds }
271