1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_NOHASH_32_PTE_8xx_H 3 #define _ASM_POWERPC_NOHASH_32_PTE_8xx_H 4 #ifdef __KERNEL__ 5 6 /* 7 * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk. 8 * We also use the two level tables, but we can put the real bits in them 9 * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0, 10 * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has 11 * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit 12 * based upon user/super access. The TLB does not have accessed nor write 13 * protect. We assume that if the TLB get loaded with an entry it is 14 * accessed, and overload the changed bit for write protect. We use 15 * two bits in the software pte that are supposed to be set to zero in 16 * the TLB entry (24 and 25) for these indicators. Although the level 1 17 * descriptor contains the guarded and writethrough/copyback bits, we can 18 * set these at the page level since they get copied from the Mx_TWC 19 * register when the TLB entry is loaded. We will use bit 27 for guard, since 20 * that is where it exists in the MD_TWC, and bit 26 for writethrough. 21 * These will get masked from the level 2 descriptor at TLB load time, and 22 * copied to the MD_TWC before it gets loaded. 23 * Large page sizes added. We currently support two sizes, 4K and 8M. 24 * This also allows a TLB hander optimization because we can directly 25 * load the PMD into MD_TWC. The 8M pages are only used for kernel 26 * mapping of well known areas. The PMD (PGD) entries contain control 27 * flags in addition to the address, so care must be taken that the 28 * software no longer assumes these are only pointers. 29 */ 30 31 /* Definitions for 8xx embedded chips. */ 32 #define _PAGE_PRESENT 0x0001 /* V: Page is valid */ 33 #define _PAGE_NO_CACHE 0x0002 /* CI: cache inhibit */ 34 #define _PAGE_SH 0x0004 /* SH: No ASID (context) compare */ 35 #define _PAGE_SPS 0x0008 /* SPS: Small Page Size (1 if 16k, 512k or 8M)*/ 36 #define _PAGE_DIRTY 0x0100 /* C: page changed */ 37 38 /* These 4 software bits must be masked out when the L2 entry is loaded 39 * into the TLB. 40 */ 41 #define _PAGE_GUARDED 0x0010 /* Copied to L1 G entry in DTLB */ 42 #define _PAGE_ACCESSED 0x0020 /* Copied to L1 APG 1 entry in I/DTLB */ 43 #define _PAGE_EXEC 0x0040 /* Copied to PP (bit 21) in ITLB */ 44 #define _PAGE_SPECIAL 0x0080 /* SW entry */ 45 46 #define _PAGE_NA 0x0200 /* Supervisor NA, User no access */ 47 #define _PAGE_RO 0x0600 /* Supervisor RO, User no access */ 48 49 #define _PAGE_HUGE 0x0800 /* Copied to L1 PS bit 29 */ 50 51 #define _PAGE_NAX (_PAGE_NA | _PAGE_EXEC) 52 #define _PAGE_ROX (_PAGE_RO | _PAGE_EXEC) 53 #define _PAGE_RW 0 54 #define _PAGE_RWX _PAGE_EXEC 55 56 /* cache related flags non existing on 8xx */ 57 #define _PAGE_COHERENT 0 58 #define _PAGE_WRITETHRU 0 59 60 #define _PAGE_KERNEL_RO (_PAGE_SH | _PAGE_RO) 61 #define _PAGE_KERNEL_ROX (_PAGE_SH | _PAGE_RO | _PAGE_EXEC) 62 #define _PAGE_KERNEL_RW (_PAGE_SH | _PAGE_DIRTY) 63 #define _PAGE_KERNEL_RWX (_PAGE_SH | _PAGE_DIRTY | _PAGE_EXEC) 64 65 #define _PMD_PRESENT 0x0001 66 #define _PMD_PRESENT_MASK _PMD_PRESENT 67 #define _PMD_BAD 0x0f90 68 #define _PMD_PAGE_MASK 0x000c 69 #define _PMD_PAGE_8M 0x000c 70 #define _PMD_PAGE_512K 0x0004 71 #define _PMD_ACCESSED 0x0020 /* APG 1 */ 72 #define _PMD_USER 0x0040 /* APG 2 */ 73 74 #define _PTE_NONE_MASK 0 75 76 #ifdef CONFIG_PPC_16K_PAGES 77 #define _PAGE_PSIZE _PAGE_SPS 78 #else 79 #define _PAGE_PSIZE 0 80 #endif 81 82 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE) 83 #define _PAGE_BASE (_PAGE_BASE_NC) 84 85 #include <asm/pgtable-masks.h> 86 87 #ifndef __ASSEMBLY__ 88 static inline pte_t pte_wrprotect(pte_t pte) 89 { 90 return __pte(pte_val(pte) | _PAGE_RO); 91 } 92 93 #define pte_wrprotect pte_wrprotect 94 95 static inline int pte_read(pte_t pte) 96 { 97 return (pte_val(pte) & _PAGE_RO) != _PAGE_NA; 98 } 99 100 #define pte_read pte_read 101 102 static inline int pte_write(pte_t pte) 103 { 104 return !(pte_val(pte) & _PAGE_RO); 105 } 106 107 #define pte_write pte_write 108 109 static inline pte_t pte_mkwrite_novma(pte_t pte) 110 { 111 return __pte(pte_val(pte) & ~_PAGE_RO); 112 } 113 114 #define pte_mkwrite_novma pte_mkwrite_novma 115 116 static inline pte_t pte_mkhuge(pte_t pte) 117 { 118 return __pte(pte_val(pte) | _PAGE_SPS | _PAGE_HUGE); 119 } 120 121 #define pte_mkhuge pte_mkhuge 122 123 static inline pte_basic_t pte_update(struct mm_struct *mm, unsigned long addr, pte_t *p, 124 unsigned long clr, unsigned long set, int huge); 125 126 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 127 { 128 pte_update(mm, addr, ptep, 0, _PAGE_RO, 0); 129 } 130 #define ptep_set_wrprotect ptep_set_wrprotect 131 132 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep, 133 pte_t entry, unsigned long address, int psize) 134 { 135 unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_EXEC); 136 unsigned long clr = ~pte_val(entry) & _PAGE_RO; 137 int huge = psize > mmu_virtual_psize ? 1 : 0; 138 139 pte_update(vma->vm_mm, address, ptep, clr, set, huge); 140 141 flush_tlb_page(vma, address); 142 } 143 #define __ptep_set_access_flags __ptep_set_access_flags 144 145 static inline unsigned long pgd_leaf_size(pgd_t pgd) 146 { 147 if (pgd_val(pgd) & _PMD_PAGE_8M) 148 return SZ_8M; 149 return SZ_4M; 150 } 151 152 #define pgd_leaf_size pgd_leaf_size 153 154 static inline unsigned long pte_leaf_size(pte_t pte) 155 { 156 pte_basic_t val = pte_val(pte); 157 158 if (val & _PAGE_HUGE) 159 return SZ_512K; 160 if (val & _PAGE_SPS) 161 return SZ_16K; 162 return SZ_4K; 163 } 164 165 #define pte_leaf_size pte_leaf_size 166 167 /* 168 * On the 8xx, the page tables are a bit special. For 16k pages, we have 169 * 4 identical entries. For 512k pages, we have 128 entries as if it was 170 * 4k pages, but they are flagged as 512k pages for the hardware. 171 * For other page sizes, we have a single entry in the table. 172 */ 173 static pmd_t *pmd_off(struct mm_struct *mm, unsigned long addr); 174 static int hugepd_ok(hugepd_t hpd); 175 176 static inline int number_of_cells_per_pte(pmd_t *pmd, pte_basic_t val, int huge) 177 { 178 if (!huge) 179 return PAGE_SIZE / SZ_4K; 180 else if (hugepd_ok(*((hugepd_t *)pmd))) 181 return 1; 182 else if (IS_ENABLED(CONFIG_PPC_4K_PAGES) && !(val & _PAGE_HUGE)) 183 return SZ_16K / SZ_4K; 184 else 185 return SZ_512K / SZ_4K; 186 } 187 188 static inline pte_basic_t pte_update(struct mm_struct *mm, unsigned long addr, pte_t *p, 189 unsigned long clr, unsigned long set, int huge) 190 { 191 pte_basic_t *entry = (pte_basic_t *)p; 192 pte_basic_t old = pte_val(*p); 193 pte_basic_t new = (old & ~(pte_basic_t)clr) | set; 194 int num, i; 195 pmd_t *pmd = pmd_off(mm, addr); 196 197 num = number_of_cells_per_pte(pmd, new, huge); 198 199 for (i = 0; i < num; i += PAGE_SIZE / SZ_4K, new += PAGE_SIZE) { 200 *entry++ = new; 201 if (IS_ENABLED(CONFIG_PPC_16K_PAGES) && num != 1) { 202 *entry++ = new; 203 *entry++ = new; 204 *entry++ = new; 205 } 206 } 207 208 return old; 209 } 210 211 #define pte_update pte_update 212 213 #ifdef CONFIG_PPC_16K_PAGES 214 #define ptep_get ptep_get 215 static inline pte_t ptep_get(pte_t *ptep) 216 { 217 pte_basic_t val = READ_ONCE(ptep->pte); 218 pte_t pte = {val, val, val, val}; 219 220 return pte; 221 } 222 #endif /* CONFIG_PPC_16K_PAGES */ 223 224 #endif 225 226 #endif /* __KERNEL__ */ 227 #endif /* _ASM_POWERPC_NOHASH_32_PTE_8xx_H */ 228