1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 #ifndef _ASM_POWERPC_PROCESSOR_H 3 #define _ASM_POWERPC_PROCESSOR_H 4 5 /* 6 * Copyright (C) 2001 PPC 64 Team, IBM Corp 7 */ 8 9 #include <vdso/processor.h> 10 11 #include <asm/reg.h> 12 13 #ifdef CONFIG_VSX 14 #define TS_FPRWIDTH 2 15 16 #ifdef __BIG_ENDIAN__ 17 #define TS_FPROFFSET 0 18 #define TS_VSRLOWOFFSET 1 19 #else 20 #define TS_FPROFFSET 1 21 #define TS_VSRLOWOFFSET 0 22 #endif 23 24 #else 25 #define TS_FPRWIDTH 1 26 #define TS_FPROFFSET 0 27 #endif 28 29 #ifdef CONFIG_PPC64 30 /* Default SMT priority is set to 3. Use 11- 13bits to save priority. */ 31 #define PPR_PRIORITY 3 32 #ifdef __ASSEMBLY__ 33 #define DEFAULT_PPR (PPR_PRIORITY << 50) 34 #else 35 #define DEFAULT_PPR ((u64)PPR_PRIORITY << 50) 36 #endif /* __ASSEMBLY__ */ 37 #endif /* CONFIG_PPC64 */ 38 39 #ifndef __ASSEMBLY__ 40 #include <linux/types.h> 41 #include <linux/thread_info.h> 42 #include <asm/ptrace.h> 43 #include <asm/hw_breakpoint.h> 44 45 /* We do _not_ want to define new machine types at all, those must die 46 * in favor of using the device-tree 47 * -- BenH. 48 */ 49 50 /* PREP sub-platform types. Unused */ 51 #define _PREP_Motorola 0x01 /* motorola prep */ 52 #define _PREP_Firm 0x02 /* firmworks prep */ 53 #define _PREP_IBM 0x00 /* ibm prep */ 54 #define _PREP_Bull 0x03 /* bull prep */ 55 56 /* CHRP sub-platform types. These are arbitrary */ 57 #define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ 58 #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ 59 #define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */ 60 #define _CHRP_briq 0x07 /* TotalImpact's briQ */ 61 62 #if defined(__KERNEL__) && defined(CONFIG_PPC32) 63 64 extern int _chrp_type; 65 66 #endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */ 67 68 #ifdef __KERNEL__ 69 70 #ifdef CONFIG_PPC64 71 #include <asm/task_size_64.h> 72 #else 73 #include <asm/task_size_32.h> 74 #endif 75 76 struct task_struct; 77 void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp); 78 79 #define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET] 80 #define TS_CKFPR(i) ckfp_state.fpr[i][TS_FPROFFSET] 81 82 /* FP and VSX 0-31 register set */ 83 struct thread_fp_state { 84 u64 fpr[32][TS_FPRWIDTH] __attribute__((aligned(16))); 85 u64 fpscr; /* Floating point status */ 86 }; 87 88 /* Complete AltiVec register set including VSCR */ 89 struct thread_vr_state { 90 vector128 vr[32] __attribute__((aligned(16))); 91 vector128 vscr __attribute__((aligned(16))); 92 }; 93 94 struct debug_reg { 95 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 96 /* 97 * The following help to manage the use of Debug Control Registers 98 * om the BookE platforms. 99 */ 100 uint32_t dbcr0; 101 uint32_t dbcr1; 102 #ifdef CONFIG_BOOKE 103 uint32_t dbcr2; 104 #endif 105 /* 106 * The stored value of the DBSR register will be the value at the 107 * last debug interrupt. This register can only be read from the 108 * user (will never be written to) and has value while helping to 109 * describe the reason for the last debug trap. Torez 110 */ 111 uint32_t dbsr; 112 /* 113 * The following will contain addresses used by debug applications 114 * to help trace and trap on particular address locations. 115 * The bits in the Debug Control Registers above help define which 116 * of the following registers will contain valid data and/or addresses. 117 */ 118 unsigned long iac1; 119 unsigned long iac2; 120 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 121 unsigned long iac3; 122 unsigned long iac4; 123 #endif 124 unsigned long dac1; 125 unsigned long dac2; 126 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 127 unsigned long dvc1; 128 unsigned long dvc2; 129 #endif 130 #endif 131 }; 132 133 struct thread_struct { 134 unsigned long ksp; /* Kernel stack pointer */ 135 136 #ifdef CONFIG_PPC64 137 unsigned long ksp_vsid; 138 #endif 139 struct pt_regs *regs; /* Pointer to saved register state */ 140 #ifdef CONFIG_BOOKE 141 /* BookE base exception scratch space; align on cacheline */ 142 unsigned long normsave[8] ____cacheline_aligned; 143 #endif 144 #ifdef CONFIG_PPC32 145 void *pgdir; /* root of page-table tree */ 146 #ifdef CONFIG_PPC_RTAS 147 unsigned long rtas_sp; /* stack pointer for when in RTAS */ 148 #endif 149 #if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP) 150 unsigned long kuap; /* opened segments for user access */ 151 #endif 152 unsigned long srr0; 153 unsigned long srr1; 154 unsigned long dar; 155 unsigned long dsisr; 156 #ifdef CONFIG_PPC_BOOK3S_32 157 unsigned long r0, r3, r4, r5, r6, r8, r9, r11; 158 unsigned long lr, ctr; 159 unsigned long sr0; 160 #endif 161 #endif /* CONFIG_PPC32 */ 162 #if defined(CONFIG_BOOKE_OR_40x) && defined(CONFIG_PPC_KUAP) 163 unsigned long pid; /* value written in PID reg. at interrupt exit */ 164 #endif 165 /* Debug Registers */ 166 struct debug_reg debug; 167 #ifdef CONFIG_PPC_FPU_REGS 168 struct thread_fp_state fp_state; 169 struct thread_fp_state *fp_save_area; 170 #endif 171 int fpexc_mode; /* floating-point exception mode */ 172 unsigned int align_ctl; /* alignment handling control */ 173 #ifdef CONFIG_HAVE_HW_BREAKPOINT 174 struct perf_event *ptrace_bps[HBP_NUM_MAX]; 175 /* 176 * Helps identify source of single-step exception and subsequent 177 * hw-breakpoint enablement 178 */ 179 struct perf_event *last_hit_ubp[HBP_NUM_MAX]; 180 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 181 struct arch_hw_breakpoint hw_brk[HBP_NUM_MAX]; /* hardware breakpoint info */ 182 unsigned long trap_nr; /* last trap # on this thread */ 183 u8 load_slb; /* Ages out SLB preload cache entries */ 184 u8 load_fp; 185 #ifdef CONFIG_ALTIVEC 186 u8 load_vec; 187 struct thread_vr_state vr_state; 188 struct thread_vr_state *vr_save_area; 189 unsigned long vrsave; 190 int used_vr; /* set if process has used altivec */ 191 #endif /* CONFIG_ALTIVEC */ 192 #ifdef CONFIG_VSX 193 /* VSR status */ 194 int used_vsr; /* set if process has used VSX */ 195 #endif /* CONFIG_VSX */ 196 #ifdef CONFIG_SPE 197 struct_group(spe, 198 unsigned long evr[32]; /* upper 32-bits of SPE regs */ 199 u64 acc; /* Accumulator */ 200 ); 201 unsigned long spefscr; /* SPE & eFP status */ 202 unsigned long spefscr_last; /* SPEFSCR value on last prctl 203 call or trap return */ 204 int used_spe; /* set if process has used spe */ 205 #endif /* CONFIG_SPE */ 206 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 207 u8 load_tm; 208 u64 tm_tfhar; /* Transaction fail handler addr */ 209 u64 tm_texasr; /* Transaction exception & summary */ 210 u64 tm_tfiar; /* Transaction fail instr address reg */ 211 struct pt_regs ckpt_regs; /* Checkpointed registers */ 212 213 unsigned long tm_tar; 214 unsigned long tm_ppr; 215 unsigned long tm_dscr; 216 unsigned long tm_amr; 217 218 /* 219 * Checkpointed FP and VSX 0-31 register set. 220 * 221 * When a transaction is active/signalled/scheduled etc., *regs is the 222 * most recent set of/speculated GPRs with ckpt_regs being the older 223 * checkpointed regs to which we roll back if transaction aborts. 224 * 225 * These are analogous to how ckpt_regs and pt_regs work 226 */ 227 struct thread_fp_state ckfp_state; /* Checkpointed FP state */ 228 struct thread_vr_state ckvr_state; /* Checkpointed VR state */ 229 unsigned long ckvrsave; /* Checkpointed VRSAVE */ 230 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 231 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER 232 void* kvm_shadow_vcpu; /* KVM internal data */ 233 #endif /* CONFIG_KVM_BOOK3S_32_HANDLER */ 234 #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE) 235 struct kvm_vcpu *kvm_vcpu; 236 #endif 237 #ifdef CONFIG_PPC64 238 unsigned long dscr; 239 unsigned long fscr; 240 /* 241 * This member element dscr_inherit indicates that the process 242 * has explicitly attempted and changed the DSCR register value 243 * for itself. Hence kernel wont use the default CPU DSCR value 244 * contained in the PACA structure anymore during process context 245 * switch. Once this variable is set, this behaviour will also be 246 * inherited to all the children of this process from that point 247 * onwards. 248 */ 249 int dscr_inherit; 250 unsigned long tidr; 251 #endif 252 #ifdef CONFIG_PPC_BOOK3S_64 253 unsigned long tar; 254 unsigned long ebbrr; 255 unsigned long ebbhr; 256 unsigned long bescr; 257 unsigned long siar; 258 unsigned long sdar; 259 unsigned long sier; 260 unsigned long mmcr2; 261 unsigned mmcr0; 262 263 unsigned used_ebb; 264 unsigned long mmcr3; 265 unsigned long sier2; 266 unsigned long sier3; 267 268 #endif 269 }; 270 271 #define ARCH_MIN_TASKALIGN 16 272 273 #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) 274 #define INIT_SP_LIMIT ((unsigned long)&init_stack) 275 276 #ifdef CONFIG_SPE 277 #define SPEFSCR_INIT \ 278 .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \ 279 .spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, 280 #else 281 #define SPEFSCR_INIT 282 #endif 283 284 #ifdef CONFIG_PPC_BOOK3S_32 285 #define SR0_INIT .sr0 = IS_ENABLED(CONFIG_PPC_KUEP) ? SR_NX : 0, 286 #else 287 #define SR0_INIT 288 #endif 289 290 #if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP) 291 #define INIT_THREAD { \ 292 .ksp = INIT_SP, \ 293 .pgdir = swapper_pg_dir, \ 294 .kuap = ~0UL, /* KUAP_NONE */ \ 295 .fpexc_mode = MSR_FE0 | MSR_FE1, \ 296 SPEFSCR_INIT \ 297 SR0_INIT \ 298 } 299 #elif defined(CONFIG_PPC32) 300 #define INIT_THREAD { \ 301 .ksp = INIT_SP, \ 302 .pgdir = swapper_pg_dir, \ 303 .fpexc_mode = MSR_FE0 | MSR_FE1, \ 304 SPEFSCR_INIT \ 305 SR0_INIT \ 306 } 307 #else 308 #define INIT_THREAD { \ 309 .ksp = INIT_SP, \ 310 .fpexc_mode = 0, \ 311 } 312 #endif 313 314 #define task_pt_regs(tsk) ((tsk)->thread.regs) 315 316 unsigned long __get_wchan(struct task_struct *p); 317 318 #define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0) 319 #define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0) 320 321 /* Get/set floating-point exception mode */ 322 #define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr)) 323 #define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val)) 324 325 extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr); 326 extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val); 327 328 #define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr)) 329 #define SET_ENDIAN(tsk, val) set_endian((tsk), (val)) 330 331 extern int get_endian(struct task_struct *tsk, unsigned long adr); 332 extern int set_endian(struct task_struct *tsk, unsigned int val); 333 334 #define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr)) 335 #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) 336 337 extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr); 338 extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val); 339 340 extern void load_fp_state(struct thread_fp_state *fp); 341 extern void store_fp_state(struct thread_fp_state *fp); 342 extern void load_vr_state(struct thread_vr_state *vr); 343 extern void store_vr_state(struct thread_vr_state *vr); 344 345 static inline unsigned int __unpack_fe01(unsigned long msr_bits) 346 { 347 return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8); 348 } 349 350 static inline unsigned long __pack_fe01(unsigned int fpmode) 351 { 352 return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1); 353 } 354 355 #ifdef CONFIG_PPC64 356 357 #define spin_begin() \ 358 asm volatile(ASM_FTR_IFCLR( \ 359 "or 1,1,1", /* HMT_LOW */ \ 360 "nop", /* v3.1 uses pause_short in cpu_relax instead */ \ 361 %0) :: "i" (CPU_FTR_ARCH_31) : "memory") 362 363 #define spin_cpu_relax() \ 364 asm volatile(ASM_FTR_IFCLR( \ 365 "nop", /* Before v3.1 use priority nops in spin_begin/end */ \ 366 PPC_WAIT(2, 0), /* aka pause_short */ \ 367 %0) :: "i" (CPU_FTR_ARCH_31) : "memory") 368 369 #define spin_end() \ 370 asm volatile(ASM_FTR_IFCLR( \ 371 "or 2,2,2", /* HMT_MEDIUM */ \ 372 "nop", \ 373 %0) :: "i" (CPU_FTR_ARCH_31) : "memory") 374 375 #endif 376 377 /* Check that a certain kernel stack pointer is valid in task_struct p */ 378 int validate_sp(unsigned long sp, struct task_struct *p, 379 unsigned long nbytes); 380 381 /* 382 * Prefetch macros. 383 */ 384 #define ARCH_HAS_PREFETCH 385 #define ARCH_HAS_PREFETCHW 386 #define ARCH_HAS_SPINLOCK_PREFETCH 387 388 static inline void prefetch(const void *x) 389 { 390 if (unlikely(!x)) 391 return; 392 393 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x)); 394 } 395 396 static inline void prefetchw(const void *x) 397 { 398 if (unlikely(!x)) 399 return; 400 401 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x)); 402 } 403 404 #define spin_lock_prefetch(x) prefetchw(x) 405 406 /* asm stubs */ 407 extern unsigned long isa300_idle_stop_noloss(unsigned long psscr_val); 408 extern unsigned long isa300_idle_stop_mayloss(unsigned long psscr_val); 409 extern unsigned long isa206_idle_insn_mayloss(unsigned long type); 410 #ifdef CONFIG_PPC_970_NAP 411 extern void power4_idle_nap(void); 412 void power4_idle_nap_return(void); 413 #endif 414 415 extern unsigned long cpuidle_disable; 416 enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF}; 417 418 extern int powersave_nap; /* set if nap mode can be used in idle loop */ 419 420 extern void power7_idle_type(unsigned long type); 421 extern void arch300_idle_type(unsigned long stop_psscr_val, 422 unsigned long stop_psscr_mask); 423 void pnv_power9_force_smt4_catch(void); 424 void pnv_power9_force_smt4_release(void); 425 426 extern int fix_alignment(struct pt_regs *); 427 428 #ifdef CONFIG_PPC64 429 /* 430 * We handle most unaligned accesses in hardware. On the other hand 431 * unaligned DMA can be very expensive on some ppc64 IO chips (it does 432 * powers of 2 writes until it reaches sufficient alignment). 433 * 434 * Based on this we disable the IP header alignment in network drivers. 435 */ 436 #define NET_IP_ALIGN 0 437 #endif 438 439 int do_mathemu(struct pt_regs *regs); 440 int do_spe_mathemu(struct pt_regs *regs); 441 int speround_handler(struct pt_regs *regs); 442 443 /* VMX copying */ 444 int enter_vmx_usercopy(void); 445 int exit_vmx_usercopy(void); 446 int enter_vmx_ops(void); 447 void *exit_vmx_ops(void *dest); 448 449 #endif /* __KERNEL__ */ 450 #endif /* __ASSEMBLY__ */ 451 #endif /* _ASM_POWERPC_PROCESSOR_H */ 452