xref: /linux/arch/powerpc/kernel/head_85xx.S (revision 2da68a77) 
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Kernel execution entry point code.
4 *
5 *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
6 *	Initial PowerPC version.
7 *    Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
8 *	Rewritten for PReP
9 *    Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
10 *	Low-level exception handers, MMU support, and rewrite.
11 *    Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
12 *	PowerPC 8xx modifications.
13 *    Copyright (c) 1998-1999 TiVo, Inc.
14 *	PowerPC 403GCX modifications.
15 *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
16 *	PowerPC 403GCX/405GP modifications.
17 *    Copyright 2000 MontaVista Software Inc.
18 *	PPC405 modifications
19 *	PowerPC 403GCX/405GP modifications.
20 *	Author: MontaVista Software, Inc.
21 *		frank_rowand@mvista.com or source@mvista.com
22 *		debbie_chu@mvista.com
23 *    Copyright 2002-2004 MontaVista Software, Inc.
24 *	PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
25 *    Copyright 2004 Freescale Semiconductor, Inc
26 *	PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
27 */
28
29#include <linux/init.h>
30#include <linux/threads.h>
31#include <linux/pgtable.h>
32#include <asm/processor.h>
33#include <asm/page.h>
34#include <asm/mmu.h>
35#include <asm/cputable.h>
36#include <asm/thread_info.h>
37#include <asm/ppc_asm.h>
38#include <asm/asm-offsets.h>
39#include <asm/cache.h>
40#include <asm/ptrace.h>
41#include <asm/export.h>
42#include <asm/feature-fixups.h>
43#include "head_booke.h"
44
45/* As with the other PowerPC ports, it is expected that when code
46 * execution begins here, the following registers contain valid, yet
47 * optional, information:
48 *
49 *   r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
50 *   r4 - Starting address of the init RAM disk
51 *   r5 - Ending address of the init RAM disk
52 *   r6 - Start of kernel command line string (e.g. "mem=128")
53 *   r7 - End of kernel command line string
54 *
55 */
56	__HEAD
57_GLOBAL(_stext);
58_GLOBAL(_start);
59	/*
60	 * Reserve a word at a fixed location to store the address
61	 * of abatron_pteptrs
62	 */
63	nop
64
65	/* Translate device tree address to physical, save in r30/r31 */
66	bl	get_phys_addr
67	mr	r30,r3
68	mr	r31,r4
69
70	li	r25,0			/* phys kernel start (low) */
71	li	r24,0			/* CPU number */
72	li	r23,0			/* phys kernel start (high) */
73
74#ifdef CONFIG_RELOCATABLE
75	LOAD_REG_ADDR_PIC(r3, _stext)	/* Get our current runtime base */
76
77	/* Translate _stext address to physical, save in r23/r25 */
78	bl	get_phys_addr
79	mr	r23,r3
80	mr	r25,r4
81
82	bcl	20,31,$+4
830:	mflr	r8
84	addis	r3,r8,(is_second_reloc - 0b)@ha
85	lwz	r19,(is_second_reloc - 0b)@l(r3)
86
87	/* Check if this is the second relocation. */
88	cmpwi	r19,1
89	bne	1f
90
91	/*
92	 * For the second relocation, we already get the real memstart_addr
93	 * from device tree. So we will map PAGE_OFFSET to memstart_addr,
94	 * then the virtual address of start kernel should be:
95	 *          PAGE_OFFSET + (kernstart_addr - memstart_addr)
96	 * Since the offset between kernstart_addr and memstart_addr should
97	 * never be beyond 1G, so we can just use the lower 32bit of them
98	 * for the calculation.
99	 */
100	lis	r3,PAGE_OFFSET@h
101
102	addis	r4,r8,(kernstart_addr - 0b)@ha
103	addi	r4,r4,(kernstart_addr - 0b)@l
104	lwz	r5,4(r4)
105
106	addis	r6,r8,(memstart_addr - 0b)@ha
107	addi	r6,r6,(memstart_addr - 0b)@l
108	lwz	r7,4(r6)
109
110	subf	r5,r7,r5
111	add	r3,r3,r5
112	b	2f
113
1141:
115	/*
116	 * We have the runtime (virtual) address of our base.
117	 * We calculate our shift of offset from a 64M page.
118	 * We could map the 64M page we belong to at PAGE_OFFSET and
119	 * get going from there.
120	 */
121	lis	r4,KERNELBASE@h
122	ori	r4,r4,KERNELBASE@l
123	rlwinm	r6,r25,0,0x3ffffff		/* r6 = PHYS_START % 64M */
124	rlwinm	r5,r4,0,0x3ffffff		/* r5 = KERNELBASE % 64M */
125	subf	r3,r5,r6			/* r3 = r6 - r5 */
126	add	r3,r4,r3			/* Required Virtual Address */
127
1282:	bl	relocate
129
130	/*
131	 * For the second relocation, we already set the right tlb entries
132	 * for the kernel space, so skip the code in 85xx_entry_mapping.S
133	*/
134	cmpwi	r19,1
135	beq	set_ivor
136#endif
137
138/* We try to not make any assumptions about how the boot loader
139 * setup or used the TLBs.  We invalidate all mappings from the
140 * boot loader and load a single entry in TLB1[0] to map the
141 * first 64M of kernel memory.  Any boot info passed from the
142 * bootloader needs to live in this first 64M.
143 *
144 * Requirement on bootloader:
145 *  - The page we're executing in needs to reside in TLB1 and
146 *    have IPROT=1.  If not an invalidate broadcast could
147 *    evict the entry we're currently executing in.
148 *
149 *  r3 = Index of TLB1 were executing in
150 *  r4 = Current MSR[IS]
151 *  r5 = Index of TLB1 temp mapping
152 *
153 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
154 * if needed
155 */
156
157_GLOBAL(__early_start)
158	LOAD_REG_ADDR_PIC(r20, kernstart_virt_addr)
159	lwz     r20,0(r20)
160
161#define ENTRY_MAPPING_BOOT_SETUP
162#include "85xx_entry_mapping.S"
163#undef ENTRY_MAPPING_BOOT_SETUP
164
165set_ivor:
166	/* Establish the interrupt vector offsets */
167	SET_IVOR(0,  CriticalInput);
168	SET_IVOR(1,  MachineCheck);
169	SET_IVOR(2,  DataStorage);
170	SET_IVOR(3,  InstructionStorage);
171	SET_IVOR(4,  ExternalInput);
172	SET_IVOR(5,  Alignment);
173	SET_IVOR(6,  Program);
174	SET_IVOR(7,  FloatingPointUnavailable);
175	SET_IVOR(8,  SystemCall);
176	SET_IVOR(9,  AuxillaryProcessorUnavailable);
177	SET_IVOR(10, Decrementer);
178	SET_IVOR(11, FixedIntervalTimer);
179	SET_IVOR(12, WatchdogTimer);
180	SET_IVOR(13, DataTLBError);
181	SET_IVOR(14, InstructionTLBError);
182	SET_IVOR(15, DebugCrit);
183
184	/* Establish the interrupt vector base */
185	lis	r4,interrupt_base@h	/* IVPR only uses the high 16-bits */
186	mtspr	SPRN_IVPR,r4
187
188	/* Setup the defaults for TLB entries */
189	li	r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
190	mtspr	SPRN_MAS4, r2
191
192#if !defined(CONFIG_BDI_SWITCH)
193	/*
194	 * The Abatron BDI JTAG debugger does not tolerate others
195	 * mucking with the debug registers.
196	 */
197	lis	r2,DBCR0_IDM@h
198	mtspr	SPRN_DBCR0,r2
199	isync
200	/* clear any residual debug events */
201	li	r2,-1
202	mtspr	SPRN_DBSR,r2
203#endif
204
205#ifdef CONFIG_SMP
206	/* Check to see if we're the second processor, and jump
207	 * to the secondary_start code if so
208	 */
209	LOAD_REG_ADDR_PIC(r24, boot_cpuid)
210	lwz	r24, 0(r24)
211	cmpwi	r24, -1
212	mfspr   r24,SPRN_PIR
213	bne	__secondary_start
214#endif
215
216	/*
217	 * This is where the main kernel code starts.
218	 */
219
220	/* ptr to current */
221	lis	r2,init_task@h
222	ori	r2,r2,init_task@l
223
224	/* ptr to current thread */
225	addi	r4,r2,THREAD	/* init task's THREAD */
226	mtspr	SPRN_SPRG_THREAD,r4
227
228	/* stack */
229	lis	r1,init_thread_union@h
230	ori	r1,r1,init_thread_union@l
231	li	r0,0
232	stwu	r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
233
234#ifdef CONFIG_SMP
235	stw	r24, TASK_CPU(r2)
236#endif
237
238	bl	early_init
239
240#ifdef CONFIG_KASAN
241	bl	kasan_early_init
242#endif
243#ifdef CONFIG_RELOCATABLE
244	mr	r3,r30
245	mr	r4,r31
246#ifdef CONFIG_PHYS_64BIT
247	mr	r5,r23
248	mr	r6,r25
249#else
250	mr	r5,r25
251#endif
252	bl	relocate_init
253#endif
254
255#ifdef CONFIG_DYNAMIC_MEMSTART
256	lis	r3,kernstart_addr@ha
257	la	r3,kernstart_addr@l(r3)
258#ifdef CONFIG_PHYS_64BIT
259	stw	r23,0(r3)
260	stw	r25,4(r3)
261#else
262	stw	r25,0(r3)
263#endif
264#endif
265
266/*
267 * Decide what sort of machine this is and initialize the MMU.
268 */
269	mr	r3,r30
270	mr	r4,r31
271	bl	machine_init
272	bl	MMU_init
273
274	/* Setup PTE pointers for the Abatron bdiGDB */
275	lis	r6, swapper_pg_dir@h
276	ori	r6, r6, swapper_pg_dir@l
277	lis	r5, abatron_pteptrs@h
278	ori	r5, r5, abatron_pteptrs@l
279	lis     r3, kernstart_virt_addr@ha
280	lwz     r4, kernstart_virt_addr@l(r3)
281	stw	r5, 0(r4)	/* Save abatron_pteptrs at a fixed location */
282	stw	r6, 0(r5)
283
284	/* Let's move on */
285	lis	r4,start_kernel@h
286	ori	r4,r4,start_kernel@l
287	lis	r3,MSR_KERNEL@h
288	ori	r3,r3,MSR_KERNEL@l
289	mtspr	SPRN_SRR0,r4
290	mtspr	SPRN_SRR1,r3
291	rfi			/* change context and jump to start_kernel */
292
293/* Macros to hide the PTE size differences
294 *
295 * FIND_PTE -- walks the page tables given EA & pgdir pointer
296 *   r10 -- EA of fault
297 *   r11 -- PGDIR pointer
298 *   r12 -- free
299 *   label 2: is the bailout case
300 *
301 * if we find the pte (fall through):
302 *   r11 is low pte word
303 *   r12 is pointer to the pte
304 *   r10 is the pshift from the PGD, if we're a hugepage
305 */
306#ifdef CONFIG_PTE_64BIT
307#ifdef CONFIG_HUGETLB_PAGE
308#define FIND_PTE	\
309	rlwinm	r12, r10, 13, 19, 29;	/* Compute pgdir/pmd offset */	\
310	lwzx	r11, r12, r11;		/* Get pgd/pmd entry */		\
311	rlwinm.	r12, r11, 0, 0, 20;	/* Extract pt base address */	\
312	blt	1000f;			/* Normal non-huge page */	\
313	beq	2f;			/* Bail if no table */		\
314	oris	r11, r11, PD_HUGE@h;	/* Put back address bit */	\
315	andi.	r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */	\
316	xor	r12, r10, r11;		/* drop size bits from pointer */ \
317	b	1001f;							\
3181000:	rlwimi	r12, r10, 23, 20, 28;	/* Compute pte address */	\
319	li	r10, 0;			/* clear r10 */			\
3201001:	lwz	r11, 4(r12);		/* Get pte entry */
321#else
322#define FIND_PTE	\
323	rlwinm	r12, r10, 13, 19, 29;	/* Compute pgdir/pmd offset */	\
324	lwzx	r11, r12, r11;		/* Get pgd/pmd entry */		\
325	rlwinm.	r12, r11, 0, 0, 20;	/* Extract pt base address */	\
326	beq	2f;			/* Bail if no table */		\
327	rlwimi	r12, r10, 23, 20, 28;	/* Compute pte address */	\
328	lwz	r11, 4(r12);		/* Get pte entry */
329#endif /* HUGEPAGE */
330#else /* !PTE_64BIT */
331#define FIND_PTE	\
332	rlwimi	r11, r10, 12, 20, 29;	/* Create L1 (pgdir/pmd) address */	\
333	lwz	r11, 0(r11);		/* Get L1 entry */			\
334	rlwinm.	r12, r11, 0, 0, 19;	/* Extract L2 (pte) base address */	\
335	beq	2f;			/* Bail if no table */			\
336	rlwimi	r12, r10, 22, 20, 29;	/* Compute PTE address */		\
337	lwz	r11, 0(r12);		/* Get Linux PTE */
338#endif
339
340/*
341 * Interrupt vector entry code
342 *
343 * The Book E MMUs are always on so we don't need to handle
344 * interrupts in real mode as with previous PPC processors. In
345 * this case we handle interrupts in the kernel virtual address
346 * space.
347 *
348 * Interrupt vectors are dynamically placed relative to the
349 * interrupt prefix as determined by the address of interrupt_base.
350 * The interrupt vectors offsets are programmed using the labels
351 * for each interrupt vector entry.
352 *
353 * Interrupt vectors must be aligned on a 16 byte boundary.
354 * We align on a 32 byte cache line boundary for good measure.
355 */
356
357interrupt_base:
358	/* Critical Input Interrupt */
359	CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception)
360
361	/* Machine Check Interrupt */
362	MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
363
364	/* Data Storage Interrupt */
365	START_EXCEPTION(DataStorage)
366	NORMAL_EXCEPTION_PROLOG(0x300, DATA_STORAGE)
367	mfspr	r5,SPRN_ESR		/* Grab the ESR, save it */
368	stw	r5,_ESR(r11)
369	mfspr	r4,SPRN_DEAR		/* Grab the DEAR, save it */
370	stw	r4, _DEAR(r11)
371	andis.	r10,r5,(ESR_ILK|ESR_DLK)@h
372	bne	1f
373	prepare_transfer_to_handler
374	bl	do_page_fault
375	b	interrupt_return
3761:
377	prepare_transfer_to_handler
378	bl	CacheLockingException
379	b	interrupt_return
380
381	/* Instruction Storage Interrupt */
382	INSTRUCTION_STORAGE_EXCEPTION
383
384	/* External Input Interrupt */
385	EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ)
386
387	/* Alignment Interrupt */
388	ALIGNMENT_EXCEPTION
389
390	/* Program Interrupt */
391	PROGRAM_EXCEPTION
392
393	/* Floating Point Unavailable Interrupt */
394#ifdef CONFIG_PPC_FPU
395	FP_UNAVAILABLE_EXCEPTION
396#else
397	EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, unknown_exception)
398#endif
399
400	/* System Call Interrupt */
401	START_EXCEPTION(SystemCall)
402	SYSCALL_ENTRY   0xc00 BOOKE_INTERRUPT_SYSCALL SPRN_SRR1
403
404	/* Auxiliary Processor Unavailable Interrupt */
405	EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, unknown_exception)
406
407	/* Decrementer Interrupt */
408	DECREMENTER_EXCEPTION
409
410	/* Fixed Internal Timer Interrupt */
411	/* TODO: Add FIT support */
412	EXCEPTION(0x3100, FIT, FixedIntervalTimer, unknown_exception)
413
414	/* Watchdog Timer Interrupt */
415#ifdef CONFIG_BOOKE_WDT
416	CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException)
417#else
418	CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception)
419#endif
420
421	/* Data TLB Error Interrupt */
422	START_EXCEPTION(DataTLBError)
423	mtspr	SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
424	mfspr	r10, SPRN_SPRG_THREAD
425	stw	r11, THREAD_NORMSAVE(0)(r10)
426#ifdef CONFIG_KVM_BOOKE_HV
427BEGIN_FTR_SECTION
428	mfspr	r11, SPRN_SRR1
429END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
430#endif
431	stw	r12, THREAD_NORMSAVE(1)(r10)
432	stw	r13, THREAD_NORMSAVE(2)(r10)
433	mfcr	r13
434	stw	r13, THREAD_NORMSAVE(3)(r10)
435	DO_KVM	BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1
436START_BTB_FLUSH_SECTION
437	mfspr r11, SPRN_SRR1
438	andi. r10,r11,MSR_PR
439	beq 1f
440	BTB_FLUSH(r10)
4411:
442END_BTB_FLUSH_SECTION
443	mfspr	r10, SPRN_DEAR		/* Get faulting address */
444
445	/* If we are faulting a kernel address, we have to use the
446	 * kernel page tables.
447	 */
448	lis	r11, PAGE_OFFSET@h
449	cmplw	5, r10, r11
450	blt	5, 3f
451	lis	r11, swapper_pg_dir@h
452	ori	r11, r11, swapper_pg_dir@l
453
454	mfspr	r12,SPRN_MAS1		/* Set TID to 0 */
455	rlwinm	r12,r12,0,16,1
456	mtspr	SPRN_MAS1,r12
457
458	b	4f
459
460	/* Get the PGD for the current thread */
4613:
462	mfspr	r11,SPRN_SPRG_THREAD
463	lwz	r11,PGDIR(r11)
464
465#ifdef CONFIG_PPC_KUAP
466	mfspr	r12, SPRN_MAS1
467	rlwinm.	r12,r12,0,0x3fff0000
468	beq	2f			/* KUAP fault */
469#endif
470
4714:
472	/* Mask of required permission bits. Note that while we
473	 * do copy ESR:ST to _PAGE_RW position as trying to write
474	 * to an RO page is pretty common, we don't do it with
475	 * _PAGE_DIRTY. We could do it, but it's a fairly rare
476	 * event so I'd rather take the overhead when it happens
477	 * rather than adding an instruction here. We should measure
478	 * whether the whole thing is worth it in the first place
479	 * as we could avoid loading SPRN_ESR completely in the first
480	 * place...
481	 *
482	 * TODO: Is it worth doing that mfspr & rlwimi in the first
483	 *       place or can we save a couple of instructions here ?
484	 */
485	mfspr	r12,SPRN_ESR
486#ifdef CONFIG_PTE_64BIT
487	li	r13,_PAGE_PRESENT
488	oris	r13,r13,_PAGE_ACCESSED@h
489#else
490	li	r13,_PAGE_PRESENT|_PAGE_ACCESSED
491#endif
492	rlwimi	r13,r12,11,29,29
493
494	FIND_PTE
495	andc.	r13,r13,r11		/* Check permission */
496
497#ifdef CONFIG_PTE_64BIT
498#ifdef CONFIG_SMP
499	subf	r13,r11,r12		/* create false data dep */
500	lwzx	r13,r11,r13		/* Get upper pte bits */
501#else
502	lwz	r13,0(r12)		/* Get upper pte bits */
503#endif
504#endif
505
506	bne	2f			/* Bail if permission/valid mismatch */
507
508	/* Jump to common tlb load */
509	b	finish_tlb_load
5102:
511	/* The bailout.  Restore registers to pre-exception conditions
512	 * and call the heavyweights to help us out.
513	 */
514	mfspr	r10, SPRN_SPRG_THREAD
515	lwz	r11, THREAD_NORMSAVE(3)(r10)
516	mtcr	r11
517	lwz	r13, THREAD_NORMSAVE(2)(r10)
518	lwz	r12, THREAD_NORMSAVE(1)(r10)
519	lwz	r11, THREAD_NORMSAVE(0)(r10)
520	mfspr	r10, SPRN_SPRG_RSCRATCH0
521	b	DataStorage
522
523	/* Instruction TLB Error Interrupt */
524	/*
525	 * Nearly the same as above, except we get our
526	 * information from different registers and bailout
527	 * to a different point.
528	 */
529	START_EXCEPTION(InstructionTLBError)
530	mtspr	SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
531	mfspr	r10, SPRN_SPRG_THREAD
532	stw	r11, THREAD_NORMSAVE(0)(r10)
533#ifdef CONFIG_KVM_BOOKE_HV
534BEGIN_FTR_SECTION
535	mfspr	r11, SPRN_SRR1
536END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
537#endif
538	stw	r12, THREAD_NORMSAVE(1)(r10)
539	stw	r13, THREAD_NORMSAVE(2)(r10)
540	mfcr	r13
541	stw	r13, THREAD_NORMSAVE(3)(r10)
542	DO_KVM	BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1
543START_BTB_FLUSH_SECTION
544	mfspr r11, SPRN_SRR1
545	andi. r10,r11,MSR_PR
546	beq 1f
547	BTB_FLUSH(r10)
5481:
549END_BTB_FLUSH_SECTION
550
551	mfspr	r10, SPRN_SRR0		/* Get faulting address */
552
553	/* If we are faulting a kernel address, we have to use the
554	 * kernel page tables.
555	 */
556	lis	r11, PAGE_OFFSET@h
557	cmplw	5, r10, r11
558	blt	5, 3f
559	lis	r11, swapper_pg_dir@h
560	ori	r11, r11, swapper_pg_dir@l
561
562	mfspr	r12,SPRN_MAS1		/* Set TID to 0 */
563	rlwinm	r12,r12,0,16,1
564	mtspr	SPRN_MAS1,r12
565
566	/* Make up the required permissions for kernel code */
567#ifdef CONFIG_PTE_64BIT
568	li	r13,_PAGE_PRESENT | _PAGE_BAP_SX
569	oris	r13,r13,_PAGE_ACCESSED@h
570#else
571	li	r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
572#endif
573	b	4f
574
575	/* Get the PGD for the current thread */
5763:
577	mfspr	r11,SPRN_SPRG_THREAD
578	lwz	r11,PGDIR(r11)
579
580#ifdef CONFIG_PPC_KUAP
581	mfspr	r12, SPRN_MAS1
582	rlwinm.	r12,r12,0,0x3fff0000
583	beq	2f			/* KUAP fault */
584#endif
585
586	/* Make up the required permissions for user code */
587#ifdef CONFIG_PTE_64BIT
588	li	r13,_PAGE_PRESENT | _PAGE_BAP_UX
589	oris	r13,r13,_PAGE_ACCESSED@h
590#else
591	li	r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
592#endif
593
5944:
595	FIND_PTE
596	andc.	r13,r13,r11		/* Check permission */
597
598#ifdef CONFIG_PTE_64BIT
599#ifdef CONFIG_SMP
600	subf	r13,r11,r12		/* create false data dep */
601	lwzx	r13,r11,r13		/* Get upper pte bits */
602#else
603	lwz	r13,0(r12)		/* Get upper pte bits */
604#endif
605#endif
606
607	bne	2f			/* Bail if permission mismatch */
608
609	/* Jump to common TLB load point */
610	b	finish_tlb_load
611
6122:
613	/* The bailout.  Restore registers to pre-exception conditions
614	 * and call the heavyweights to help us out.
615	 */
616	mfspr	r10, SPRN_SPRG_THREAD
617	lwz	r11, THREAD_NORMSAVE(3)(r10)
618	mtcr	r11
619	lwz	r13, THREAD_NORMSAVE(2)(r10)
620	lwz	r12, THREAD_NORMSAVE(1)(r10)
621	lwz	r11, THREAD_NORMSAVE(0)(r10)
622	mfspr	r10, SPRN_SPRG_RSCRATCH0
623	b	InstructionStorage
624
625/* Define SPE handlers for e500v2 */
626#ifdef CONFIG_SPE
627	/* SPE Unavailable */
628	START_EXCEPTION(SPEUnavailable)
629	NORMAL_EXCEPTION_PROLOG(0x2010, SPE_UNAVAIL)
630	beq	1f
631	bl	load_up_spe
632	b	fast_exception_return
6331:	prepare_transfer_to_handler
634	bl	KernelSPE
635	b	interrupt_return
636#elif defined(CONFIG_SPE_POSSIBLE)
637	EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, unknown_exception)
638#endif /* CONFIG_SPE_POSSIBLE */
639
640	/* SPE Floating Point Data */
641#ifdef CONFIG_SPE
642	START_EXCEPTION(SPEFloatingPointData)
643	NORMAL_EXCEPTION_PROLOG(0x2030, SPE_FP_DATA)
644	prepare_transfer_to_handler
645	bl	SPEFloatingPointException
646	REST_NVGPRS(r1)
647	b	interrupt_return
648
649	/* SPE Floating Point Round */
650	START_EXCEPTION(SPEFloatingPointRound)
651	NORMAL_EXCEPTION_PROLOG(0x2050, SPE_FP_ROUND)
652	prepare_transfer_to_handler
653	bl	SPEFloatingPointRoundException
654	REST_NVGPRS(r1)
655	b	interrupt_return
656#elif defined(CONFIG_SPE_POSSIBLE)
657	EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData, unknown_exception)
658	EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, unknown_exception)
659#endif /* CONFIG_SPE_POSSIBLE */
660
661
662	/* Performance Monitor */
663	EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \
664		  performance_monitor_exception)
665
666	EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception)
667
668	CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \
669			   CriticalDoorbell, unknown_exception)
670
671	/* Debug Interrupt */
672	DEBUG_DEBUG_EXCEPTION
673	DEBUG_CRIT_EXCEPTION
674
675	GUEST_DOORBELL_EXCEPTION
676
677	CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \
678			   unknown_exception)
679
680	/* Hypercall */
681	EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception)
682
683	/* Embedded Hypervisor Privilege */
684	EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception)
685
686interrupt_end:
687
688/*
689 * Local functions
690 */
691
692/*
693 * Both the instruction and data TLB miss get to this
694 * point to load the TLB.
695 *	r10 - tsize encoding (if HUGETLB_PAGE) or available to use
696 *	r11 - TLB (info from Linux PTE)
697 *	r12 - available to use
698 *	r13 - upper bits of PTE (if PTE_64BIT) or available to use
699 *	CR5 - results of addr >= PAGE_OFFSET
700 *	MAS0, MAS1 - loaded with proper value when we get here
701 *	MAS2, MAS3 - will need additional info from Linux PTE
702 *	Upon exit, we reload everything and RFI.
703 */
704finish_tlb_load:
705#ifdef CONFIG_HUGETLB_PAGE
706	cmpwi	6, r10, 0			/* check for huge page */
707	beq	6, finish_tlb_load_cont    	/* !huge */
708
709	/* Alas, we need more scratch registers for hugepages */
710	mfspr	r12, SPRN_SPRG_THREAD
711	stw	r14, THREAD_NORMSAVE(4)(r12)
712	stw	r15, THREAD_NORMSAVE(5)(r12)
713	stw	r16, THREAD_NORMSAVE(6)(r12)
714	stw	r17, THREAD_NORMSAVE(7)(r12)
715
716	/* Get the next_tlbcam_idx percpu var */
717#ifdef CONFIG_SMP
718	lwz	r15, TASK_CPU-THREAD(r12)
719	lis     r14, __per_cpu_offset@h
720	ori     r14, r14, __per_cpu_offset@l
721	rlwinm  r15, r15, 2, 0, 29
722	lwzx    r16, r14, r15
723#else
724	li	r16, 0
725#endif
726	lis     r17, next_tlbcam_idx@h
727	ori	r17, r17, next_tlbcam_idx@l
728	add	r17, r17, r16			/* r17 = *next_tlbcam_idx */
729	lwz     r15, 0(r17)			/* r15 = next_tlbcam_idx */
730
731	lis	r14, MAS0_TLBSEL(1)@h		/* select TLB1 (TLBCAM) */
732	rlwimi	r14, r15, 16, 4, 15		/* next_tlbcam_idx entry */
733	mtspr	SPRN_MAS0, r14
734
735	/* Extract TLB1CFG(NENTRY) */
736	mfspr	r16, SPRN_TLB1CFG
737	andi.	r16, r16, 0xfff
738
739	/* Update next_tlbcam_idx, wrapping when necessary */
740	addi	r15, r15, 1
741	cmpw	r15, r16
742	blt 	100f
743	lis	r14, tlbcam_index@h
744	ori	r14, r14, tlbcam_index@l
745	lwz	r15, 0(r14)
746100:	stw	r15, 0(r17)
747
748	/*
749	 * Calc MAS1_TSIZE from r10 (which has pshift encoded)
750	 * tlb_enc = (pshift - 10).
751	 */
752	subi	r15, r10, 10
753	mfspr	r16, SPRN_MAS1
754	rlwimi	r16, r15, 7, 20, 24
755	mtspr	SPRN_MAS1, r16
756
757	/* copy the pshift for use later */
758	mr	r14, r10
759
760	/* fall through */
761
762#endif /* CONFIG_HUGETLB_PAGE */
763
764	/*
765	 * We set execute, because we don't have the granularity to
766	 * properly set this at the page level (Linux problem).
767	 * Many of these bits are software only.  Bits we don't set
768	 * here we (properly should) assume have the appropriate value.
769	 */
770finish_tlb_load_cont:
771#ifdef CONFIG_PTE_64BIT
772	rlwinm	r12, r11, 32-2, 26, 31	/* Move in perm bits */
773	andi.	r10, r11, _PAGE_DIRTY
774	bne	1f
775	li	r10, MAS3_SW | MAS3_UW
776	andc	r12, r12, r10
7771:	rlwimi	r12, r13, 20, 0, 11	/* grab RPN[32:43] */
778	rlwimi	r12, r11, 20, 12, 19	/* grab RPN[44:51] */
7792:	mtspr	SPRN_MAS3, r12
780BEGIN_MMU_FTR_SECTION
781	srwi	r10, r13, 12		/* grab RPN[12:31] */
782	mtspr	SPRN_MAS7, r10
783END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
784#else
785	li	r10, (_PAGE_EXEC | _PAGE_PRESENT)
786	mr	r13, r11
787	rlwimi	r10, r11, 31, 29, 29	/* extract _PAGE_DIRTY into SW */
788	and	r12, r11, r10
789	andi.	r10, r11, _PAGE_USER	/* Test for _PAGE_USER */
790	slwi	r10, r12, 1
791	or	r10, r10, r12
792	rlwinm	r10, r10, 0, ~_PAGE_EXEC	/* Clear SX on user pages */
793	iseleq	r12, r12, r10
794	rlwimi	r13, r12, 0, 20, 31	/* Get RPN from PTE, merge w/ perms */
795	mtspr	SPRN_MAS3, r13
796#endif
797
798	mfspr	r12, SPRN_MAS2
799#ifdef CONFIG_PTE_64BIT
800	rlwimi	r12, r11, 32-19, 27, 31	/* extract WIMGE from pte */
801#else
802	rlwimi	r12, r11, 26, 27, 31	/* extract WIMGE from pte */
803#endif
804#ifdef CONFIG_HUGETLB_PAGE
805	beq	6, 3f			/* don't mask if page isn't huge */
806	li	r13, 1
807	slw	r13, r13, r14
808	subi	r13, r13, 1
809	rlwinm	r13, r13, 0, 0, 19	/* bottom bits used for WIMGE/etc */
810	andc	r12, r12, r13		/* mask off ea bits within the page */
811#endif
8123:	mtspr	SPRN_MAS2, r12
813
814tlb_write_entry:
815	tlbwe
816
817	/* Done...restore registers and get out of here.  */
818	mfspr	r10, SPRN_SPRG_THREAD
819#ifdef CONFIG_HUGETLB_PAGE
820	beq	6, 8f /* skip restore for 4k page faults */
821	lwz	r14, THREAD_NORMSAVE(4)(r10)
822	lwz	r15, THREAD_NORMSAVE(5)(r10)
823	lwz	r16, THREAD_NORMSAVE(6)(r10)
824	lwz	r17, THREAD_NORMSAVE(7)(r10)
825#endif
8268:	lwz	r11, THREAD_NORMSAVE(3)(r10)
827	mtcr	r11
828	lwz	r13, THREAD_NORMSAVE(2)(r10)
829	lwz	r12, THREAD_NORMSAVE(1)(r10)
830	lwz	r11, THREAD_NORMSAVE(0)(r10)
831	mfspr	r10, SPRN_SPRG_RSCRATCH0
832	rfi					/* Force context change */
833
834#ifdef CONFIG_SPE
835/* Note that the SPE support is closely modeled after the AltiVec
836 * support.  Changes to one are likely to be applicable to the
837 * other!  */
838_GLOBAL(load_up_spe)
839/*
840 * Disable SPE for the task which had SPE previously,
841 * and save its SPE registers in its thread_struct.
842 * Enables SPE for use in the kernel on return.
843 * On SMP we know the SPE units are free, since we give it up every
844 * switch.  -- Kumar
845 */
846	mfmsr	r5
847	oris	r5,r5,MSR_SPE@h
848	mtmsr	r5			/* enable use of SPE now */
849	isync
850	/* enable use of SPE after return */
851	oris	r9,r9,MSR_SPE@h
852	mfspr	r5,SPRN_SPRG_THREAD	/* current task's THREAD (phys) */
853	li	r4,1
854	li	r10,THREAD_ACC
855	stw	r4,THREAD_USED_SPE(r5)
856	evlddx	evr4,r10,r5
857	evmra	evr4,evr4
858	REST_32EVRS(0,r10,r5,THREAD_EVR0)
859	blr
860
861/*
862 * SPE unavailable trap from kernel - print a message, but let
863 * the task use SPE in the kernel until it returns to user mode.
864 */
865KernelSPE:
866	lwz	r3,_MSR(r1)
867	oris	r3,r3,MSR_SPE@h
868	stw	r3,_MSR(r1)	/* enable use of SPE after return */
869#ifdef CONFIG_PRINTK
870	lis	r3,87f@h
871	ori	r3,r3,87f@l
872	mr	r4,r2		/* current */
873	lwz	r5,_NIP(r1)
874	bl	_printk
875#endif
876	b	interrupt_return
877#ifdef CONFIG_PRINTK
87887:	.string	"SPE used in kernel  (task=%p, pc=%x)  \n"
879#endif
880	.align	4,0
881
882#endif /* CONFIG_SPE */
883
884/*
885 * Translate the effec addr in r3 to phys addr. The phys addr will be put
886 * into r3(higher 32bit) and r4(lower 32bit)
887 */
888get_phys_addr:
889	mfmsr	r8
890	mfspr	r9,SPRN_PID
891	rlwinm	r9,r9,16,0x3fff0000	/* turn PID into MAS6[SPID] */
892	rlwimi	r9,r8,28,0x00000001	/* turn MSR[DS] into MAS6[SAS] */
893	mtspr	SPRN_MAS6,r9
894
895	tlbsx	0,r3			/* must succeed */
896
897	mfspr	r8,SPRN_MAS1
898	mfspr	r12,SPRN_MAS3
899	rlwinm	r9,r8,25,0x1f		/* r9 = log2(page size) */
900	li	r10,1024
901	slw	r10,r10,r9		/* r10 = page size */
902	addi	r10,r10,-1
903	and	r11,r3,r10		/* r11 = page offset */
904	andc	r4,r12,r10		/* r4 = page base */
905	or	r4,r4,r11		/* r4 = devtree phys addr */
906#ifdef CONFIG_PHYS_64BIT
907	mfspr	r3,SPRN_MAS7
908#endif
909	blr
910
911/*
912 * Global functions
913 */
914
915#ifdef CONFIG_PPC_E500
916#ifndef CONFIG_PPC_E500MC
917/* Adjust or setup IVORs for e500v1/v2 */
918_GLOBAL(__setup_e500_ivors)
919	li	r3,DebugCrit@l
920	mtspr	SPRN_IVOR15,r3
921	li	r3,SPEUnavailable@l
922	mtspr	SPRN_IVOR32,r3
923	li	r3,SPEFloatingPointData@l
924	mtspr	SPRN_IVOR33,r3
925	li	r3,SPEFloatingPointRound@l
926	mtspr	SPRN_IVOR34,r3
927	li	r3,PerformanceMonitor@l
928	mtspr	SPRN_IVOR35,r3
929	sync
930	blr
931#else
932/* Adjust or setup IVORs for e500mc */
933_GLOBAL(__setup_e500mc_ivors)
934	li	r3,DebugDebug@l
935	mtspr	SPRN_IVOR15,r3
936	li	r3,PerformanceMonitor@l
937	mtspr	SPRN_IVOR35,r3
938	li	r3,Doorbell@l
939	mtspr	SPRN_IVOR36,r3
940	li	r3,CriticalDoorbell@l
941	mtspr	SPRN_IVOR37,r3
942	sync
943	blr
944
945/* setup ehv ivors for */
946_GLOBAL(__setup_ehv_ivors)
947	li	r3,GuestDoorbell@l
948	mtspr	SPRN_IVOR38,r3
949	li	r3,CriticalGuestDoorbell@l
950	mtspr	SPRN_IVOR39,r3
951	li	r3,Hypercall@l
952	mtspr	SPRN_IVOR40,r3
953	li	r3,Ehvpriv@l
954	mtspr	SPRN_IVOR41,r3
955	sync
956	blr
957#endif /* CONFIG_PPC_E500MC */
958#endif /* CONFIG_PPC_E500 */
959
960#ifdef CONFIG_SPE
961/*
962 * extern void __giveup_spe(struct task_struct *prev)
963 *
964 */
965_GLOBAL(__giveup_spe)
966	addi	r3,r3,THREAD		/* want THREAD of task */
967	lwz	r5,PT_REGS(r3)
968	cmpi	0,r5,0
969	SAVE_32EVRS(0, r4, r3, THREAD_EVR0)
970	evxor	evr6, evr6, evr6	/* clear out evr6 */
971	evmwumiaa evr6, evr6, evr6	/* evr6 <- ACC = 0 * 0 + ACC */
972	li	r4,THREAD_ACC
973	evstddx	evr6, r4, r3		/* save off accumulator */
974	beq	1f
975	lwz	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
976	lis	r3,MSR_SPE@h
977	andc	r4,r4,r3		/* disable SPE for previous task */
978	stw	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
9791:
980	blr
981#endif /* CONFIG_SPE */
982
983/*
984 * extern void abort(void)
985 *
986 * At present, this routine just applies a system reset.
987 */
988_GLOBAL(abort)
989	li	r13,0
990	mtspr	SPRN_DBCR0,r13		/* disable all debug events */
991	isync
992	mfmsr	r13
993	ori	r13,r13,MSR_DE@l	/* Enable Debug Events */
994	mtmsr	r13
995	isync
996	mfspr	r13,SPRN_DBCR0
997	lis	r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
998	mtspr	SPRN_DBCR0,r13
999	isync
1000
1001#ifdef CONFIG_SMP
1002/* When we get here, r24 needs to hold the CPU # */
1003	.globl __secondary_start
1004__secondary_start:
1005	LOAD_REG_ADDR_PIC(r3, tlbcam_index)
1006	lwz	r3,0(r3)
1007	mtctr	r3
1008	li	r26,0		/* r26 safe? */
1009
1010	bl	switch_to_as1
1011	mr	r27,r3		/* tlb entry */
1012	/* Load each CAM entry */
10131:	mr	r3,r26
1014	bl	loadcam_entry
1015	addi	r26,r26,1
1016	bdnz	1b
1017	mr	r3,r27		/* tlb entry */
1018	LOAD_REG_ADDR_PIC(r4, memstart_addr)
1019	lwz	r4,0(r4)
1020	mr	r5,r25		/* phys kernel start */
1021	rlwinm	r5,r5,0,~0x3ffffff	/* aligned 64M */
1022	subf	r4,r5,r4	/* memstart_addr - phys kernel start */
1023	lis	r7,KERNELBASE@h
1024	ori	r7,r7,KERNELBASE@l
1025	cmpw	r20,r7		/* if kernstart_virt_addr != KERNELBASE, randomized */
1026	beq	2f
1027	li	r4,0
10282:	li	r5,0		/* no device tree */
1029	li	r6,0		/* not boot cpu */
1030	bl	restore_to_as0
1031
1032
1033	lis	r3,__secondary_hold_acknowledge@h
1034	ori	r3,r3,__secondary_hold_acknowledge@l
1035	stw	r24,0(r3)
1036
1037	li	r3,0
1038	mr	r4,r24		/* Why? */
1039	bl	call_setup_cpu
1040
1041	/* get current's stack and current */
1042	lis	r2,secondary_current@ha
1043	lwz	r2,secondary_current@l(r2)
1044	lwz	r1,TASK_STACK(r2)
1045
1046	/* stack */
1047	addi	r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1048	li	r0,0
1049	stw	r0,0(r1)
1050
1051	/* ptr to current thread */
1052	addi	r4,r2,THREAD	/* address of our thread_struct */
1053	mtspr	SPRN_SPRG_THREAD,r4
1054
1055	/* Setup the defaults for TLB entries */
1056	li	r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
1057	mtspr	SPRN_MAS4,r4
1058
1059	/* Jump to start_secondary */
1060	lis	r4,MSR_KERNEL@h
1061	ori	r4,r4,MSR_KERNEL@l
1062	lis	r3,start_secondary@h
1063	ori	r3,r3,start_secondary@l
1064	mtspr	SPRN_SRR0,r3
1065	mtspr	SPRN_SRR1,r4
1066	sync
1067	rfi
1068	sync
1069
1070	.globl __secondary_hold_acknowledge
1071__secondary_hold_acknowledge:
1072	.long	-1
1073#endif
1074
1075/*
1076 * Create a 64M tlb by address and entry
1077 * r3 - entry
1078 * r4 - virtual address
1079 * r5/r6 - physical address
1080 */
1081_GLOBAL(create_kaslr_tlb_entry)
1082	lis     r7,0x1000               /* Set MAS0(TLBSEL) = 1 */
1083	rlwimi  r7,r3,16,4,15           /* Setup MAS0 = TLBSEL | ESEL(r6) */
1084	mtspr   SPRN_MAS0,r7            /* Write MAS0 */
1085
1086	lis     r3,(MAS1_VALID|MAS1_IPROT)@h
1087	ori     r3,r3,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
1088	mtspr   SPRN_MAS1,r3            /* Write MAS1 */
1089
1090	lis     r3,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@h
1091	ori     r3,r3,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@l
1092	and     r3,r3,r4
1093	ori	r3,r3,MAS2_M_IF_NEEDED@l
1094	mtspr   SPRN_MAS2,r3            /* Write MAS2(EPN) */
1095
1096#ifdef CONFIG_PHYS_64BIT
1097	ori     r8,r6,(MAS3_SW|MAS3_SR|MAS3_SX)
1098	mtspr   SPRN_MAS3,r8            /* Write MAS3(RPN) */
1099	mtspr	SPRN_MAS7,r5
1100#else
1101	ori     r8,r5,(MAS3_SW|MAS3_SR|MAS3_SX)
1102	mtspr   SPRN_MAS3,r8            /* Write MAS3(RPN) */
1103#endif
1104
1105	tlbwe                           /* Write TLB */
1106	isync
1107	sync
1108	blr
1109
1110/*
1111 * Return to the start of the relocated kernel and run again
1112 * r3 - virtual address of fdt
1113 * r4 - entry of the kernel
1114 */
1115_GLOBAL(reloc_kernel_entry)
1116	mfmsr	r7
1117	rlwinm	r7, r7, 0, ~(MSR_IS | MSR_DS)
1118
1119	mtspr	SPRN_SRR0,r4
1120	mtspr	SPRN_SRR1,r7
1121	rfi
1122
1123/*
1124 * Create a tlb entry with the same effective and physical address as
1125 * the tlb entry used by the current running code. But set the TS to 1.
1126 * Then switch to the address space 1. It will return with the r3 set to
1127 * the ESEL of the new created tlb.
1128 */
1129_GLOBAL(switch_to_as1)
1130	mflr	r5
1131
1132	/* Find a entry not used */
1133	mfspr	r3,SPRN_TLB1CFG
1134	andi.	r3,r3,0xfff
1135	mfspr	r4,SPRN_PID
1136	rlwinm	r4,r4,16,0x3fff0000	/* turn PID into MAS6[SPID] */
1137	mtspr	SPRN_MAS6,r4
11381:	lis	r4,0x1000		/* Set MAS0(TLBSEL) = 1 */
1139	addi	r3,r3,-1
1140	rlwimi	r4,r3,16,4,15		/* Setup MAS0 = TLBSEL | ESEL(r3) */
1141	mtspr	SPRN_MAS0,r4
1142	tlbre
1143	mfspr	r4,SPRN_MAS1
1144	andis.	r4,r4,MAS1_VALID@h
1145	bne	1b
1146
1147	/* Get the tlb entry used by the current running code */
1148	bcl	20,31,$+4
11490:	mflr	r4
1150	tlbsx	0,r4
1151
1152	mfspr	r4,SPRN_MAS1
1153	ori	r4,r4,MAS1_TS		/* Set the TS = 1 */
1154	mtspr	SPRN_MAS1,r4
1155
1156	mfspr	r4,SPRN_MAS0
1157	rlwinm	r4,r4,0,~MAS0_ESEL_MASK
1158	rlwimi	r4,r3,16,4,15		/* Setup MAS0 = TLBSEL | ESEL(r3) */
1159	mtspr	SPRN_MAS0,r4
1160	tlbwe
1161	isync
1162	sync
1163
1164	mfmsr	r4
1165	ori	r4,r4,MSR_IS | MSR_DS
1166	mtspr	SPRN_SRR0,r5
1167	mtspr	SPRN_SRR1,r4
1168	sync
1169	rfi
1170
1171/*
1172 * Restore to the address space 0 and also invalidate the tlb entry created
1173 * by switch_to_as1.
1174 * r3 - the tlb entry which should be invalidated
1175 * r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0)
1176 * r5 - device tree virtual address. If r4 is 0, r5 is ignored.
1177 * r6 - boot cpu
1178*/
1179_GLOBAL(restore_to_as0)
1180	mflr	r0
1181
1182	bcl	20,31,$+4
11830:	mflr	r9
1184	addi	r9,r9,1f - 0b
1185
1186	/*
1187	 * We may map the PAGE_OFFSET in AS0 to a different physical address,
1188	 * so we need calculate the right jump and device tree address based
1189	 * on the offset passed by r4.
1190	 */
1191	add	r9,r9,r4
1192	add	r5,r5,r4
1193	add	r0,r0,r4
1194
11952:	mfmsr	r7
1196	li	r8,(MSR_IS | MSR_DS)
1197	andc	r7,r7,r8
1198
1199	mtspr	SPRN_SRR0,r9
1200	mtspr	SPRN_SRR1,r7
1201	sync
1202	rfi
1203
1204	/* Invalidate the temporary tlb entry for AS1 */
12051:	lis	r9,0x1000		/* Set MAS0(TLBSEL) = 1 */
1206	rlwimi	r9,r3,16,4,15		/* Setup MAS0 = TLBSEL | ESEL(r3) */
1207	mtspr	SPRN_MAS0,r9
1208	tlbre
1209	mfspr	r9,SPRN_MAS1
1210	rlwinm	r9,r9,0,2,31		/* Clear MAS1 Valid and IPPROT */
1211	mtspr	SPRN_MAS1,r9
1212	tlbwe
1213	isync
1214
1215	cmpwi	r4,0
1216	cmpwi	cr1,r6,0
1217	cror	eq,4*cr1+eq,eq
1218	bne	3f			/* offset != 0 && is_boot_cpu */
1219	mtlr	r0
1220	blr
1221
1222	/*
1223	 * The PAGE_OFFSET will map to a different physical address,
1224	 * jump to _start to do another relocation again.
1225	*/
12263:	mr	r3,r5
1227	bl	_start
1228