1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Port for PPC64 David Engebretsen, IBM Corp. 4 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 5 * 6 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 7 * Rework, based on alpha PCI code. 8 */ 9 10 #undef DEBUG 11 12 #include <linux/kernel.h> 13 #include <linux/pci.h> 14 #include <linux/string.h> 15 #include <linux/init.h> 16 #include <linux/export.h> 17 #include <linux/mm.h> 18 #include <linux/list.h> 19 #include <linux/syscalls.h> 20 #include <linux/irq.h> 21 #include <linux/vmalloc.h> 22 23 #include <asm/processor.h> 24 #include <asm/io.h> 25 #include <asm/prom.h> 26 #include <asm/pci-bridge.h> 27 #include <asm/byteorder.h> 28 #include <asm/machdep.h> 29 #include <asm/ppc-pci.h> 30 31 /* pci_io_base -- the base address from which io bars are offsets. 32 * This is the lowest I/O base address (so bar values are always positive), 33 * and it *must* be the start of ISA space if an ISA bus exists because 34 * ISA drivers use hard coded offsets. If no ISA bus exists nothing 35 * is mapped on the first 64K of IO space 36 */ 37 unsigned long pci_io_base; 38 EXPORT_SYMBOL(pci_io_base); 39 40 static int __init pcibios_init(void) 41 { 42 struct pci_controller *hose, *tmp; 43 44 printk(KERN_INFO "PCI: Probing PCI hardware\n"); 45 46 /* For now, override phys_mem_access_prot. If we need it,g 47 * later, we may move that initialization to each ppc_md 48 */ 49 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot; 50 51 /* On ppc64, we always enable PCI domains and we keep domain 0 52 * backward compatible in /proc for video cards 53 */ 54 pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0); 55 56 /* Scan all of the recorded PCI controllers. */ 57 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 58 pcibios_scan_phb(hose); 59 pci_bus_add_devices(hose->bus); 60 } 61 62 /* Call common code to handle resource allocation */ 63 pcibios_resource_survey(); 64 65 printk(KERN_DEBUG "PCI: Probing PCI hardware done\n"); 66 67 return 0; 68 } 69 70 subsys_initcall(pcibios_init); 71 72 int pcibios_unmap_io_space(struct pci_bus *bus) 73 { 74 struct pci_controller *hose; 75 76 WARN_ON(bus == NULL); 77 78 /* If this is not a PHB, we only flush the hash table over 79 * the area mapped by this bridge. We don't play with the PTE 80 * mappings since we might have to deal with sub-page alignments 81 * so flushing the hash table is the only sane way to make sure 82 * that no hash entries are covering that removed bridge area 83 * while still allowing other busses overlapping those pages 84 * 85 * Note: If we ever support P2P hotplug on Book3E, we'll have 86 * to do an appropriate TLB flush here too 87 */ 88 if (bus->self) { 89 #ifdef CONFIG_PPC_BOOK3S_64 90 struct resource *res = bus->resource[0]; 91 #endif 92 93 pr_debug("IO unmapping for PCI-PCI bridge %s\n", 94 pci_name(bus->self)); 95 96 #ifdef CONFIG_PPC_BOOK3S_64 97 __flush_hash_table_range(&init_mm, res->start + _IO_BASE, 98 res->end + _IO_BASE + 1); 99 #endif 100 return 0; 101 } 102 103 /* Get the host bridge */ 104 hose = pci_bus_to_host(bus); 105 106 /* Check if we have IOs allocated */ 107 if (hose->io_base_alloc == NULL) 108 return 0; 109 110 pr_debug("IO unmapping for PHB %pOF\n", hose->dn); 111 pr_debug(" alloc=0x%p\n", hose->io_base_alloc); 112 113 /* This is a PHB, we fully unmap the IO area */ 114 vunmap(hose->io_base_alloc); 115 116 return 0; 117 } 118 EXPORT_SYMBOL_GPL(pcibios_unmap_io_space); 119 120 static int pcibios_map_phb_io_space(struct pci_controller *hose) 121 { 122 struct vm_struct *area; 123 unsigned long phys_page; 124 unsigned long size_page; 125 unsigned long io_virt_offset; 126 127 phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE); 128 size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE); 129 130 /* Make sure IO area address is clear */ 131 hose->io_base_alloc = NULL; 132 133 /* If there's no IO to map on that bus, get away too */ 134 if (hose->pci_io_size == 0 || hose->io_base_phys == 0) 135 return 0; 136 137 /* Let's allocate some IO space for that guy. We don't pass 138 * VM_IOREMAP because we don't care about alignment tricks that 139 * the core does in that case. Maybe we should due to stupid card 140 * with incomplete address decoding but I'd rather not deal with 141 * those outside of the reserved 64K legacy region. 142 */ 143 area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END); 144 if (area == NULL) 145 return -ENOMEM; 146 hose->io_base_alloc = area->addr; 147 hose->io_base_virt = (void __iomem *)(area->addr + 148 hose->io_base_phys - phys_page); 149 150 pr_debug("IO mapping for PHB %pOF\n", hose->dn); 151 pr_debug(" phys=0x%016llx, virt=0x%p (alloc=0x%p)\n", 152 hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc); 153 pr_debug(" size=0x%016llx (alloc=0x%016lx)\n", 154 hose->pci_io_size, size_page); 155 156 /* Establish the mapping */ 157 if (__ioremap_at(phys_page, area->addr, size_page, 158 pgprot_noncached(PAGE_KERNEL)) == NULL) 159 return -ENOMEM; 160 161 /* Fixup hose IO resource */ 162 io_virt_offset = pcibios_io_space_offset(hose); 163 hose->io_resource.start += io_virt_offset; 164 hose->io_resource.end += io_virt_offset; 165 166 pr_debug(" hose->io_resource=%pR\n", &hose->io_resource); 167 168 return 0; 169 } 170 171 int pcibios_map_io_space(struct pci_bus *bus) 172 { 173 WARN_ON(bus == NULL); 174 175 /* If this not a PHB, nothing to do, page tables still exist and 176 * thus HPTEs will be faulted in when needed 177 */ 178 if (bus->self) { 179 pr_debug("IO mapping for PCI-PCI bridge %s\n", 180 pci_name(bus->self)); 181 pr_debug(" virt=0x%016llx...0x%016llx\n", 182 bus->resource[0]->start + _IO_BASE, 183 bus->resource[0]->end + _IO_BASE); 184 return 0; 185 } 186 187 return pcibios_map_phb_io_space(pci_bus_to_host(bus)); 188 } 189 EXPORT_SYMBOL_GPL(pcibios_map_io_space); 190 191 void pcibios_setup_phb_io_space(struct pci_controller *hose) 192 { 193 pcibios_map_phb_io_space(hose); 194 } 195 196 #define IOBASE_BRIDGE_NUMBER 0 197 #define IOBASE_MEMORY 1 198 #define IOBASE_IO 2 199 #define IOBASE_ISA_IO 3 200 #define IOBASE_ISA_MEM 4 201 202 SYSCALL_DEFINE3(pciconfig_iobase, long, which, unsigned long, in_bus, 203 unsigned long, in_devfn) 204 { 205 struct pci_controller* hose; 206 struct pci_bus *tmp_bus, *bus = NULL; 207 struct device_node *hose_node; 208 209 /* Argh ! Please forgive me for that hack, but that's the 210 * simplest way to get existing XFree to not lockup on some 211 * G5 machines... So when something asks for bus 0 io base 212 * (bus 0 is HT root), we return the AGP one instead. 213 */ 214 if (in_bus == 0 && of_machine_is_compatible("MacRISC4")) { 215 struct device_node *agp; 216 217 agp = of_find_compatible_node(NULL, NULL, "u3-agp"); 218 if (agp) 219 in_bus = 0xf0; 220 of_node_put(agp); 221 } 222 223 /* That syscall isn't quite compatible with PCI domains, but it's 224 * used on pre-domains setup. We return the first match 225 */ 226 227 list_for_each_entry(tmp_bus, &pci_root_buses, node) { 228 if (in_bus >= tmp_bus->number && 229 in_bus <= tmp_bus->busn_res.end) { 230 bus = tmp_bus; 231 break; 232 } 233 } 234 if (bus == NULL || bus->dev.of_node == NULL) 235 return -ENODEV; 236 237 hose_node = bus->dev.of_node; 238 hose = PCI_DN(hose_node)->phb; 239 240 switch (which) { 241 case IOBASE_BRIDGE_NUMBER: 242 return (long)hose->first_busno; 243 case IOBASE_MEMORY: 244 return (long)hose->mem_offset[0]; 245 case IOBASE_IO: 246 return (long)hose->io_base_phys; 247 case IOBASE_ISA_IO: 248 return (long)isa_io_base; 249 case IOBASE_ISA_MEM: 250 return -EINVAL; 251 } 252 253 return -EOPNOTSUPP; 254 } 255 256 #ifdef CONFIG_NUMA 257 int pcibus_to_node(struct pci_bus *bus) 258 { 259 struct pci_controller *phb = pci_bus_to_host(bus); 260 return phb->node; 261 } 262 EXPORT_SYMBOL(pcibus_to_node); 263 #endif 264