1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Helper routines to scan the device tree for PCI devices and busses 4 * 5 * Migrated out of PowerPC architecture pci_64.c file by Grant Likely 6 * <grant.likely@secretlab.ca> so that these routines are available for 7 * 32 bit also. 8 * 9 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 10 * Rework, based on alpha PCI code. 11 * Copyright (c) 2009 Secret Lab Technologies Ltd. 12 */ 13 14 #include <linux/pci.h> 15 #include <linux/export.h> 16 #include <asm/pci-bridge.h> 17 #include <asm/prom.h> 18 19 /** 20 * get_int_prop - Decode a u32 from a device tree property 21 */ 22 static u32 get_int_prop(struct device_node *np, const char *name, u32 def) 23 { 24 const __be32 *prop; 25 int len; 26 27 prop = of_get_property(np, name, &len); 28 if (prop && len >= 4) 29 return of_read_number(prop, 1); 30 return def; 31 } 32 33 /** 34 * pci_parse_of_flags - Parse the flags cell of a device tree PCI address 35 * @addr0: value of 1st cell of a device tree PCI address. 36 * @bridge: Set this flag if the address is from a bridge 'ranges' property 37 */ 38 unsigned int pci_parse_of_flags(u32 addr0, int bridge) 39 { 40 unsigned int flags = 0; 41 42 if (addr0 & 0x02000000) { 43 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY; 44 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64; 45 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M; 46 if (addr0 & 0x40000000) 47 flags |= IORESOURCE_PREFETCH 48 | PCI_BASE_ADDRESS_MEM_PREFETCH; 49 /* Note: We don't know whether the ROM has been left enabled 50 * by the firmware or not. We mark it as disabled (ie, we do 51 * not set the IORESOURCE_ROM_ENABLE flag) for now rather than 52 * do a config space read, it will be force-enabled if needed 53 */ 54 if (!bridge && (addr0 & 0xff) == 0x30) 55 flags |= IORESOURCE_READONLY; 56 } else if (addr0 & 0x01000000) 57 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; 58 if (flags) 59 flags |= IORESOURCE_SIZEALIGN; 60 return flags; 61 } 62 63 /** 64 * of_pci_parse_addrs - Parse PCI addresses assigned in the device tree node 65 * @node: device tree node for the PCI device 66 * @dev: pci_dev structure for the device 67 * 68 * This function parses the 'assigned-addresses' property of a PCI devices' 69 * device tree node and writes them into the associated pci_dev structure. 70 */ 71 static void of_pci_parse_addrs(struct device_node *node, struct pci_dev *dev) 72 { 73 u64 base, size; 74 unsigned int flags; 75 struct pci_bus_region region; 76 struct resource *res; 77 const __be32 *addrs; 78 u32 i; 79 int proplen; 80 81 addrs = of_get_property(node, "assigned-addresses", &proplen); 82 if (!addrs) 83 return; 84 pr_debug(" parse addresses (%d bytes) @ %p\n", proplen, addrs); 85 for (; proplen >= 20; proplen -= 20, addrs += 5) { 86 flags = pci_parse_of_flags(of_read_number(addrs, 1), 0); 87 if (!flags) 88 continue; 89 base = of_read_number(&addrs[1], 2); 90 size = of_read_number(&addrs[3], 2); 91 if (!size) 92 continue; 93 i = of_read_number(addrs, 1) & 0xff; 94 pr_debug(" base: %llx, size: %llx, i: %x\n", 95 (unsigned long long)base, 96 (unsigned long long)size, i); 97 98 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) { 99 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2]; 100 } else if (i == dev->rom_base_reg) { 101 res = &dev->resource[PCI_ROM_RESOURCE]; 102 flags |= IORESOURCE_READONLY; 103 } else { 104 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i); 105 continue; 106 } 107 res->flags = flags; 108 res->name = pci_name(dev); 109 region.start = base; 110 region.end = base + size - 1; 111 pcibios_bus_to_resource(dev->bus, res, ®ion); 112 } 113 } 114 115 /** 116 * of_create_pci_dev - Given a device tree node on a pci bus, create a pci_dev 117 * @node: device tree node pointer 118 * @bus: bus the device is sitting on 119 * @devfn: PCI function number, extracted from device tree by caller. 120 */ 121 struct pci_dev *of_create_pci_dev(struct device_node *node, 122 struct pci_bus *bus, int devfn) 123 { 124 struct pci_dev *dev; 125 126 dev = pci_alloc_dev(bus); 127 if (!dev) 128 return NULL; 129 130 pr_debug(" create device, devfn: %x, type: %s\n", devfn, 131 of_node_get_device_type(node)); 132 133 dev->dev.of_node = of_node_get(node); 134 dev->dev.parent = bus->bridge; 135 dev->dev.bus = &pci_bus_type; 136 dev->devfn = devfn; 137 dev->multifunction = 0; /* maybe a lie? */ 138 dev->needs_freset = 0; /* pcie fundamental reset required */ 139 set_pcie_port_type(dev); 140 141 pci_dev_assign_slot(dev); 142 dev->vendor = get_int_prop(node, "vendor-id", 0xffff); 143 dev->device = get_int_prop(node, "device-id", 0xffff); 144 dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0); 145 dev->subsystem_device = get_int_prop(node, "subsystem-id", 0); 146 147 dev->cfg_size = pci_cfg_space_size(dev); 148 149 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus), 150 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); 151 dev->class = get_int_prop(node, "class-code", 0); 152 dev->revision = get_int_prop(node, "revision-id", 0); 153 154 pr_debug(" class: 0x%x\n", dev->class); 155 pr_debug(" revision: 0x%x\n", dev->revision); 156 157 dev->current_state = PCI_UNKNOWN; /* unknown power state */ 158 dev->error_state = pci_channel_io_normal; 159 dev->dma_mask = 0xffffffff; 160 161 /* Early fixups, before probing the BARs */ 162 pci_fixup_device(pci_fixup_early, dev); 163 164 if (of_node_is_type(node, "pci") || of_node_is_type(node, "pciex")) { 165 /* a PCI-PCI bridge */ 166 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; 167 dev->rom_base_reg = PCI_ROM_ADDRESS1; 168 set_pcie_hotplug_bridge(dev); 169 } else if (of_node_is_type(node, "cardbus")) { 170 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS; 171 } else { 172 dev->hdr_type = PCI_HEADER_TYPE_NORMAL; 173 dev->rom_base_reg = PCI_ROM_ADDRESS; 174 /* Maybe do a default OF mapping here */ 175 dev->irq = 0; 176 } 177 178 of_pci_parse_addrs(node, dev); 179 180 pr_debug(" adding to system ...\n"); 181 182 pci_device_add(dev, bus); 183 184 return dev; 185 } 186 EXPORT_SYMBOL(of_create_pci_dev); 187 188 /** 189 * of_scan_pci_bridge - Set up a PCI bridge and scan for child nodes 190 * @dev: pci_dev structure for the bridge 191 * 192 * of_scan_bus() calls this routine for each PCI bridge that it finds, and 193 * this routine in turn call of_scan_bus() recusively to scan for more child 194 * devices. 195 */ 196 void of_scan_pci_bridge(struct pci_dev *dev) 197 { 198 struct device_node *node = dev->dev.of_node; 199 struct pci_bus *bus; 200 struct pci_controller *phb; 201 const __be32 *busrange, *ranges; 202 int len, i, mode; 203 struct pci_bus_region region; 204 struct resource *res; 205 unsigned int flags; 206 u64 size; 207 208 pr_debug("of_scan_pci_bridge(%pOF)\n", node); 209 210 /* parse bus-range property */ 211 busrange = of_get_property(node, "bus-range", &len); 212 if (busrange == NULL || len != 8) { 213 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %pOF\n", 214 node); 215 return; 216 } 217 ranges = of_get_property(node, "ranges", &len); 218 if (ranges == NULL) { 219 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %pOF\n", 220 node); 221 return; 222 } 223 224 bus = pci_find_bus(pci_domain_nr(dev->bus), 225 of_read_number(busrange, 1)); 226 if (!bus) { 227 bus = pci_add_new_bus(dev->bus, dev, 228 of_read_number(busrange, 1)); 229 if (!bus) { 230 printk(KERN_ERR "Failed to create pci bus for %pOF\n", 231 node); 232 return; 233 } 234 } 235 236 bus->primary = dev->bus->number; 237 pci_bus_insert_busn_res(bus, of_read_number(busrange, 1), 238 of_read_number(busrange+1, 1)); 239 bus->bridge_ctl = 0; 240 241 /* parse ranges property */ 242 /* PCI #address-cells == 3 and #size-cells == 2 always */ 243 res = &dev->resource[PCI_BRIDGE_RESOURCES]; 244 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) { 245 res->flags = 0; 246 bus->resource[i] = res; 247 ++res; 248 } 249 i = 1; 250 for (; len >= 32; len -= 32, ranges += 8) { 251 flags = pci_parse_of_flags(of_read_number(ranges, 1), 1); 252 size = of_read_number(&ranges[6], 2); 253 if (flags == 0 || size == 0) 254 continue; 255 if (flags & IORESOURCE_IO) { 256 res = bus->resource[0]; 257 if (res->flags) { 258 printk(KERN_ERR "PCI: ignoring extra I/O range" 259 " for bridge %pOF\n", node); 260 continue; 261 } 262 } else { 263 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) { 264 printk(KERN_ERR "PCI: too many memory ranges" 265 " for bridge %pOF\n", node); 266 continue; 267 } 268 res = bus->resource[i]; 269 ++i; 270 } 271 res->flags = flags; 272 region.start = of_read_number(&ranges[1], 2); 273 region.end = region.start + size - 1; 274 pcibios_bus_to_resource(dev->bus, res, ®ion); 275 } 276 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), 277 bus->number); 278 pr_debug(" bus name: %s\n", bus->name); 279 280 phb = pci_bus_to_host(bus); 281 282 mode = PCI_PROBE_NORMAL; 283 if (phb->controller_ops.probe_mode) 284 mode = phb->controller_ops.probe_mode(bus); 285 pr_debug(" probe mode: %d\n", mode); 286 287 if (mode == PCI_PROBE_DEVTREE) 288 of_scan_bus(node, bus); 289 else if (mode == PCI_PROBE_NORMAL) 290 pci_scan_child_bus(bus); 291 } 292 EXPORT_SYMBOL(of_scan_pci_bridge); 293 294 static struct pci_dev *of_scan_pci_dev(struct pci_bus *bus, 295 struct device_node *dn) 296 { 297 struct pci_dev *dev = NULL; 298 const __be32 *reg; 299 int reglen, devfn; 300 #ifdef CONFIG_EEH 301 struct eeh_dev *edev = pdn_to_eeh_dev(PCI_DN(dn)); 302 #endif 303 304 pr_debug(" * %pOF\n", dn); 305 if (!of_device_is_available(dn)) 306 return NULL; 307 308 reg = of_get_property(dn, "reg", ®len); 309 if (reg == NULL || reglen < 20) 310 return NULL; 311 devfn = (of_read_number(reg, 1) >> 8) & 0xff; 312 313 /* Check if the PCI device is already there */ 314 dev = pci_get_slot(bus, devfn); 315 if (dev) { 316 pci_dev_put(dev); 317 return dev; 318 } 319 320 /* Device removed permanently ? */ 321 #ifdef CONFIG_EEH 322 if (edev && (edev->mode & EEH_DEV_REMOVED)) 323 return NULL; 324 #endif 325 326 /* create a new pci_dev for this device */ 327 dev = of_create_pci_dev(dn, bus, devfn); 328 if (!dev) 329 return NULL; 330 331 pr_debug(" dev header type: %x\n", dev->hdr_type); 332 return dev; 333 } 334 335 /** 336 * __of_scan_bus - given a PCI bus node, setup bus and scan for child devices 337 * @node: device tree node for the PCI bus 338 * @bus: pci_bus structure for the PCI bus 339 * @rescan_existing: Flag indicating bus has already been set up 340 */ 341 static void __of_scan_bus(struct device_node *node, struct pci_bus *bus, 342 int rescan_existing) 343 { 344 struct device_node *child; 345 struct pci_dev *dev; 346 347 pr_debug("of_scan_bus(%pOF) bus no %d...\n", 348 node, bus->number); 349 350 /* Scan direct children */ 351 for_each_child_of_node(node, child) { 352 dev = of_scan_pci_dev(bus, child); 353 if (!dev) 354 continue; 355 pr_debug(" dev header type: %x\n", dev->hdr_type); 356 } 357 358 /* Apply all fixups necessary. We don't fixup the bus "self" 359 * for an existing bridge that is being rescanned 360 */ 361 if (!rescan_existing) 362 pcibios_setup_bus_self(bus); 363 pcibios_setup_bus_devices(bus); 364 365 /* Now scan child busses */ 366 for_each_pci_bridge(dev, bus) 367 of_scan_pci_bridge(dev); 368 } 369 370 /** 371 * of_scan_bus - given a PCI bus node, setup bus and scan for child devices 372 * @node: device tree node for the PCI bus 373 * @bus: pci_bus structure for the PCI bus 374 */ 375 void of_scan_bus(struct device_node *node, struct pci_bus *bus) 376 { 377 __of_scan_bus(node, bus, 0); 378 } 379 EXPORT_SYMBOL_GPL(of_scan_bus); 380 381 /** 382 * of_rescan_bus - given a PCI bus node, scan for child devices 383 * @node: device tree node for the PCI bus 384 * @bus: pci_bus structure for the PCI bus 385 * 386 * Same as of_scan_bus, but for a pci_bus structure that has already been 387 * setup. 388 */ 389 void of_rescan_bus(struct device_node *node, struct pci_bus *bus) 390 { 391 __of_scan_bus(node, bus, 1); 392 } 393 EXPORT_SYMBOL_GPL(of_rescan_bus); 394 395