1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * Common boot and setup code. 5 * 6 * Copyright (C) 2001 PPC64 Team, IBM Corp 7 */ 8 9 #include <linux/export.h> 10 #include <linux/string.h> 11 #include <linux/sched.h> 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <linux/reboot.h> 15 #include <linux/delay.h> 16 #include <linux/initrd.h> 17 #include <linux/seq_file.h> 18 #include <linux/ioport.h> 19 #include <linux/console.h> 20 #include <linux/utsname.h> 21 #include <linux/tty.h> 22 #include <linux/root_dev.h> 23 #include <linux/notifier.h> 24 #include <linux/cpu.h> 25 #include <linux/unistd.h> 26 #include <linux/serial.h> 27 #include <linux/serial_8250.h> 28 #include <linux/memblock.h> 29 #include <linux/pci.h> 30 #include <linux/lockdep.h> 31 #include <linux/memory.h> 32 #include <linux/nmi.h> 33 34 #include <asm/debugfs.h> 35 #include <asm/io.h> 36 #include <asm/kdump.h> 37 #include <asm/prom.h> 38 #include <asm/processor.h> 39 #include <asm/pgtable.h> 40 #include <asm/smp.h> 41 #include <asm/elf.h> 42 #include <asm/machdep.h> 43 #include <asm/paca.h> 44 #include <asm/time.h> 45 #include <asm/cputable.h> 46 #include <asm/dt_cpu_ftrs.h> 47 #include <asm/sections.h> 48 #include <asm/btext.h> 49 #include <asm/nvram.h> 50 #include <asm/setup.h> 51 #include <asm/rtas.h> 52 #include <asm/iommu.h> 53 #include <asm/serial.h> 54 #include <asm/cache.h> 55 #include <asm/page.h> 56 #include <asm/mmu.h> 57 #include <asm/firmware.h> 58 #include <asm/xmon.h> 59 #include <asm/udbg.h> 60 #include <asm/kexec.h> 61 #include <asm/code-patching.h> 62 #include <asm/livepatch.h> 63 #include <asm/opal.h> 64 #include <asm/cputhreads.h> 65 #include <asm/hw_irq.h> 66 #include <asm/feature-fixups.h> 67 #include <asm/kup.h> 68 #include <asm/early_ioremap.h> 69 70 #include "setup.h" 71 72 int spinning_secondaries; 73 u64 ppc64_pft_size; 74 75 struct ppc64_caches ppc64_caches = { 76 .l1d = { 77 .block_size = 0x40, 78 .log_block_size = 6, 79 }, 80 .l1i = { 81 .block_size = 0x40, 82 .log_block_size = 6 83 }, 84 }; 85 EXPORT_SYMBOL_GPL(ppc64_caches); 86 87 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP) 88 void __init setup_tlb_core_data(void) 89 { 90 int cpu; 91 92 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0); 93 94 for_each_possible_cpu(cpu) { 95 int first = cpu_first_thread_sibling(cpu); 96 97 /* 98 * If we boot via kdump on a non-primary thread, 99 * make sure we point at the thread that actually 100 * set up this TLB. 101 */ 102 if (cpu_first_thread_sibling(boot_cpuid) == first) 103 first = boot_cpuid; 104 105 paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd; 106 107 /* 108 * If we have threads, we need either tlbsrx. 109 * or e6500 tablewalk mode, or else TLB handlers 110 * will be racy and could produce duplicate entries. 111 * Should we panic instead? 112 */ 113 WARN_ONCE(smt_enabled_at_boot >= 2 && 114 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) && 115 book3e_htw_mode != PPC_HTW_E6500, 116 "%s: unsupported MMU configuration\n", __func__); 117 } 118 } 119 #endif 120 121 #ifdef CONFIG_SMP 122 123 static char *smt_enabled_cmdline; 124 125 /* Look for ibm,smt-enabled OF option */ 126 void __init check_smt_enabled(void) 127 { 128 struct device_node *dn; 129 const char *smt_option; 130 131 /* Default to enabling all threads */ 132 smt_enabled_at_boot = threads_per_core; 133 134 /* Allow the command line to overrule the OF option */ 135 if (smt_enabled_cmdline) { 136 if (!strcmp(smt_enabled_cmdline, "on")) 137 smt_enabled_at_boot = threads_per_core; 138 else if (!strcmp(smt_enabled_cmdline, "off")) 139 smt_enabled_at_boot = 0; 140 else { 141 int smt; 142 int rc; 143 144 rc = kstrtoint(smt_enabled_cmdline, 10, &smt); 145 if (!rc) 146 smt_enabled_at_boot = 147 min(threads_per_core, smt); 148 } 149 } else { 150 dn = of_find_node_by_path("/options"); 151 if (dn) { 152 smt_option = of_get_property(dn, "ibm,smt-enabled", 153 NULL); 154 155 if (smt_option) { 156 if (!strcmp(smt_option, "on")) 157 smt_enabled_at_boot = threads_per_core; 158 else if (!strcmp(smt_option, "off")) 159 smt_enabled_at_boot = 0; 160 } 161 162 of_node_put(dn); 163 } 164 } 165 } 166 167 /* Look for smt-enabled= cmdline option */ 168 static int __init early_smt_enabled(char *p) 169 { 170 smt_enabled_cmdline = p; 171 return 0; 172 } 173 early_param("smt-enabled", early_smt_enabled); 174 175 #endif /* CONFIG_SMP */ 176 177 /** Fix up paca fields required for the boot cpu */ 178 static void __init fixup_boot_paca(void) 179 { 180 /* The boot cpu is started */ 181 get_paca()->cpu_start = 1; 182 /* Allow percpu accesses to work until we setup percpu data */ 183 get_paca()->data_offset = 0; 184 /* Mark interrupts disabled in PACA */ 185 irq_soft_mask_set(IRQS_DISABLED); 186 } 187 188 static void __init configure_exceptions(void) 189 { 190 /* 191 * Setup the trampolines from the lowmem exception vectors 192 * to the kdump kernel when not using a relocatable kernel. 193 */ 194 setup_kdump_trampoline(); 195 196 /* Under a PAPR hypervisor, we need hypercalls */ 197 if (firmware_has_feature(FW_FEATURE_SET_MODE)) { 198 /* Enable AIL if possible */ 199 pseries_enable_reloc_on_exc(); 200 201 /* 202 * Tell the hypervisor that we want our exceptions to 203 * be taken in little endian mode. 204 * 205 * We don't call this for big endian as our calling convention 206 * makes us always enter in BE, and the call may fail under 207 * some circumstances with kdump. 208 */ 209 #ifdef __LITTLE_ENDIAN__ 210 pseries_little_endian_exceptions(); 211 #endif 212 } else { 213 /* Set endian mode using OPAL */ 214 if (firmware_has_feature(FW_FEATURE_OPAL)) 215 opal_configure_cores(); 216 217 /* AIL on native is done in cpu_ready_for_interrupts() */ 218 } 219 } 220 221 static void cpu_ready_for_interrupts(void) 222 { 223 /* 224 * Enable AIL if supported, and we are in hypervisor mode. This 225 * is called once for every processor. 226 * 227 * If we are not in hypervisor mode the job is done once for 228 * the whole partition in configure_exceptions(). 229 */ 230 if (cpu_has_feature(CPU_FTR_HVMODE) && 231 cpu_has_feature(CPU_FTR_ARCH_207S)) { 232 unsigned long lpcr = mfspr(SPRN_LPCR); 233 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3); 234 } 235 236 /* 237 * Set HFSCR:TM based on CPU features: 238 * In the special case of TM no suspend (P9N DD2.1), Linux is 239 * told TM is off via the dt-ftrs but told to (partially) use 240 * it via OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED. So HFSCR[TM] 241 * will be off from dt-ftrs but we need to turn it on for the 242 * no suspend case. 243 */ 244 if (cpu_has_feature(CPU_FTR_HVMODE)) { 245 if (cpu_has_feature(CPU_FTR_TM_COMP)) 246 mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) | HFSCR_TM); 247 else 248 mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM); 249 } 250 251 /* Set IR and DR in PACA MSR */ 252 get_paca()->kernel_msr = MSR_KERNEL; 253 } 254 255 unsigned long spr_default_dscr = 0; 256 257 void __init record_spr_defaults(void) 258 { 259 if (early_cpu_has_feature(CPU_FTR_DSCR)) 260 spr_default_dscr = mfspr(SPRN_DSCR); 261 } 262 263 /* 264 * Early initialization entry point. This is called by head.S 265 * with MMU translation disabled. We rely on the "feature" of 266 * the CPU that ignores the top 2 bits of the address in real 267 * mode so we can access kernel globals normally provided we 268 * only toy with things in the RMO region. From here, we do 269 * some early parsing of the device-tree to setup out MEMBLOCK 270 * data structures, and allocate & initialize the hash table 271 * and segment tables so we can start running with translation 272 * enabled. 273 * 274 * It is this function which will call the probe() callback of 275 * the various platform types and copy the matching one to the 276 * global ppc_md structure. Your platform can eventually do 277 * some very early initializations from the probe() routine, but 278 * this is not recommended, be very careful as, for example, the 279 * device-tree is not accessible via normal means at this point. 280 */ 281 282 void __init early_setup(unsigned long dt_ptr) 283 { 284 static __initdata struct paca_struct boot_paca; 285 286 /* -------- printk is _NOT_ safe to use here ! ------- */ 287 288 /* Try new device tree based feature discovery ... */ 289 if (!dt_cpu_ftrs_init(__va(dt_ptr))) 290 /* Otherwise use the old style CPU table */ 291 identify_cpu(0, mfspr(SPRN_PVR)); 292 293 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ 294 initialise_paca(&boot_paca, 0); 295 setup_paca(&boot_paca); 296 fixup_boot_paca(); 297 298 /* -------- printk is now safe to use ------- */ 299 300 /* Enable early debugging if any specified (see udbg.h) */ 301 udbg_early_init(); 302 303 udbg_printf(" -> %s(), dt_ptr: 0x%lx\n", __func__, dt_ptr); 304 305 /* 306 * Do early initialization using the flattened device 307 * tree, such as retrieving the physical memory map or 308 * calculating/retrieving the hash table size. 309 */ 310 early_init_devtree(__va(dt_ptr)); 311 312 /* Now we know the logical id of our boot cpu, setup the paca. */ 313 if (boot_cpuid != 0) { 314 /* Poison paca_ptrs[0] again if it's not the boot cpu */ 315 memset(&paca_ptrs[0], 0x88, sizeof(paca_ptrs[0])); 316 } 317 setup_paca(paca_ptrs[boot_cpuid]); 318 fixup_boot_paca(); 319 320 /* 321 * Configure exception handlers. This include setting up trampolines 322 * if needed, setting exception endian mode, etc... 323 */ 324 configure_exceptions(); 325 326 /* 327 * Configure Kernel Userspace Protection. This needs to happen before 328 * feature fixups for platforms that implement this using features. 329 */ 330 setup_kup(); 331 332 /* Apply all the dynamic patching */ 333 apply_feature_fixups(); 334 setup_feature_keys(); 335 336 early_ioremap_setup(); 337 338 /* Initialize the hash table or TLB handling */ 339 early_init_mmu(); 340 341 /* 342 * After firmware and early platform setup code has set things up, 343 * we note the SPR values for configurable control/performance 344 * registers, and use those as initial defaults. 345 */ 346 record_spr_defaults(); 347 348 /* 349 * At this point, we can let interrupts switch to virtual mode 350 * (the MMU has been setup), so adjust the MSR in the PACA to 351 * have IR and DR set and enable AIL if it exists 352 */ 353 cpu_ready_for_interrupts(); 354 355 /* 356 * We enable ftrace here, but since we only support DYNAMIC_FTRACE, it 357 * will only actually get enabled on the boot cpu much later once 358 * ftrace itself has been initialized. 359 */ 360 this_cpu_enable_ftrace(); 361 362 udbg_printf(" <- %s()\n", __func__); 363 364 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX 365 /* 366 * This needs to be done *last* (after the above udbg_printf() even) 367 * 368 * Right after we return from this function, we turn on the MMU 369 * which means the real-mode access trick that btext does will 370 * no longer work, it needs to switch to using a real MMU 371 * mapping. This call will ensure that it does 372 */ 373 btext_map(); 374 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */ 375 } 376 377 #ifdef CONFIG_SMP 378 void early_setup_secondary(void) 379 { 380 /* Mark interrupts disabled in PACA */ 381 irq_soft_mask_set(IRQS_DISABLED); 382 383 /* Initialize the hash table or TLB handling */ 384 early_init_mmu_secondary(); 385 386 /* Perform any KUP setup that is per-cpu */ 387 setup_kup(); 388 389 /* 390 * At this point, we can let interrupts switch to virtual mode 391 * (the MMU has been setup), so adjust the MSR in the PACA to 392 * have IR and DR set. 393 */ 394 cpu_ready_for_interrupts(); 395 } 396 397 #endif /* CONFIG_SMP */ 398 399 void panic_smp_self_stop(void) 400 { 401 hard_irq_disable(); 402 spin_begin(); 403 while (1) 404 spin_cpu_relax(); 405 } 406 407 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE) 408 static bool use_spinloop(void) 409 { 410 if (IS_ENABLED(CONFIG_PPC_BOOK3S)) { 411 /* 412 * See comments in head_64.S -- not all platforms insert 413 * secondaries at __secondary_hold and wait at the spin 414 * loop. 415 */ 416 if (firmware_has_feature(FW_FEATURE_OPAL)) 417 return false; 418 return true; 419 } 420 421 /* 422 * When book3e boots from kexec, the ePAPR spin table does 423 * not get used. 424 */ 425 return of_property_read_bool(of_chosen, "linux,booted-from-kexec"); 426 } 427 428 void smp_release_cpus(void) 429 { 430 unsigned long *ptr; 431 int i; 432 433 if (!use_spinloop()) 434 return; 435 436 /* All secondary cpus are spinning on a common spinloop, release them 437 * all now so they can start to spin on their individual paca 438 * spinloops. For non SMP kernels, the secondary cpus never get out 439 * of the common spinloop. 440 */ 441 442 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop 443 - PHYSICAL_START); 444 *ptr = ppc_function_entry(generic_secondary_smp_init); 445 446 /* And wait a bit for them to catch up */ 447 for (i = 0; i < 100000; i++) { 448 mb(); 449 HMT_low(); 450 if (spinning_secondaries == 0) 451 break; 452 udelay(1); 453 } 454 pr_debug("spinning_secondaries = %d\n", spinning_secondaries); 455 } 456 #endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */ 457 458 /* 459 * Initialize some remaining members of the ppc64_caches and systemcfg 460 * structures 461 * (at least until we get rid of them completely). This is mostly some 462 * cache informations about the CPU that will be used by cache flush 463 * routines and/or provided to userland 464 */ 465 466 static void init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize, 467 u32 bsize, u32 sets) 468 { 469 info->size = size; 470 info->sets = sets; 471 info->line_size = lsize; 472 info->block_size = bsize; 473 info->log_block_size = __ilog2(bsize); 474 if (bsize) 475 info->blocks_per_page = PAGE_SIZE / bsize; 476 else 477 info->blocks_per_page = 0; 478 479 if (sets == 0) 480 info->assoc = 0xffff; 481 else 482 info->assoc = size / (sets * lsize); 483 } 484 485 static bool __init parse_cache_info(struct device_node *np, 486 bool icache, 487 struct ppc_cache_info *info) 488 { 489 static const char *ipropnames[] __initdata = { 490 "i-cache-size", 491 "i-cache-sets", 492 "i-cache-block-size", 493 "i-cache-line-size", 494 }; 495 static const char *dpropnames[] __initdata = { 496 "d-cache-size", 497 "d-cache-sets", 498 "d-cache-block-size", 499 "d-cache-line-size", 500 }; 501 const char **propnames = icache ? ipropnames : dpropnames; 502 const __be32 *sizep, *lsizep, *bsizep, *setsp; 503 u32 size, lsize, bsize, sets; 504 bool success = true; 505 506 size = 0; 507 sets = -1u; 508 lsize = bsize = cur_cpu_spec->dcache_bsize; 509 sizep = of_get_property(np, propnames[0], NULL); 510 if (sizep != NULL) 511 size = be32_to_cpu(*sizep); 512 setsp = of_get_property(np, propnames[1], NULL); 513 if (setsp != NULL) 514 sets = be32_to_cpu(*setsp); 515 bsizep = of_get_property(np, propnames[2], NULL); 516 lsizep = of_get_property(np, propnames[3], NULL); 517 if (bsizep == NULL) 518 bsizep = lsizep; 519 if (lsizep != NULL) 520 lsize = be32_to_cpu(*lsizep); 521 if (bsizep != NULL) 522 bsize = be32_to_cpu(*bsizep); 523 if (sizep == NULL || bsizep == NULL || lsizep == NULL) 524 success = false; 525 526 /* 527 * OF is weird .. it represents fully associative caches 528 * as "1 way" which doesn't make much sense and doesn't 529 * leave room for direct mapped. We'll assume that 0 530 * in OF means direct mapped for that reason. 531 */ 532 if (sets == 1) 533 sets = 0; 534 else if (sets == 0) 535 sets = 1; 536 537 init_cache_info(info, size, lsize, bsize, sets); 538 539 return success; 540 } 541 542 void __init initialize_cache_info(void) 543 { 544 struct device_node *cpu = NULL, *l2, *l3 = NULL; 545 u32 pvr; 546 547 /* 548 * All shipping POWER8 machines have a firmware bug that 549 * puts incorrect information in the device-tree. This will 550 * be (hopefully) fixed for future chips but for now hard 551 * code the values if we are running on one of these 552 */ 553 pvr = PVR_VER(mfspr(SPRN_PVR)); 554 if (pvr == PVR_POWER8 || pvr == PVR_POWER8E || 555 pvr == PVR_POWER8NVL) { 556 /* size lsize blk sets */ 557 init_cache_info(&ppc64_caches.l1i, 0x8000, 128, 128, 32); 558 init_cache_info(&ppc64_caches.l1d, 0x10000, 128, 128, 64); 559 init_cache_info(&ppc64_caches.l2, 0x80000, 128, 0, 512); 560 init_cache_info(&ppc64_caches.l3, 0x800000, 128, 0, 8192); 561 } else 562 cpu = of_find_node_by_type(NULL, "cpu"); 563 564 /* 565 * We're assuming *all* of the CPUs have the same 566 * d-cache and i-cache sizes... -Peter 567 */ 568 if (cpu) { 569 if (!parse_cache_info(cpu, false, &ppc64_caches.l1d)) 570 pr_warn("Argh, can't find dcache properties !\n"); 571 572 if (!parse_cache_info(cpu, true, &ppc64_caches.l1i)) 573 pr_warn("Argh, can't find icache properties !\n"); 574 575 /* 576 * Try to find the L2 and L3 if any. Assume they are 577 * unified and use the D-side properties. 578 */ 579 l2 = of_find_next_cache_node(cpu); 580 of_node_put(cpu); 581 if (l2) { 582 parse_cache_info(l2, false, &ppc64_caches.l2); 583 l3 = of_find_next_cache_node(l2); 584 of_node_put(l2); 585 } 586 if (l3) { 587 parse_cache_info(l3, false, &ppc64_caches.l3); 588 of_node_put(l3); 589 } 590 } 591 592 /* For use by binfmt_elf */ 593 dcache_bsize = ppc64_caches.l1d.block_size; 594 icache_bsize = ppc64_caches.l1i.block_size; 595 596 cur_cpu_spec->dcache_bsize = dcache_bsize; 597 cur_cpu_spec->icache_bsize = icache_bsize; 598 } 599 600 /* 601 * This returns the limit below which memory accesses to the linear 602 * mapping are guarnateed not to cause an architectural exception (e.g., 603 * TLB or SLB miss fault). 604 * 605 * This is used to allocate PACAs and various interrupt stacks that 606 * that are accessed early in interrupt handlers that must not cause 607 * re-entrant interrupts. 608 */ 609 __init u64 ppc64_bolted_size(void) 610 { 611 #ifdef CONFIG_PPC_BOOK3E 612 /* Freescale BookE bolts the entire linear mapping */ 613 /* XXX: BookE ppc64_rma_limit setup seems to disagree? */ 614 if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E)) 615 return linear_map_top; 616 /* Other BookE, we assume the first GB is bolted */ 617 return 1ul << 30; 618 #else 619 /* BookS radix, does not take faults on linear mapping */ 620 if (early_radix_enabled()) 621 return ULONG_MAX; 622 623 /* BookS hash, the first segment is bolted */ 624 if (early_mmu_has_feature(MMU_FTR_1T_SEGMENT)) 625 return 1UL << SID_SHIFT_1T; 626 return 1UL << SID_SHIFT; 627 #endif 628 } 629 630 static void *__init alloc_stack(unsigned long limit, int cpu) 631 { 632 void *ptr; 633 634 BUILD_BUG_ON(STACK_INT_FRAME_SIZE % 16); 635 636 ptr = memblock_alloc_try_nid(THREAD_SIZE, THREAD_SIZE, 637 MEMBLOCK_LOW_LIMIT, limit, 638 early_cpu_to_node(cpu)); 639 if (!ptr) 640 panic("cannot allocate stacks"); 641 642 return ptr; 643 } 644 645 void __init irqstack_early_init(void) 646 { 647 u64 limit = ppc64_bolted_size(); 648 unsigned int i; 649 650 /* 651 * Interrupt stacks must be in the first segment since we 652 * cannot afford to take SLB misses on them. They are not 653 * accessed in realmode. 654 */ 655 for_each_possible_cpu(i) { 656 softirq_ctx[i] = alloc_stack(limit, i); 657 hardirq_ctx[i] = alloc_stack(limit, i); 658 } 659 } 660 661 #ifdef CONFIG_PPC_BOOK3E 662 void __init exc_lvl_early_init(void) 663 { 664 unsigned int i; 665 666 for_each_possible_cpu(i) { 667 void *sp; 668 669 sp = alloc_stack(ULONG_MAX, i); 670 critirq_ctx[i] = sp; 671 paca_ptrs[i]->crit_kstack = sp + THREAD_SIZE; 672 673 sp = alloc_stack(ULONG_MAX, i); 674 dbgirq_ctx[i] = sp; 675 paca_ptrs[i]->dbg_kstack = sp + THREAD_SIZE; 676 677 sp = alloc_stack(ULONG_MAX, i); 678 mcheckirq_ctx[i] = sp; 679 paca_ptrs[i]->mc_kstack = sp + THREAD_SIZE; 680 } 681 682 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) 683 patch_exception(0x040, exc_debug_debug_book3e); 684 } 685 #endif 686 687 /* 688 * Stack space used when we detect a bad kernel stack pointer, and 689 * early in SMP boots before relocation is enabled. Exclusive emergency 690 * stack for machine checks. 691 */ 692 void __init emergency_stack_init(void) 693 { 694 u64 limit; 695 unsigned int i; 696 697 /* 698 * Emergency stacks must be under 256MB, we cannot afford to take 699 * SLB misses on them. The ABI also requires them to be 128-byte 700 * aligned. 701 * 702 * Since we use these as temporary stacks during secondary CPU 703 * bringup, machine check, system reset, and HMI, we need to get 704 * at them in real mode. This means they must also be within the RMO 705 * region. 706 * 707 * The IRQ stacks allocated elsewhere in this file are zeroed and 708 * initialized in kernel/irq.c. These are initialized here in order 709 * to have emergency stacks available as early as possible. 710 */ 711 limit = min(ppc64_bolted_size(), ppc64_rma_size); 712 713 for_each_possible_cpu(i) { 714 paca_ptrs[i]->emergency_sp = alloc_stack(limit, i) + THREAD_SIZE; 715 716 #ifdef CONFIG_PPC_BOOK3S_64 717 /* emergency stack for NMI exception handling. */ 718 paca_ptrs[i]->nmi_emergency_sp = alloc_stack(limit, i) + THREAD_SIZE; 719 720 /* emergency stack for machine check exception handling. */ 721 paca_ptrs[i]->mc_emergency_sp = alloc_stack(limit, i) + THREAD_SIZE; 722 #endif 723 } 724 } 725 726 #ifdef CONFIG_SMP 727 #define PCPU_DYN_SIZE () 728 729 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) 730 { 731 return memblock_alloc_try_nid(size, align, __pa(MAX_DMA_ADDRESS), 732 MEMBLOCK_ALLOC_ACCESSIBLE, 733 early_cpu_to_node(cpu)); 734 735 } 736 737 static void __init pcpu_fc_free(void *ptr, size_t size) 738 { 739 memblock_free(__pa(ptr), size); 740 } 741 742 static int pcpu_cpu_distance(unsigned int from, unsigned int to) 743 { 744 if (early_cpu_to_node(from) == early_cpu_to_node(to)) 745 return LOCAL_DISTANCE; 746 else 747 return REMOTE_DISTANCE; 748 } 749 750 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; 751 EXPORT_SYMBOL(__per_cpu_offset); 752 753 void __init setup_per_cpu_areas(void) 754 { 755 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; 756 size_t atom_size; 757 unsigned long delta; 758 unsigned int cpu; 759 int rc; 760 761 /* 762 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need 763 * to group units. For larger mappings, use 1M atom which 764 * should be large enough to contain a number of units. 765 */ 766 if (mmu_linear_psize == MMU_PAGE_4K) 767 atom_size = PAGE_SIZE; 768 else 769 atom_size = 1 << 20; 770 771 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, 772 pcpu_fc_alloc, pcpu_fc_free); 773 if (rc < 0) 774 panic("cannot initialize percpu area (err=%d)", rc); 775 776 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; 777 for_each_possible_cpu(cpu) { 778 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; 779 paca_ptrs[cpu]->data_offset = __per_cpu_offset[cpu]; 780 } 781 } 782 #endif 783 784 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE 785 unsigned long memory_block_size_bytes(void) 786 { 787 if (ppc_md.memory_block_size) 788 return ppc_md.memory_block_size(); 789 790 return MIN_MEMORY_BLOCK_SIZE; 791 } 792 #endif 793 794 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) 795 struct ppc_pci_io ppc_pci_io; 796 EXPORT_SYMBOL(ppc_pci_io); 797 #endif 798 799 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF 800 u64 hw_nmi_get_sample_period(int watchdog_thresh) 801 { 802 return ppc_proc_freq * watchdog_thresh; 803 } 804 #endif 805 806 /* 807 * The perf based hardlockup detector breaks PMU event based branches, so 808 * disable it by default. Book3S has a soft-nmi hardlockup detector based 809 * on the decrementer interrupt, so it does not suffer from this problem. 810 * 811 * It is likely to get false positives in VM guests, so disable it there 812 * by default too. 813 */ 814 static int __init disable_hardlockup_detector(void) 815 { 816 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF 817 hardlockup_detector_disable(); 818 #else 819 if (firmware_has_feature(FW_FEATURE_LPAR)) 820 hardlockup_detector_disable(); 821 #endif 822 823 return 0; 824 } 825 early_initcall(disable_hardlockup_detector); 826 827 #ifdef CONFIG_PPC_BOOK3S_64 828 static enum l1d_flush_type enabled_flush_types; 829 static void *l1d_flush_fallback_area; 830 static bool no_rfi_flush; 831 bool rfi_flush; 832 833 static int __init handle_no_rfi_flush(char *p) 834 { 835 pr_info("rfi-flush: disabled on command line."); 836 no_rfi_flush = true; 837 return 0; 838 } 839 early_param("no_rfi_flush", handle_no_rfi_flush); 840 841 /* 842 * The RFI flush is not KPTI, but because users will see doco that says to use 843 * nopti we hijack that option here to also disable the RFI flush. 844 */ 845 static int __init handle_no_pti(char *p) 846 { 847 pr_info("rfi-flush: disabling due to 'nopti' on command line.\n"); 848 handle_no_rfi_flush(NULL); 849 return 0; 850 } 851 early_param("nopti", handle_no_pti); 852 853 static void do_nothing(void *unused) 854 { 855 /* 856 * We don't need to do the flush explicitly, just enter+exit kernel is 857 * sufficient, the RFI exit handlers will do the right thing. 858 */ 859 } 860 861 void rfi_flush_enable(bool enable) 862 { 863 if (enable) { 864 do_rfi_flush_fixups(enabled_flush_types); 865 on_each_cpu(do_nothing, NULL, 1); 866 } else 867 do_rfi_flush_fixups(L1D_FLUSH_NONE); 868 869 rfi_flush = enable; 870 } 871 872 static void __ref init_fallback_flush(void) 873 { 874 u64 l1d_size, limit; 875 int cpu; 876 877 /* Only allocate the fallback flush area once (at boot time). */ 878 if (l1d_flush_fallback_area) 879 return; 880 881 l1d_size = ppc64_caches.l1d.size; 882 883 /* 884 * If there is no d-cache-size property in the device tree, l1d_size 885 * could be zero. That leads to the loop in the asm wrapping around to 886 * 2^64-1, and then walking off the end of the fallback area and 887 * eventually causing a page fault which is fatal. Just default to 888 * something vaguely sane. 889 */ 890 if (!l1d_size) 891 l1d_size = (64 * 1024); 892 893 limit = min(ppc64_bolted_size(), ppc64_rma_size); 894 895 /* 896 * Align to L1d size, and size it at 2x L1d size, to catch possible 897 * hardware prefetch runoff. We don't have a recipe for load patterns to 898 * reliably avoid the prefetcher. 899 */ 900 l1d_flush_fallback_area = memblock_alloc_try_nid(l1d_size * 2, 901 l1d_size, MEMBLOCK_LOW_LIMIT, 902 limit, NUMA_NO_NODE); 903 if (!l1d_flush_fallback_area) 904 panic("%s: Failed to allocate %llu bytes align=0x%llx max_addr=%pa\n", 905 __func__, l1d_size * 2, l1d_size, &limit); 906 907 908 for_each_possible_cpu(cpu) { 909 struct paca_struct *paca = paca_ptrs[cpu]; 910 paca->rfi_flush_fallback_area = l1d_flush_fallback_area; 911 paca->l1d_flush_size = l1d_size; 912 } 913 } 914 915 void setup_rfi_flush(enum l1d_flush_type types, bool enable) 916 { 917 if (types & L1D_FLUSH_FALLBACK) { 918 pr_info("rfi-flush: fallback displacement flush available\n"); 919 init_fallback_flush(); 920 } 921 922 if (types & L1D_FLUSH_ORI) 923 pr_info("rfi-flush: ori type flush available\n"); 924 925 if (types & L1D_FLUSH_MTTRIG) 926 pr_info("rfi-flush: mttrig type flush available\n"); 927 928 enabled_flush_types = types; 929 930 if (!no_rfi_flush && !cpu_mitigations_off()) 931 rfi_flush_enable(enable); 932 } 933 934 #ifdef CONFIG_DEBUG_FS 935 static int rfi_flush_set(void *data, u64 val) 936 { 937 bool enable; 938 939 if (val == 1) 940 enable = true; 941 else if (val == 0) 942 enable = false; 943 else 944 return -EINVAL; 945 946 /* Only do anything if we're changing state */ 947 if (enable != rfi_flush) 948 rfi_flush_enable(enable); 949 950 return 0; 951 } 952 953 static int rfi_flush_get(void *data, u64 *val) 954 { 955 *val = rfi_flush ? 1 : 0; 956 return 0; 957 } 958 959 DEFINE_SIMPLE_ATTRIBUTE(fops_rfi_flush, rfi_flush_get, rfi_flush_set, "%llu\n"); 960 961 static __init int rfi_flush_debugfs_init(void) 962 { 963 debugfs_create_file("rfi_flush", 0600, powerpc_debugfs_root, NULL, &fops_rfi_flush); 964 return 0; 965 } 966 device_initcall(rfi_flush_debugfs_init); 967 #endif 968 #endif /* CONFIG_PPC_BOOK3S_64 */ 969