1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * MPC85xx RDB Board Setup
4  *
5  * Copyright 2009,2012-2013 Freescale Semiconductor Inc.
6  */
7 
8 #include <linux/stddef.h>
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/kdev_t.h>
12 #include <linux/delay.h>
13 #include <linux/seq_file.h>
14 #include <linux/interrupt.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/fsl/guts.h>
18 
19 #include <asm/time.h>
20 #include <asm/machdep.h>
21 #include <asm/pci-bridge.h>
22 #include <mm/mmu_decl.h>
23 #include <asm/udbg.h>
24 #include <asm/mpic.h>
25 #include <soc/fsl/qe/qe.h>
26 
27 #include <sysdev/fsl_soc.h>
28 #include <sysdev/fsl_pci.h>
29 #include "smp.h"
30 
31 #include "mpc85xx.h"
32 
33 static void __init mpc85xx_rdb_pic_init(void)
34 {
35 	struct mpic *mpic;
36 	int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU;
37 
38 	if (of_machine_is_compatible("fsl,MPC85XXRDB-CAMP"))
39 		flags |= MPIC_NO_RESET;
40 
41 	mpic = mpic_alloc(NULL, 0, flags, 0, 256, " OpenPIC  ");
42 
43 	if (WARN_ON(!mpic))
44 		return;
45 
46 	mpic_init(mpic);
47 }
48 
49 /*
50  * Setup the architecture
51  */
52 static void __init mpc85xx_rdb_setup_arch(void)
53 {
54 	if (ppc_md.progress)
55 		ppc_md.progress("mpc85xx_rdb_setup_arch()", 0);
56 
57 	mpc85xx_smp_init();
58 
59 	fsl_pci_assign_primary();
60 
61 	mpc85xx_qe_par_io_init();
62 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
63 	if (machine_is(p1025_rdb)) {
64 		struct device_node *np;
65 
66 		struct ccsr_guts __iomem *guts;
67 
68 		np = of_find_node_by_name(NULL, "global-utilities");
69 		if (np) {
70 			guts = of_iomap(np, 0);
71 			if (!guts) {
72 
73 				pr_err("mpc85xx-rdb: could not map global utilities register\n");
74 
75 			} else {
76 			/* P1025 has pins muxed for QE and other functions. To
77 			* enable QE UEC mode, we need to set bit QE0 for UCC1
78 			* in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
79 			* and QE12 for QE MII management singals in PMUXCR
80 			* register.
81 			*/
82 				setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
83 						MPC85xx_PMUXCR_QE(3) |
84 						MPC85xx_PMUXCR_QE(9) |
85 						MPC85xx_PMUXCR_QE(12));
86 				iounmap(guts);
87 			}
88 			of_node_put(np);
89 		}
90 
91 	}
92 #endif
93 
94 	pr_info("MPC85xx RDB board from Freescale Semiconductor\n");
95 }
96 
97 machine_arch_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices);
98 machine_arch_initcall(p1020_rdb, mpc85xx_common_publish_devices);
99 machine_arch_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
100 machine_arch_initcall(p1020_rdb_pd, mpc85xx_common_publish_devices);
101 machine_arch_initcall(p1020_utm_pc, mpc85xx_common_publish_devices);
102 machine_arch_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices);
103 machine_arch_initcall(p1025_rdb, mpc85xx_common_publish_devices);
104 machine_arch_initcall(p1024_rdb, mpc85xx_common_publish_devices);
105 
106 define_machine(p1020_rdb) {
107 	.name			= "P1020 RDB",
108 	.compatible		= "fsl,P1020RDB",
109 	.setup_arch		= mpc85xx_rdb_setup_arch,
110 	.init_IRQ		= mpc85xx_rdb_pic_init,
111 #ifdef CONFIG_PCI
112 	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
113 	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
114 #endif
115 	.get_irq		= mpic_get_irq,
116 	.progress		= udbg_progress,
117 };
118 
119 define_machine(p1021_rdb_pc) {
120 	.name			= "P1021 RDB-PC",
121 	.compatible		= "fsl,P1021RDB-PC",
122 	.setup_arch		= mpc85xx_rdb_setup_arch,
123 	.init_IRQ		= mpc85xx_rdb_pic_init,
124 #ifdef CONFIG_PCI
125 	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
126 	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
127 #endif
128 	.get_irq		= mpic_get_irq,
129 	.progress		= udbg_progress,
130 };
131 
132 define_machine(p1025_rdb) {
133 	.name			= "P1025 RDB",
134 	.compatible		= "fsl,P1025RDB",
135 	.setup_arch		= mpc85xx_rdb_setup_arch,
136 	.init_IRQ		= mpc85xx_rdb_pic_init,
137 #ifdef CONFIG_PCI
138 	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
139 	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
140 #endif
141 	.get_irq		= mpic_get_irq,
142 	.progress		= udbg_progress,
143 };
144 
145 define_machine(p1020_mbg_pc) {
146 	.name			= "P1020 MBG-PC",
147 	.compatible		= "fsl,P1020MBG-PC",
148 	.setup_arch		= mpc85xx_rdb_setup_arch,
149 	.init_IRQ		= mpc85xx_rdb_pic_init,
150 #ifdef CONFIG_PCI
151 	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
152 	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
153 #endif
154 	.get_irq		= mpic_get_irq,
155 	.progress		= udbg_progress,
156 };
157 
158 define_machine(p1020_utm_pc) {
159 	.name			= "P1020 UTM-PC",
160 	.compatible		= "fsl,P1020UTM-PC",
161 	.setup_arch		= mpc85xx_rdb_setup_arch,
162 	.init_IRQ		= mpc85xx_rdb_pic_init,
163 #ifdef CONFIG_PCI
164 	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
165 	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
166 #endif
167 	.get_irq		= mpic_get_irq,
168 	.progress		= udbg_progress,
169 };
170 
171 define_machine(p1020_rdb_pc) {
172 	.name			= "P1020RDB-PC",
173 	.compatible		= "fsl,P1020RDB-PC",
174 	.setup_arch		= mpc85xx_rdb_setup_arch,
175 	.init_IRQ		= mpc85xx_rdb_pic_init,
176 #ifdef CONFIG_PCI
177 	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
178 	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
179 #endif
180 	.get_irq		= mpic_get_irq,
181 	.progress		= udbg_progress,
182 };
183 
184 define_machine(p1020_rdb_pd) {
185 	.name			= "P1020RDB-PD",
186 	.compatible		= "fsl,P1020RDB-PD",
187 	.setup_arch		= mpc85xx_rdb_setup_arch,
188 	.init_IRQ		= mpc85xx_rdb_pic_init,
189 #ifdef CONFIG_PCI
190 	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
191 	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
192 #endif
193 	.get_irq		= mpic_get_irq,
194 	.progress		= udbg_progress,
195 };
196 
197 define_machine(p1024_rdb) {
198 	.name			= "P1024 RDB",
199 	.compatible		= "fsl,P1024RDB",
200 	.setup_arch		= mpc85xx_rdb_setup_arch,
201 	.init_IRQ		= mpc85xx_rdb_pic_init,
202 #ifdef CONFIG_PCI
203 	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
204 	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
205 #endif
206 	.get_irq		= mpic_get_irq,
207 	.progress		= udbg_progress,
208 };
209