1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 1996-2001 Paul Mackerras (paulus@cs.anu.edu.au) 4 * Ben. Herrenschmidt (benh@kernel.crashing.org) 5 * 6 * TODO: 7 * 8 * - Replace mdelay with some schedule loop if possible 9 * - Shorten some obfuscated delays on some routines (like modem 10 * power) 11 * - Refcount some clocks (see darwin) 12 * - Split split split... 13 */ 14 #include <linux/types.h> 15 #include <linux/init.h> 16 #include <linux/delay.h> 17 #include <linux/kernel.h> 18 #include <linux/sched.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/spinlock.h> 22 #include <linux/adb.h> 23 #include <linux/pmu.h> 24 #include <linux/ioport.h> 25 #include <linux/export.h> 26 #include <linux/pci.h> 27 #include <asm/sections.h> 28 #include <asm/errno.h> 29 #include <asm/ohare.h> 30 #include <asm/heathrow.h> 31 #include <asm/keylargo.h> 32 #include <asm/uninorth.h> 33 #include <asm/io.h> 34 #include <asm/machdep.h> 35 #include <asm/pmac_feature.h> 36 #include <asm/dbdma.h> 37 #include <asm/pci-bridge.h> 38 #include <asm/pmac_low_i2c.h> 39 40 #undef DEBUG_FEATURE 41 42 #ifdef DEBUG_FEATURE 43 #define DBG(fmt...) printk(KERN_DEBUG fmt) 44 #else 45 #define DBG(fmt...) 46 #endif 47 48 #ifdef CONFIG_PPC_BOOK3S_32 49 extern int powersave_lowspeed; 50 #endif 51 52 extern int powersave_nap; 53 extern struct device_node *k2_skiplist[2]; 54 55 /* 56 * We use a single global lock to protect accesses. Each driver has 57 * to take care of its own locking 58 */ 59 DEFINE_RAW_SPINLOCK(feature_lock); 60 61 #define LOCK(flags) raw_spin_lock_irqsave(&feature_lock, flags); 62 #define UNLOCK(flags) raw_spin_unlock_irqrestore(&feature_lock, flags); 63 64 65 /* 66 * Instance of some macio stuffs 67 */ 68 struct macio_chip macio_chips[MAX_MACIO_CHIPS]; 69 70 struct macio_chip *macio_find(struct device_node *child, int type) 71 { 72 while(child) { 73 int i; 74 75 for (i=0; i < MAX_MACIO_CHIPS && macio_chips[i].of_node; i++) 76 if (child == macio_chips[i].of_node && 77 (!type || macio_chips[i].type == type)) 78 return &macio_chips[i]; 79 child = child->parent; 80 } 81 return NULL; 82 } 83 EXPORT_SYMBOL_GPL(macio_find); 84 85 static const char *macio_names[] = 86 { 87 "Unknown", 88 "Grand Central", 89 "OHare", 90 "OHareII", 91 "Heathrow", 92 "Gatwick", 93 "Paddington", 94 "Keylargo", 95 "Pangea", 96 "Intrepid", 97 "K2", 98 "Shasta", 99 }; 100 101 102 struct device_node *uninorth_node; 103 u32 __iomem *uninorth_base; 104 105 static u32 uninorth_rev; 106 static int uninorth_maj; 107 static void __iomem *u3_ht_base; 108 109 /* 110 * For each motherboard family, we have a table of functions pointers 111 * that handle the various features. 112 */ 113 114 typedef long (*feature_call)(struct device_node *node, long param, long value); 115 116 struct feature_table_entry { 117 unsigned int selector; 118 feature_call function; 119 }; 120 121 struct pmac_mb_def 122 { 123 const char* model_string; 124 const char* model_name; 125 int model_id; 126 struct feature_table_entry* features; 127 unsigned long board_flags; 128 }; 129 static struct pmac_mb_def pmac_mb; 130 131 /* 132 * Here are the chip specific feature functions 133 */ 134 135 static inline int simple_feature_tweak(struct device_node *node, int type, 136 int reg, u32 mask, int value) 137 { 138 struct macio_chip* macio; 139 unsigned long flags; 140 141 macio = macio_find(node, type); 142 if (!macio) 143 return -ENODEV; 144 LOCK(flags); 145 if (value) 146 MACIO_BIS(reg, mask); 147 else 148 MACIO_BIC(reg, mask); 149 (void)MACIO_IN32(reg); 150 UNLOCK(flags); 151 152 return 0; 153 } 154 155 #ifndef CONFIG_PPC64 156 157 static long ohare_htw_scc_enable(struct device_node *node, long param, 158 long value) 159 { 160 struct macio_chip* macio; 161 unsigned long chan_mask; 162 unsigned long fcr; 163 unsigned long flags; 164 int htw, trans; 165 unsigned long rmask; 166 167 macio = macio_find(node, 0); 168 if (!macio) 169 return -ENODEV; 170 if (of_node_name_eq(node, "ch-a")) 171 chan_mask = MACIO_FLAG_SCCA_ON; 172 else if (of_node_name_eq(node, "ch-b")) 173 chan_mask = MACIO_FLAG_SCCB_ON; 174 else 175 return -ENODEV; 176 177 htw = (macio->type == macio_heathrow || macio->type == macio_paddington 178 || macio->type == macio_gatwick); 179 /* On these machines, the HRW_SCC_TRANS_EN_N bit mustn't be touched */ 180 trans = (pmac_mb.model_id != PMAC_TYPE_YOSEMITE && 181 pmac_mb.model_id != PMAC_TYPE_YIKES); 182 if (value) { 183 #ifdef CONFIG_ADB_PMU 184 if ((param & 0xfff) == PMAC_SCC_IRDA) 185 pmu_enable_irled(1); 186 #endif /* CONFIG_ADB_PMU */ 187 LOCK(flags); 188 fcr = MACIO_IN32(OHARE_FCR); 189 /* Check if scc cell need enabling */ 190 if (!(fcr & OH_SCC_ENABLE)) { 191 fcr |= OH_SCC_ENABLE; 192 if (htw) { 193 /* Side effect: this will also power up the 194 * modem, but it's too messy to figure out on which 195 * ports this controls the transceiver and on which 196 * it controls the modem 197 */ 198 if (trans) 199 fcr &= ~HRW_SCC_TRANS_EN_N; 200 MACIO_OUT32(OHARE_FCR, fcr); 201 fcr |= (rmask = HRW_RESET_SCC); 202 MACIO_OUT32(OHARE_FCR, fcr); 203 } else { 204 fcr |= (rmask = OH_SCC_RESET); 205 MACIO_OUT32(OHARE_FCR, fcr); 206 } 207 UNLOCK(flags); 208 (void)MACIO_IN32(OHARE_FCR); 209 mdelay(15); 210 LOCK(flags); 211 fcr &= ~rmask; 212 MACIO_OUT32(OHARE_FCR, fcr); 213 } 214 if (chan_mask & MACIO_FLAG_SCCA_ON) 215 fcr |= OH_SCCA_IO; 216 if (chan_mask & MACIO_FLAG_SCCB_ON) 217 fcr |= OH_SCCB_IO; 218 MACIO_OUT32(OHARE_FCR, fcr); 219 macio->flags |= chan_mask; 220 UNLOCK(flags); 221 if (param & PMAC_SCC_FLAG_XMON) 222 macio->flags |= MACIO_FLAG_SCC_LOCKED; 223 } else { 224 if (macio->flags & MACIO_FLAG_SCC_LOCKED) 225 return -EPERM; 226 LOCK(flags); 227 fcr = MACIO_IN32(OHARE_FCR); 228 if (chan_mask & MACIO_FLAG_SCCA_ON) 229 fcr &= ~OH_SCCA_IO; 230 if (chan_mask & MACIO_FLAG_SCCB_ON) 231 fcr &= ~OH_SCCB_IO; 232 MACIO_OUT32(OHARE_FCR, fcr); 233 if ((fcr & (OH_SCCA_IO | OH_SCCB_IO)) == 0) { 234 fcr &= ~OH_SCC_ENABLE; 235 if (htw && trans) 236 fcr |= HRW_SCC_TRANS_EN_N; 237 MACIO_OUT32(OHARE_FCR, fcr); 238 } 239 macio->flags &= ~(chan_mask); 240 UNLOCK(flags); 241 mdelay(10); 242 #ifdef CONFIG_ADB_PMU 243 if ((param & 0xfff) == PMAC_SCC_IRDA) 244 pmu_enable_irled(0); 245 #endif /* CONFIG_ADB_PMU */ 246 } 247 return 0; 248 } 249 250 static long ohare_floppy_enable(struct device_node *node, long param, 251 long value) 252 { 253 return simple_feature_tweak(node, macio_ohare, 254 OHARE_FCR, OH_FLOPPY_ENABLE, value); 255 } 256 257 static long ohare_mesh_enable(struct device_node *node, long param, long value) 258 { 259 return simple_feature_tweak(node, macio_ohare, 260 OHARE_FCR, OH_MESH_ENABLE, value); 261 } 262 263 static long ohare_ide_enable(struct device_node *node, long param, long value) 264 { 265 switch(param) { 266 case 0: 267 /* For some reason, setting the bit in set_initial_features() 268 * doesn't stick. I'm still investigating... --BenH. 269 */ 270 if (value) 271 simple_feature_tweak(node, macio_ohare, 272 OHARE_FCR, OH_IOBUS_ENABLE, 1); 273 return simple_feature_tweak(node, macio_ohare, 274 OHARE_FCR, OH_IDE0_ENABLE, value); 275 case 1: 276 return simple_feature_tweak(node, macio_ohare, 277 OHARE_FCR, OH_BAY_IDE_ENABLE, value); 278 default: 279 return -ENODEV; 280 } 281 } 282 283 static long ohare_ide_reset(struct device_node *node, long param, long value) 284 { 285 switch(param) { 286 case 0: 287 return simple_feature_tweak(node, macio_ohare, 288 OHARE_FCR, OH_IDE0_RESET_N, !value); 289 case 1: 290 return simple_feature_tweak(node, macio_ohare, 291 OHARE_FCR, OH_IDE1_RESET_N, !value); 292 default: 293 return -ENODEV; 294 } 295 } 296 297 static long ohare_sleep_state(struct device_node *node, long param, long value) 298 { 299 struct macio_chip* macio = &macio_chips[0]; 300 301 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0) 302 return -EPERM; 303 if (value == 1) { 304 MACIO_BIC(OHARE_FCR, OH_IOBUS_ENABLE); 305 } else if (value == 0) { 306 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE); 307 } 308 309 return 0; 310 } 311 312 static long heathrow_modem_enable(struct device_node *node, long param, 313 long value) 314 { 315 struct macio_chip* macio; 316 u8 gpio; 317 unsigned long flags; 318 319 macio = macio_find(node, macio_unknown); 320 if (!macio) 321 return -ENODEV; 322 gpio = MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1; 323 if (!value) { 324 LOCK(flags); 325 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio); 326 UNLOCK(flags); 327 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET); 328 mdelay(250); 329 } 330 if (pmac_mb.model_id != PMAC_TYPE_YOSEMITE && 331 pmac_mb.model_id != PMAC_TYPE_YIKES) { 332 LOCK(flags); 333 if (value) 334 MACIO_BIC(HEATHROW_FCR, HRW_SCC_TRANS_EN_N); 335 else 336 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N); 337 UNLOCK(flags); 338 (void)MACIO_IN32(HEATHROW_FCR); 339 mdelay(250); 340 } 341 if (value) { 342 LOCK(flags); 343 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1); 344 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET); 345 UNLOCK(flags); mdelay(250); LOCK(flags); 346 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio); 347 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET); 348 UNLOCK(flags); mdelay(250); LOCK(flags); 349 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1); 350 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET); 351 UNLOCK(flags); mdelay(250); 352 } 353 return 0; 354 } 355 356 static long heathrow_floppy_enable(struct device_node *node, long param, 357 long value) 358 { 359 return simple_feature_tweak(node, macio_unknown, 360 HEATHROW_FCR, 361 HRW_SWIM_ENABLE|HRW_BAY_FLOPPY_ENABLE, 362 value); 363 } 364 365 static long heathrow_mesh_enable(struct device_node *node, long param, 366 long value) 367 { 368 struct macio_chip* macio; 369 unsigned long flags; 370 371 macio = macio_find(node, macio_unknown); 372 if (!macio) 373 return -ENODEV; 374 LOCK(flags); 375 /* Set clear mesh cell enable */ 376 if (value) 377 MACIO_BIS(HEATHROW_FCR, HRW_MESH_ENABLE); 378 else 379 MACIO_BIC(HEATHROW_FCR, HRW_MESH_ENABLE); 380 (void)MACIO_IN32(HEATHROW_FCR); 381 udelay(10); 382 /* Set/Clear termination power */ 383 if (value) 384 MACIO_BIC(HEATHROW_MBCR, 0x04000000); 385 else 386 MACIO_BIS(HEATHROW_MBCR, 0x04000000); 387 (void)MACIO_IN32(HEATHROW_MBCR); 388 udelay(10); 389 UNLOCK(flags); 390 391 return 0; 392 } 393 394 static long heathrow_ide_enable(struct device_node *node, long param, 395 long value) 396 { 397 switch(param) { 398 case 0: 399 return simple_feature_tweak(node, macio_unknown, 400 HEATHROW_FCR, HRW_IDE0_ENABLE, value); 401 case 1: 402 return simple_feature_tweak(node, macio_unknown, 403 HEATHROW_FCR, HRW_BAY_IDE_ENABLE, value); 404 default: 405 return -ENODEV; 406 } 407 } 408 409 static long heathrow_ide_reset(struct device_node *node, long param, 410 long value) 411 { 412 switch(param) { 413 case 0: 414 return simple_feature_tweak(node, macio_unknown, 415 HEATHROW_FCR, HRW_IDE0_RESET_N, !value); 416 case 1: 417 return simple_feature_tweak(node, macio_unknown, 418 HEATHROW_FCR, HRW_IDE1_RESET_N, !value); 419 default: 420 return -ENODEV; 421 } 422 } 423 424 static long heathrow_bmac_enable(struct device_node *node, long param, 425 long value) 426 { 427 struct macio_chip* macio; 428 unsigned long flags; 429 430 macio = macio_find(node, 0); 431 if (!macio) 432 return -ENODEV; 433 if (value) { 434 LOCK(flags); 435 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_IO_ENABLE); 436 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_RESET); 437 UNLOCK(flags); 438 (void)MACIO_IN32(HEATHROW_FCR); 439 mdelay(10); 440 LOCK(flags); 441 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_RESET); 442 UNLOCK(flags); 443 (void)MACIO_IN32(HEATHROW_FCR); 444 mdelay(10); 445 } else { 446 LOCK(flags); 447 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE); 448 UNLOCK(flags); 449 } 450 return 0; 451 } 452 453 static long heathrow_sound_enable(struct device_node *node, long param, 454 long value) 455 { 456 struct macio_chip* macio; 457 unsigned long flags; 458 459 /* B&W G3 and Yikes don't support that properly (the 460 * sound appear to never come back after being shut down). 461 */ 462 if (pmac_mb.model_id == PMAC_TYPE_YOSEMITE || 463 pmac_mb.model_id == PMAC_TYPE_YIKES) 464 return 0; 465 466 macio = macio_find(node, 0); 467 if (!macio) 468 return -ENODEV; 469 if (value) { 470 LOCK(flags); 471 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE); 472 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N); 473 UNLOCK(flags); 474 (void)MACIO_IN32(HEATHROW_FCR); 475 } else { 476 LOCK(flags); 477 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N); 478 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE); 479 UNLOCK(flags); 480 } 481 return 0; 482 } 483 484 static u32 save_fcr[6]; 485 static u32 save_mbcr; 486 static struct dbdma_regs save_dbdma[13]; 487 static struct dbdma_regs save_alt_dbdma[13]; 488 489 static void dbdma_save(struct macio_chip *macio, struct dbdma_regs *save) 490 { 491 int i; 492 493 /* Save state & config of DBDMA channels */ 494 for (i = 0; i < 13; i++) { 495 volatile struct dbdma_regs __iomem * chan = (void __iomem *) 496 (macio->base + ((0x8000+i*0x100)>>2)); 497 save[i].cmdptr_hi = in_le32(&chan->cmdptr_hi); 498 save[i].cmdptr = in_le32(&chan->cmdptr); 499 save[i].intr_sel = in_le32(&chan->intr_sel); 500 save[i].br_sel = in_le32(&chan->br_sel); 501 save[i].wait_sel = in_le32(&chan->wait_sel); 502 } 503 } 504 505 static void dbdma_restore(struct macio_chip *macio, struct dbdma_regs *save) 506 { 507 int i; 508 509 /* Save state & config of DBDMA channels */ 510 for (i = 0; i < 13; i++) { 511 volatile struct dbdma_regs __iomem * chan = (void __iomem *) 512 (macio->base + ((0x8000+i*0x100)>>2)); 513 out_le32(&chan->control, (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16); 514 while (in_le32(&chan->status) & ACTIVE) 515 mb(); 516 out_le32(&chan->cmdptr_hi, save[i].cmdptr_hi); 517 out_le32(&chan->cmdptr, save[i].cmdptr); 518 out_le32(&chan->intr_sel, save[i].intr_sel); 519 out_le32(&chan->br_sel, save[i].br_sel); 520 out_le32(&chan->wait_sel, save[i].wait_sel); 521 } 522 } 523 524 static void heathrow_sleep(struct macio_chip *macio, int secondary) 525 { 526 if (secondary) { 527 dbdma_save(macio, save_alt_dbdma); 528 save_fcr[2] = MACIO_IN32(0x38); 529 save_fcr[3] = MACIO_IN32(0x3c); 530 } else { 531 dbdma_save(macio, save_dbdma); 532 save_fcr[0] = MACIO_IN32(0x38); 533 save_fcr[1] = MACIO_IN32(0x3c); 534 save_mbcr = MACIO_IN32(0x34); 535 /* Make sure sound is shut down */ 536 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N); 537 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE); 538 /* This seems to be necessary as well or the fan 539 * keeps coming up and battery drains fast */ 540 MACIO_BIC(HEATHROW_FCR, HRW_IOBUS_ENABLE); 541 MACIO_BIC(HEATHROW_FCR, HRW_IDE0_RESET_N); 542 /* Make sure eth is down even if module or sleep 543 * won't work properly */ 544 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE | HRW_BMAC_RESET); 545 } 546 /* Make sure modem is shut down */ 547 MACIO_OUT8(HRW_GPIO_MODEM_RESET, 548 MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1); 549 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N); 550 MACIO_BIC(HEATHROW_FCR, OH_SCCA_IO|OH_SCCB_IO|HRW_SCC_ENABLE); 551 552 /* Let things settle */ 553 (void)MACIO_IN32(HEATHROW_FCR); 554 } 555 556 static void heathrow_wakeup(struct macio_chip *macio, int secondary) 557 { 558 if (secondary) { 559 MACIO_OUT32(0x38, save_fcr[2]); 560 (void)MACIO_IN32(0x38); 561 mdelay(1); 562 MACIO_OUT32(0x3c, save_fcr[3]); 563 (void)MACIO_IN32(0x38); 564 mdelay(10); 565 dbdma_restore(macio, save_alt_dbdma); 566 } else { 567 MACIO_OUT32(0x38, save_fcr[0] | HRW_IOBUS_ENABLE); 568 (void)MACIO_IN32(0x38); 569 mdelay(1); 570 MACIO_OUT32(0x3c, save_fcr[1]); 571 (void)MACIO_IN32(0x38); 572 mdelay(1); 573 MACIO_OUT32(0x34, save_mbcr); 574 (void)MACIO_IN32(0x38); 575 mdelay(10); 576 dbdma_restore(macio, save_dbdma); 577 } 578 } 579 580 static long heathrow_sleep_state(struct device_node *node, long param, 581 long value) 582 { 583 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0) 584 return -EPERM; 585 if (value == 1) { 586 if (macio_chips[1].type == macio_gatwick) 587 heathrow_sleep(&macio_chips[0], 1); 588 heathrow_sleep(&macio_chips[0], 0); 589 } else if (value == 0) { 590 heathrow_wakeup(&macio_chips[0], 0); 591 if (macio_chips[1].type == macio_gatwick) 592 heathrow_wakeup(&macio_chips[0], 1); 593 } 594 return 0; 595 } 596 597 static long core99_scc_enable(struct device_node *node, long param, long value) 598 { 599 struct macio_chip* macio; 600 unsigned long flags; 601 unsigned long chan_mask; 602 u32 fcr; 603 604 macio = macio_find(node, 0); 605 if (!macio) 606 return -ENODEV; 607 if (of_node_name_eq(node, "ch-a")) 608 chan_mask = MACIO_FLAG_SCCA_ON; 609 else if (of_node_name_eq(node, "ch-b")) 610 chan_mask = MACIO_FLAG_SCCB_ON; 611 else 612 return -ENODEV; 613 614 if (value) { 615 int need_reset_scc = 0; 616 int need_reset_irda = 0; 617 618 LOCK(flags); 619 fcr = MACIO_IN32(KEYLARGO_FCR0); 620 /* Check if scc cell need enabling */ 621 if (!(fcr & KL0_SCC_CELL_ENABLE)) { 622 fcr |= KL0_SCC_CELL_ENABLE; 623 need_reset_scc = 1; 624 } 625 if (chan_mask & MACIO_FLAG_SCCA_ON) { 626 fcr |= KL0_SCCA_ENABLE; 627 /* Don't enable line drivers for I2S modem */ 628 if ((param & 0xfff) == PMAC_SCC_I2S1) 629 fcr &= ~KL0_SCC_A_INTF_ENABLE; 630 else 631 fcr |= KL0_SCC_A_INTF_ENABLE; 632 } 633 if (chan_mask & MACIO_FLAG_SCCB_ON) { 634 fcr |= KL0_SCCB_ENABLE; 635 /* Perform irda specific inits */ 636 if ((param & 0xfff) == PMAC_SCC_IRDA) { 637 fcr &= ~KL0_SCC_B_INTF_ENABLE; 638 fcr |= KL0_IRDA_ENABLE; 639 fcr |= KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE; 640 fcr |= KL0_IRDA_SOURCE1_SEL; 641 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0); 642 fcr &= ~(KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND); 643 need_reset_irda = 1; 644 } else 645 fcr |= KL0_SCC_B_INTF_ENABLE; 646 } 647 MACIO_OUT32(KEYLARGO_FCR0, fcr); 648 macio->flags |= chan_mask; 649 if (need_reset_scc) { 650 MACIO_BIS(KEYLARGO_FCR0, KL0_SCC_RESET); 651 (void)MACIO_IN32(KEYLARGO_FCR0); 652 UNLOCK(flags); 653 mdelay(15); 654 LOCK(flags); 655 MACIO_BIC(KEYLARGO_FCR0, KL0_SCC_RESET); 656 } 657 if (need_reset_irda) { 658 MACIO_BIS(KEYLARGO_FCR0, KL0_IRDA_RESET); 659 (void)MACIO_IN32(KEYLARGO_FCR0); 660 UNLOCK(flags); 661 mdelay(15); 662 LOCK(flags); 663 MACIO_BIC(KEYLARGO_FCR0, KL0_IRDA_RESET); 664 } 665 UNLOCK(flags); 666 if (param & PMAC_SCC_FLAG_XMON) 667 macio->flags |= MACIO_FLAG_SCC_LOCKED; 668 } else { 669 if (macio->flags & MACIO_FLAG_SCC_LOCKED) 670 return -EPERM; 671 LOCK(flags); 672 fcr = MACIO_IN32(KEYLARGO_FCR0); 673 if (chan_mask & MACIO_FLAG_SCCA_ON) 674 fcr &= ~KL0_SCCA_ENABLE; 675 if (chan_mask & MACIO_FLAG_SCCB_ON) { 676 fcr &= ~KL0_SCCB_ENABLE; 677 /* Perform irda specific clears */ 678 if ((param & 0xfff) == PMAC_SCC_IRDA) { 679 fcr &= ~KL0_IRDA_ENABLE; 680 fcr &= ~(KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE); 681 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0); 682 fcr &= ~(KL0_IRDA_SOURCE1_SEL|KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND); 683 } 684 } 685 MACIO_OUT32(KEYLARGO_FCR0, fcr); 686 if ((fcr & (KL0_SCCA_ENABLE | KL0_SCCB_ENABLE)) == 0) { 687 fcr &= ~KL0_SCC_CELL_ENABLE; 688 MACIO_OUT32(KEYLARGO_FCR0, fcr); 689 } 690 macio->flags &= ~(chan_mask); 691 UNLOCK(flags); 692 mdelay(10); 693 } 694 return 0; 695 } 696 697 static long 698 core99_modem_enable(struct device_node *node, long param, long value) 699 { 700 struct macio_chip* macio; 701 u8 gpio; 702 unsigned long flags; 703 704 /* Hack for internal USB modem */ 705 if (node == NULL) { 706 if (macio_chips[0].type != macio_keylargo) 707 return -ENODEV; 708 node = macio_chips[0].of_node; 709 } 710 macio = macio_find(node, 0); 711 if (!macio) 712 return -ENODEV; 713 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET); 714 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE; 715 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA; 716 717 if (!value) { 718 LOCK(flags); 719 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio); 720 UNLOCK(flags); 721 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 722 mdelay(250); 723 } 724 LOCK(flags); 725 if (value) { 726 MACIO_BIC(KEYLARGO_FCR2, KL2_ALT_DATA_OUT); 727 UNLOCK(flags); 728 (void)MACIO_IN32(KEYLARGO_FCR2); 729 mdelay(250); 730 } else { 731 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT); 732 UNLOCK(flags); 733 } 734 if (value) { 735 LOCK(flags); 736 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA); 737 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 738 UNLOCK(flags); mdelay(250); LOCK(flags); 739 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio); 740 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 741 UNLOCK(flags); mdelay(250); LOCK(flags); 742 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA); 743 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 744 UNLOCK(flags); mdelay(250); 745 } 746 return 0; 747 } 748 749 static long 750 pangea_modem_enable(struct device_node *node, long param, long value) 751 { 752 struct macio_chip* macio; 753 u8 gpio; 754 unsigned long flags; 755 756 /* Hack for internal USB modem */ 757 if (node == NULL) { 758 if (macio_chips[0].type != macio_pangea && 759 macio_chips[0].type != macio_intrepid) 760 return -ENODEV; 761 node = macio_chips[0].of_node; 762 } 763 macio = macio_find(node, 0); 764 if (!macio) 765 return -ENODEV; 766 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET); 767 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE; 768 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA; 769 770 if (!value) { 771 LOCK(flags); 772 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio); 773 UNLOCK(flags); 774 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 775 mdelay(250); 776 } 777 LOCK(flags); 778 if (value) { 779 MACIO_OUT8(KL_GPIO_MODEM_POWER, 780 KEYLARGO_GPIO_OUTPUT_ENABLE); 781 UNLOCK(flags); 782 (void)MACIO_IN32(KEYLARGO_FCR2); 783 mdelay(250); 784 } else { 785 MACIO_OUT8(KL_GPIO_MODEM_POWER, 786 KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA); 787 UNLOCK(flags); 788 } 789 if (value) { 790 LOCK(flags); 791 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA); 792 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 793 UNLOCK(flags); mdelay(250); LOCK(flags); 794 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio); 795 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 796 UNLOCK(flags); mdelay(250); LOCK(flags); 797 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA); 798 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 799 UNLOCK(flags); mdelay(250); 800 } 801 return 0; 802 } 803 804 static long 805 core99_ata100_enable(struct device_node *node, long value) 806 { 807 unsigned long flags; 808 struct pci_dev *pdev = NULL; 809 u8 pbus, pid; 810 int rc; 811 812 if (uninorth_rev < 0x24) 813 return -ENODEV; 814 815 LOCK(flags); 816 if (value) 817 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100); 818 else 819 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100); 820 (void)UN_IN(UNI_N_CLOCK_CNTL); 821 UNLOCK(flags); 822 udelay(20); 823 824 if (value) { 825 if (pci_device_from_OF_node(node, &pbus, &pid) == 0) 826 pdev = pci_get_domain_bus_and_slot(0, pbus, pid); 827 if (pdev == NULL) 828 return 0; 829 rc = pci_enable_device(pdev); 830 if (rc == 0) 831 pci_set_master(pdev); 832 pci_dev_put(pdev); 833 if (rc) 834 return rc; 835 } 836 return 0; 837 } 838 839 static long 840 core99_ide_enable(struct device_node *node, long param, long value) 841 { 842 /* Bus ID 0 to 2 are KeyLargo based IDE, busID 3 is U2 843 * based ata-100 844 */ 845 switch(param) { 846 case 0: 847 return simple_feature_tweak(node, macio_unknown, 848 KEYLARGO_FCR1, KL1_EIDE0_ENABLE, value); 849 case 1: 850 return simple_feature_tweak(node, macio_unknown, 851 KEYLARGO_FCR1, KL1_EIDE1_ENABLE, value); 852 case 2: 853 return simple_feature_tweak(node, macio_unknown, 854 KEYLARGO_FCR1, KL1_UIDE_ENABLE, value); 855 case 3: 856 return core99_ata100_enable(node, value); 857 default: 858 return -ENODEV; 859 } 860 } 861 862 static long 863 core99_ide_reset(struct device_node *node, long param, long value) 864 { 865 switch(param) { 866 case 0: 867 return simple_feature_tweak(node, macio_unknown, 868 KEYLARGO_FCR1, KL1_EIDE0_RESET_N, !value); 869 case 1: 870 return simple_feature_tweak(node, macio_unknown, 871 KEYLARGO_FCR1, KL1_EIDE1_RESET_N, !value); 872 case 2: 873 return simple_feature_tweak(node, macio_unknown, 874 KEYLARGO_FCR1, KL1_UIDE_RESET_N, !value); 875 default: 876 return -ENODEV; 877 } 878 } 879 880 static long 881 core99_gmac_enable(struct device_node *node, long param, long value) 882 { 883 unsigned long flags; 884 885 LOCK(flags); 886 if (value) 887 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC); 888 else 889 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC); 890 (void)UN_IN(UNI_N_CLOCK_CNTL); 891 UNLOCK(flags); 892 udelay(20); 893 894 return 0; 895 } 896 897 static long 898 core99_gmac_phy_reset(struct device_node *node, long param, long value) 899 { 900 unsigned long flags; 901 struct macio_chip *macio; 902 903 macio = &macio_chips[0]; 904 if (macio->type != macio_keylargo && macio->type != macio_pangea && 905 macio->type != macio_intrepid) 906 return -ENODEV; 907 908 LOCK(flags); 909 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, KEYLARGO_GPIO_OUTPUT_ENABLE); 910 (void)MACIO_IN8(KL_GPIO_ETH_PHY_RESET); 911 UNLOCK(flags); 912 mdelay(10); 913 LOCK(flags); 914 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, /*KEYLARGO_GPIO_OUTPUT_ENABLE | */ 915 KEYLARGO_GPIO_OUTOUT_DATA); 916 UNLOCK(flags); 917 mdelay(10); 918 919 return 0; 920 } 921 922 static long 923 core99_sound_chip_enable(struct device_node *node, long param, long value) 924 { 925 struct macio_chip* macio; 926 unsigned long flags; 927 928 macio = macio_find(node, 0); 929 if (!macio) 930 return -ENODEV; 931 932 /* Do a better probe code, screamer G4 desktops & 933 * iMacs can do that too, add a recalibrate in 934 * the driver as well 935 */ 936 if (pmac_mb.model_id == PMAC_TYPE_PISMO || 937 pmac_mb.model_id == PMAC_TYPE_TITANIUM) { 938 LOCK(flags); 939 if (value) 940 MACIO_OUT8(KL_GPIO_SOUND_POWER, 941 KEYLARGO_GPIO_OUTPUT_ENABLE | 942 KEYLARGO_GPIO_OUTOUT_DATA); 943 else 944 MACIO_OUT8(KL_GPIO_SOUND_POWER, 945 KEYLARGO_GPIO_OUTPUT_ENABLE); 946 (void)MACIO_IN8(KL_GPIO_SOUND_POWER); 947 UNLOCK(flags); 948 } 949 return 0; 950 } 951 952 static long 953 core99_airport_enable(struct device_node *node, long param, long value) 954 { 955 struct macio_chip* macio; 956 unsigned long flags; 957 int state; 958 959 macio = macio_find(node, 0); 960 if (!macio) 961 return -ENODEV; 962 963 /* Hint: we allow passing of macio itself for the sake of the 964 * sleep code 965 */ 966 if (node != macio->of_node && 967 (!node->parent || node->parent != macio->of_node)) 968 return -ENODEV; 969 state = (macio->flags & MACIO_FLAG_AIRPORT_ON) != 0; 970 if (value == state) 971 return 0; 972 if (value) { 973 /* This code is a reproduction of OF enable-cardslot 974 * and init-wireless methods, slightly hacked until 975 * I got it working. 976 */ 977 LOCK(flags); 978 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 5); 979 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf); 980 UNLOCK(flags); 981 mdelay(10); 982 LOCK(flags); 983 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 4); 984 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf); 985 UNLOCK(flags); 986 987 mdelay(10); 988 989 LOCK(flags); 990 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16); 991 (void)MACIO_IN32(KEYLARGO_FCR2); 992 udelay(10); 993 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xb, 0); 994 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xb); 995 udelay(10); 996 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xa, 0x28); 997 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xa); 998 udelay(10); 999 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xd, 0x28); 1000 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xd); 1001 udelay(10); 1002 MACIO_OUT8(KEYLARGO_GPIO_0+0xd, 0x28); 1003 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xd); 1004 udelay(10); 1005 MACIO_OUT8(KEYLARGO_GPIO_0+0xe, 0x28); 1006 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xe); 1007 UNLOCK(flags); 1008 udelay(10); 1009 MACIO_OUT32(0x1c000, 0); 1010 mdelay(1); 1011 MACIO_OUT8(0x1a3e0, 0x41); 1012 (void)MACIO_IN8(0x1a3e0); 1013 udelay(10); 1014 LOCK(flags); 1015 MACIO_BIS(KEYLARGO_FCR2, KL2_CARDSEL_16); 1016 (void)MACIO_IN32(KEYLARGO_FCR2); 1017 UNLOCK(flags); 1018 mdelay(100); 1019 1020 macio->flags |= MACIO_FLAG_AIRPORT_ON; 1021 } else { 1022 LOCK(flags); 1023 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16); 1024 (void)MACIO_IN32(KEYLARGO_FCR2); 1025 MACIO_OUT8(KL_GPIO_AIRPORT_0, 0); 1026 MACIO_OUT8(KL_GPIO_AIRPORT_1, 0); 1027 MACIO_OUT8(KL_GPIO_AIRPORT_2, 0); 1028 MACIO_OUT8(KL_GPIO_AIRPORT_3, 0); 1029 MACIO_OUT8(KL_GPIO_AIRPORT_4, 0); 1030 (void)MACIO_IN8(KL_GPIO_AIRPORT_4); 1031 UNLOCK(flags); 1032 1033 macio->flags &= ~MACIO_FLAG_AIRPORT_ON; 1034 } 1035 return 0; 1036 } 1037 1038 #ifdef CONFIG_SMP 1039 static long 1040 core99_reset_cpu(struct device_node *node, long param, long value) 1041 { 1042 unsigned int reset_io = 0; 1043 unsigned long flags; 1044 struct macio_chip *macio; 1045 struct device_node *np; 1046 const int dflt_reset_lines[] = { KL_GPIO_RESET_CPU0, 1047 KL_GPIO_RESET_CPU1, 1048 KL_GPIO_RESET_CPU2, 1049 KL_GPIO_RESET_CPU3 }; 1050 1051 macio = &macio_chips[0]; 1052 if (macio->type != macio_keylargo) 1053 return -ENODEV; 1054 1055 for_each_of_cpu_node(np) { 1056 const u32 *num = of_get_property(np, "reg", NULL); 1057 const u32 *rst = of_get_property(np, "soft-reset", NULL); 1058 if (num == NULL || rst == NULL) 1059 continue; 1060 if (param == *num) { 1061 reset_io = *rst; 1062 break; 1063 } 1064 } 1065 if (np == NULL || reset_io == 0) 1066 reset_io = dflt_reset_lines[param]; 1067 1068 LOCK(flags); 1069 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE); 1070 (void)MACIO_IN8(reset_io); 1071 udelay(1); 1072 MACIO_OUT8(reset_io, 0); 1073 (void)MACIO_IN8(reset_io); 1074 UNLOCK(flags); 1075 1076 return 0; 1077 } 1078 #endif /* CONFIG_SMP */ 1079 1080 static long 1081 core99_usb_enable(struct device_node *node, long param, long value) 1082 { 1083 struct macio_chip *macio; 1084 unsigned long flags; 1085 const char *prop; 1086 int number; 1087 u32 reg; 1088 1089 macio = &macio_chips[0]; 1090 if (macio->type != macio_keylargo && macio->type != macio_pangea && 1091 macio->type != macio_intrepid) 1092 return -ENODEV; 1093 1094 prop = of_get_property(node, "AAPL,clock-id", NULL); 1095 if (!prop) 1096 return -ENODEV; 1097 if (strncmp(prop, "usb0u048", 8) == 0) 1098 number = 0; 1099 else if (strncmp(prop, "usb1u148", 8) == 0) 1100 number = 2; 1101 else if (strncmp(prop, "usb2u248", 8) == 0) 1102 number = 4; 1103 else 1104 return -ENODEV; 1105 1106 /* Sorry for the brute-force locking, but this is only used during 1107 * sleep and the timing seem to be critical 1108 */ 1109 LOCK(flags); 1110 if (value) { 1111 /* Turn ON */ 1112 if (number == 0) { 1113 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1)); 1114 (void)MACIO_IN32(KEYLARGO_FCR0); 1115 UNLOCK(flags); 1116 mdelay(1); 1117 LOCK(flags); 1118 MACIO_BIS(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE); 1119 } else if (number == 2) { 1120 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1)); 1121 UNLOCK(flags); 1122 (void)MACIO_IN32(KEYLARGO_FCR0); 1123 mdelay(1); 1124 LOCK(flags); 1125 MACIO_BIS(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE); 1126 } else if (number == 4) { 1127 MACIO_BIC(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1)); 1128 UNLOCK(flags); 1129 (void)MACIO_IN32(KEYLARGO_FCR1); 1130 mdelay(1); 1131 LOCK(flags); 1132 MACIO_BIS(KEYLARGO_FCR1, KL1_USB2_CELL_ENABLE); 1133 } 1134 if (number < 4) { 1135 reg = MACIO_IN32(KEYLARGO_FCR4); 1136 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) | 1137 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number)); 1138 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) | 1139 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1)); 1140 MACIO_OUT32(KEYLARGO_FCR4, reg); 1141 (void)MACIO_IN32(KEYLARGO_FCR4); 1142 udelay(10); 1143 } else { 1144 reg = MACIO_IN32(KEYLARGO_FCR3); 1145 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) | 1146 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0)); 1147 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) | 1148 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1)); 1149 MACIO_OUT32(KEYLARGO_FCR3, reg); 1150 (void)MACIO_IN32(KEYLARGO_FCR3); 1151 udelay(10); 1152 } 1153 if (macio->type == macio_intrepid) { 1154 /* wait for clock stopped bits to clear */ 1155 u32 test0 = 0, test1 = 0; 1156 u32 status0, status1; 1157 int timeout = 1000; 1158 1159 UNLOCK(flags); 1160 switch (number) { 1161 case 0: 1162 test0 = UNI_N_CLOCK_STOPPED_USB0; 1163 test1 = UNI_N_CLOCK_STOPPED_USB0PCI; 1164 break; 1165 case 2: 1166 test0 = UNI_N_CLOCK_STOPPED_USB1; 1167 test1 = UNI_N_CLOCK_STOPPED_USB1PCI; 1168 break; 1169 case 4: 1170 test0 = UNI_N_CLOCK_STOPPED_USB2; 1171 test1 = UNI_N_CLOCK_STOPPED_USB2PCI; 1172 break; 1173 } 1174 do { 1175 if (--timeout <= 0) { 1176 printk(KERN_ERR "core99_usb_enable: " 1177 "Timeout waiting for clocks\n"); 1178 break; 1179 } 1180 mdelay(1); 1181 status0 = UN_IN(UNI_N_CLOCK_STOP_STATUS0); 1182 status1 = UN_IN(UNI_N_CLOCK_STOP_STATUS1); 1183 } while ((status0 & test0) | (status1 & test1)); 1184 LOCK(flags); 1185 } 1186 } else { 1187 /* Turn OFF */ 1188 if (number < 4) { 1189 reg = MACIO_IN32(KEYLARGO_FCR4); 1190 reg |= KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) | 1191 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number); 1192 reg |= KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) | 1193 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1); 1194 MACIO_OUT32(KEYLARGO_FCR4, reg); 1195 (void)MACIO_IN32(KEYLARGO_FCR4); 1196 udelay(1); 1197 } else { 1198 reg = MACIO_IN32(KEYLARGO_FCR3); 1199 reg |= KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) | 1200 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0); 1201 reg |= KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) | 1202 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1); 1203 MACIO_OUT32(KEYLARGO_FCR3, reg); 1204 (void)MACIO_IN32(KEYLARGO_FCR3); 1205 udelay(1); 1206 } 1207 if (number == 0) { 1208 if (macio->type != macio_intrepid) 1209 MACIO_BIC(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE); 1210 (void)MACIO_IN32(KEYLARGO_FCR0); 1211 udelay(1); 1212 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1)); 1213 (void)MACIO_IN32(KEYLARGO_FCR0); 1214 } else if (number == 2) { 1215 if (macio->type != macio_intrepid) 1216 MACIO_BIC(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE); 1217 (void)MACIO_IN32(KEYLARGO_FCR0); 1218 udelay(1); 1219 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1)); 1220 (void)MACIO_IN32(KEYLARGO_FCR0); 1221 } else if (number == 4) { 1222 udelay(1); 1223 MACIO_BIS(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1)); 1224 (void)MACIO_IN32(KEYLARGO_FCR1); 1225 } 1226 udelay(1); 1227 } 1228 UNLOCK(flags); 1229 1230 return 0; 1231 } 1232 1233 static long 1234 core99_firewire_enable(struct device_node *node, long param, long value) 1235 { 1236 unsigned long flags; 1237 struct macio_chip *macio; 1238 1239 macio = &macio_chips[0]; 1240 if (macio->type != macio_keylargo && macio->type != macio_pangea && 1241 macio->type != macio_intrepid) 1242 return -ENODEV; 1243 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED)) 1244 return -ENODEV; 1245 1246 LOCK(flags); 1247 if (value) { 1248 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW); 1249 (void)UN_IN(UNI_N_CLOCK_CNTL); 1250 } else { 1251 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW); 1252 (void)UN_IN(UNI_N_CLOCK_CNTL); 1253 } 1254 UNLOCK(flags); 1255 mdelay(1); 1256 1257 return 0; 1258 } 1259 1260 static long 1261 core99_firewire_cable_power(struct device_node *node, long param, long value) 1262 { 1263 unsigned long flags; 1264 struct macio_chip *macio; 1265 1266 /* Trick: we allow NULL node */ 1267 if ((pmac_mb.board_flags & PMAC_MB_HAS_FW_POWER) == 0) 1268 return -ENODEV; 1269 macio = &macio_chips[0]; 1270 if (macio->type != macio_keylargo && macio->type != macio_pangea && 1271 macio->type != macio_intrepid) 1272 return -ENODEV; 1273 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED)) 1274 return -ENODEV; 1275 1276 LOCK(flags); 1277 if (value) { 1278 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 0); 1279 MACIO_IN8(KL_GPIO_FW_CABLE_POWER); 1280 udelay(10); 1281 } else { 1282 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 4); 1283 MACIO_IN8(KL_GPIO_FW_CABLE_POWER); udelay(10); 1284 } 1285 UNLOCK(flags); 1286 mdelay(1); 1287 1288 return 0; 1289 } 1290 1291 static long 1292 intrepid_aack_delay_enable(struct device_node *node, long param, long value) 1293 { 1294 unsigned long flags; 1295 1296 if (uninorth_rev < 0xd2) 1297 return -ENODEV; 1298 1299 LOCK(flags); 1300 if (param) 1301 UN_BIS(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE); 1302 else 1303 UN_BIC(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE); 1304 UNLOCK(flags); 1305 1306 return 0; 1307 } 1308 1309 1310 #endif /* CONFIG_PPC64 */ 1311 1312 static long 1313 core99_read_gpio(struct device_node *node, long param, long value) 1314 { 1315 struct macio_chip *macio = &macio_chips[0]; 1316 1317 return MACIO_IN8(param); 1318 } 1319 1320 1321 static long 1322 core99_write_gpio(struct device_node *node, long param, long value) 1323 { 1324 struct macio_chip *macio = &macio_chips[0]; 1325 1326 MACIO_OUT8(param, (u8)(value & 0xff)); 1327 return 0; 1328 } 1329 1330 #ifdef CONFIG_PPC64 1331 static long g5_gmac_enable(struct device_node *node, long param, long value) 1332 { 1333 struct macio_chip *macio = &macio_chips[0]; 1334 unsigned long flags; 1335 1336 if (node == NULL) 1337 return -ENODEV; 1338 1339 LOCK(flags); 1340 if (value) { 1341 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE); 1342 mb(); 1343 k2_skiplist[0] = NULL; 1344 } else { 1345 k2_skiplist[0] = node; 1346 mb(); 1347 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE); 1348 } 1349 1350 UNLOCK(flags); 1351 mdelay(1); 1352 1353 return 0; 1354 } 1355 1356 static long g5_fw_enable(struct device_node *node, long param, long value) 1357 { 1358 struct macio_chip *macio = &macio_chips[0]; 1359 unsigned long flags; 1360 1361 if (node == NULL) 1362 return -ENODEV; 1363 1364 LOCK(flags); 1365 if (value) { 1366 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE); 1367 mb(); 1368 k2_skiplist[1] = NULL; 1369 } else { 1370 k2_skiplist[1] = node; 1371 mb(); 1372 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE); 1373 } 1374 1375 UNLOCK(flags); 1376 mdelay(1); 1377 1378 return 0; 1379 } 1380 1381 static long g5_mpic_enable(struct device_node *node, long param, long value) 1382 { 1383 unsigned long flags; 1384 struct device_node *parent = of_get_parent(node); 1385 int is_u3; 1386 1387 if (parent == NULL) 1388 return 0; 1389 is_u3 = of_node_name_eq(parent, "u3") || of_node_name_eq(parent, "u4"); 1390 of_node_put(parent); 1391 if (!is_u3) 1392 return 0; 1393 1394 LOCK(flags); 1395 UN_BIS(U3_TOGGLE_REG, U3_MPIC_RESET | U3_MPIC_OUTPUT_ENABLE); 1396 UNLOCK(flags); 1397 1398 return 0; 1399 } 1400 1401 static long g5_eth_phy_reset(struct device_node *node, long param, long value) 1402 { 1403 struct macio_chip *macio = &macio_chips[0]; 1404 struct device_node *phy; 1405 int need_reset; 1406 1407 /* 1408 * We must not reset the combo PHYs, only the BCM5221 found in 1409 * the iMac G5. 1410 */ 1411 phy = of_get_next_child(node, NULL); 1412 if (!phy) 1413 return -ENODEV; 1414 need_reset = of_device_is_compatible(phy, "B5221"); 1415 of_node_put(phy); 1416 if (!need_reset) 1417 return 0; 1418 1419 /* PHY reset is GPIO 29, not in device-tree unfortunately */ 1420 MACIO_OUT8(K2_GPIO_EXTINT_0 + 29, 1421 KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA); 1422 /* Thankfully, this is now always called at a time when we can 1423 * schedule by sungem. 1424 */ 1425 msleep(10); 1426 MACIO_OUT8(K2_GPIO_EXTINT_0 + 29, 0); 1427 1428 return 0; 1429 } 1430 1431 static long g5_i2s_enable(struct device_node *node, long param, long value) 1432 { 1433 /* Very crude implementation for now */ 1434 struct macio_chip *macio = &macio_chips[0]; 1435 unsigned long flags; 1436 int cell; 1437 u32 fcrs[3][3] = { 1438 { 0, 1439 K2_FCR1_I2S0_CELL_ENABLE | 1440 K2_FCR1_I2S0_CLK_ENABLE_BIT | K2_FCR1_I2S0_ENABLE, 1441 KL3_I2S0_CLK18_ENABLE 1442 }, 1443 { KL0_SCC_A_INTF_ENABLE, 1444 K2_FCR1_I2S1_CELL_ENABLE | 1445 K2_FCR1_I2S1_CLK_ENABLE_BIT | K2_FCR1_I2S1_ENABLE, 1446 KL3_I2S1_CLK18_ENABLE 1447 }, 1448 { KL0_SCC_B_INTF_ENABLE, 1449 SH_FCR1_I2S2_CELL_ENABLE | 1450 SH_FCR1_I2S2_CLK_ENABLE_BIT | SH_FCR1_I2S2_ENABLE, 1451 SH_FCR3_I2S2_CLK18_ENABLE 1452 }, 1453 }; 1454 1455 if (macio->type != macio_keylargo2 && macio->type != macio_shasta) 1456 return -ENODEV; 1457 if (strncmp(node->name, "i2s-", 4)) 1458 return -ENODEV; 1459 cell = node->name[4] - 'a'; 1460 switch(cell) { 1461 case 0: 1462 case 1: 1463 break; 1464 case 2: 1465 if (macio->type == macio_shasta) 1466 break; 1467 fallthrough; 1468 default: 1469 return -ENODEV; 1470 } 1471 1472 LOCK(flags); 1473 if (value) { 1474 MACIO_BIC(KEYLARGO_FCR0, fcrs[cell][0]); 1475 MACIO_BIS(KEYLARGO_FCR1, fcrs[cell][1]); 1476 MACIO_BIS(KEYLARGO_FCR3, fcrs[cell][2]); 1477 } else { 1478 MACIO_BIC(KEYLARGO_FCR3, fcrs[cell][2]); 1479 MACIO_BIC(KEYLARGO_FCR1, fcrs[cell][1]); 1480 MACIO_BIS(KEYLARGO_FCR0, fcrs[cell][0]); 1481 } 1482 udelay(10); 1483 UNLOCK(flags); 1484 1485 return 0; 1486 } 1487 1488 1489 #ifdef CONFIG_SMP 1490 static long g5_reset_cpu(struct device_node *node, long param, long value) 1491 { 1492 unsigned int reset_io = 0; 1493 unsigned long flags; 1494 struct macio_chip *macio; 1495 struct device_node *np; 1496 1497 macio = &macio_chips[0]; 1498 if (macio->type != macio_keylargo2 && macio->type != macio_shasta) 1499 return -ENODEV; 1500 1501 for_each_of_cpu_node(np) { 1502 const u32 *num = of_get_property(np, "reg", NULL); 1503 const u32 *rst = of_get_property(np, "soft-reset", NULL); 1504 if (num == NULL || rst == NULL) 1505 continue; 1506 if (param == *num) { 1507 reset_io = *rst; 1508 break; 1509 } 1510 } 1511 if (np == NULL || reset_io == 0) 1512 return -ENODEV; 1513 1514 LOCK(flags); 1515 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE); 1516 (void)MACIO_IN8(reset_io); 1517 udelay(1); 1518 MACIO_OUT8(reset_io, 0); 1519 (void)MACIO_IN8(reset_io); 1520 UNLOCK(flags); 1521 1522 return 0; 1523 } 1524 #endif /* CONFIG_SMP */ 1525 1526 /* 1527 * This can be called from pmac_smp so isn't static 1528 * 1529 * This takes the second CPU off the bus on dual CPU machines 1530 * running UP 1531 */ 1532 void __init g5_phy_disable_cpu1(void) 1533 { 1534 if (uninorth_maj == 3) 1535 UN_OUT(U3_API_PHY_CONFIG_1, 0); 1536 } 1537 #endif /* CONFIG_PPC64 */ 1538 1539 #ifndef CONFIG_PPC64 1540 1541 1542 #ifdef CONFIG_PM 1543 static u32 save_gpio_levels[2]; 1544 static u8 save_gpio_extint[KEYLARGO_GPIO_EXTINT_CNT]; 1545 static u8 save_gpio_normal[KEYLARGO_GPIO_CNT]; 1546 static u32 save_unin_clock_ctl; 1547 1548 static void keylargo_shutdown(struct macio_chip *macio, int sleep_mode) 1549 { 1550 u32 temp; 1551 1552 if (sleep_mode) { 1553 mdelay(1); 1554 MACIO_BIS(KEYLARGO_FCR0, KL0_USB_REF_SUSPEND); 1555 (void)MACIO_IN32(KEYLARGO_FCR0); 1556 mdelay(1); 1557 } 1558 1559 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE | 1560 KL0_SCC_CELL_ENABLE | 1561 KL0_IRDA_ENABLE | KL0_IRDA_CLK32_ENABLE | 1562 KL0_IRDA_CLK19_ENABLE); 1563 1564 MACIO_BIC(KEYLARGO_MBCR, KL_MBCR_MB0_DEV_MASK); 1565 MACIO_BIS(KEYLARGO_MBCR, KL_MBCR_MB0_IDE_ENABLE); 1566 1567 MACIO_BIC(KEYLARGO_FCR1, 1568 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT | 1569 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE | 1570 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT | 1571 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE | 1572 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE | 1573 KL1_EIDE0_ENABLE | KL1_EIDE0_RESET_N | 1574 KL1_EIDE1_ENABLE | KL1_EIDE1_RESET_N | 1575 KL1_UIDE_ENABLE); 1576 1577 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT); 1578 MACIO_BIC(KEYLARGO_FCR2, KL2_IOBUS_ENABLE); 1579 1580 temp = MACIO_IN32(KEYLARGO_FCR3); 1581 if (macio->rev >= 2) { 1582 temp |= KL3_SHUTDOWN_PLL2X; 1583 if (sleep_mode) 1584 temp |= KL3_SHUTDOWN_PLL_TOTAL; 1585 } 1586 1587 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 | 1588 KL3_SHUTDOWN_PLLKW35; 1589 if (sleep_mode) 1590 temp |= KL3_SHUTDOWN_PLLKW12; 1591 temp &= ~(KL3_CLK66_ENABLE | KL3_CLK49_ENABLE | KL3_CLK45_ENABLE 1592 | KL3_CLK31_ENABLE | KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE); 1593 if (sleep_mode) 1594 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_VIA_CLK16_ENABLE); 1595 MACIO_OUT32(KEYLARGO_FCR3, temp); 1596 1597 /* Flush posted writes & wait a bit */ 1598 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1); 1599 } 1600 1601 static void pangea_shutdown(struct macio_chip *macio, int sleep_mode) 1602 { 1603 u32 temp; 1604 1605 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE | 1606 KL0_SCC_CELL_ENABLE | 1607 KL0_USB0_CELL_ENABLE | KL0_USB1_CELL_ENABLE); 1608 1609 MACIO_BIC(KEYLARGO_FCR1, 1610 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT | 1611 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE | 1612 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT | 1613 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE | 1614 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE | 1615 KL1_UIDE_ENABLE); 1616 if (pmac_mb.board_flags & PMAC_MB_MOBILE) 1617 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N); 1618 1619 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT); 1620 1621 temp = MACIO_IN32(KEYLARGO_FCR3); 1622 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 | 1623 KL3_SHUTDOWN_PLLKW35; 1624 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE | KL3_CLK31_ENABLE 1625 | KL3_I2S0_CLK18_ENABLE | KL3_I2S1_CLK18_ENABLE); 1626 if (sleep_mode) 1627 temp &= ~(KL3_VIA_CLK16_ENABLE | KL3_TIMER_CLK18_ENABLE); 1628 MACIO_OUT32(KEYLARGO_FCR3, temp); 1629 1630 /* Flush posted writes & wait a bit */ 1631 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1); 1632 } 1633 1634 static void intrepid_shutdown(struct macio_chip *macio, int sleep_mode) 1635 { 1636 u32 temp; 1637 1638 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE | 1639 KL0_SCC_CELL_ENABLE); 1640 1641 MACIO_BIC(KEYLARGO_FCR1, 1642 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT | 1643 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE | 1644 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE | 1645 KL1_EIDE0_ENABLE); 1646 if (pmac_mb.board_flags & PMAC_MB_MOBILE) 1647 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N); 1648 1649 temp = MACIO_IN32(KEYLARGO_FCR3); 1650 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE | 1651 KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE); 1652 if (sleep_mode) 1653 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_IT_VIA_CLK32_ENABLE); 1654 MACIO_OUT32(KEYLARGO_FCR3, temp); 1655 1656 /* Flush posted writes & wait a bit */ 1657 (void)MACIO_IN32(KEYLARGO_FCR0); 1658 mdelay(10); 1659 } 1660 1661 1662 static int 1663 core99_sleep(void) 1664 { 1665 struct macio_chip *macio; 1666 int i; 1667 1668 macio = &macio_chips[0]; 1669 if (macio->type != macio_keylargo && macio->type != macio_pangea && 1670 macio->type != macio_intrepid) 1671 return -ENODEV; 1672 1673 /* We power off the wireless slot in case it was not done 1674 * by the driver. We don't power it on automatically however 1675 */ 1676 if (macio->flags & MACIO_FLAG_AIRPORT_ON) 1677 core99_airport_enable(macio->of_node, 0, 0); 1678 1679 /* We power off the FW cable. Should be done by the driver... */ 1680 if (macio->flags & MACIO_FLAG_FW_SUPPORTED) { 1681 core99_firewire_enable(NULL, 0, 0); 1682 core99_firewire_cable_power(NULL, 0, 0); 1683 } 1684 1685 /* We make sure int. modem is off (in case driver lost it) */ 1686 if (macio->type == macio_keylargo) 1687 core99_modem_enable(macio->of_node, 0, 0); 1688 else 1689 pangea_modem_enable(macio->of_node, 0, 0); 1690 1691 /* We make sure the sound is off as well */ 1692 core99_sound_chip_enable(macio->of_node, 0, 0); 1693 1694 /* 1695 * Save various bits of KeyLargo 1696 */ 1697 1698 /* Save the state of the various GPIOs */ 1699 save_gpio_levels[0] = MACIO_IN32(KEYLARGO_GPIO_LEVELS0); 1700 save_gpio_levels[1] = MACIO_IN32(KEYLARGO_GPIO_LEVELS1); 1701 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++) 1702 save_gpio_extint[i] = MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+i); 1703 for (i=0; i<KEYLARGO_GPIO_CNT; i++) 1704 save_gpio_normal[i] = MACIO_IN8(KEYLARGO_GPIO_0+i); 1705 1706 /* Save the FCRs */ 1707 if (macio->type == macio_keylargo) 1708 save_mbcr = MACIO_IN32(KEYLARGO_MBCR); 1709 save_fcr[0] = MACIO_IN32(KEYLARGO_FCR0); 1710 save_fcr[1] = MACIO_IN32(KEYLARGO_FCR1); 1711 save_fcr[2] = MACIO_IN32(KEYLARGO_FCR2); 1712 save_fcr[3] = MACIO_IN32(KEYLARGO_FCR3); 1713 save_fcr[4] = MACIO_IN32(KEYLARGO_FCR4); 1714 if (macio->type == macio_pangea || macio->type == macio_intrepid) 1715 save_fcr[5] = MACIO_IN32(KEYLARGO_FCR5); 1716 1717 /* Save state & config of DBDMA channels */ 1718 dbdma_save(macio, save_dbdma); 1719 1720 /* 1721 * Turn off as much as we can 1722 */ 1723 if (macio->type == macio_pangea) 1724 pangea_shutdown(macio, 1); 1725 else if (macio->type == macio_intrepid) 1726 intrepid_shutdown(macio, 1); 1727 else if (macio->type == macio_keylargo) 1728 keylargo_shutdown(macio, 1); 1729 1730 /* 1731 * Put the host bridge to sleep 1732 */ 1733 1734 save_unin_clock_ctl = UN_IN(UNI_N_CLOCK_CNTL); 1735 /* Note: do not switch GMAC off, driver does it when necessary, WOL must keep it 1736 * enabled ! 1737 */ 1738 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl & 1739 ~(/*UNI_N_CLOCK_CNTL_GMAC|*/UNI_N_CLOCK_CNTL_FW/*|UNI_N_CLOCK_CNTL_PCI*/)); 1740 udelay(100); 1741 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING); 1742 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_SLEEP); 1743 mdelay(10); 1744 1745 /* 1746 * FIXME: A bit of black magic with OpenPIC (don't ask me why) 1747 */ 1748 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) { 1749 MACIO_BIS(0x506e0, 0x00400000); 1750 MACIO_BIS(0x506e0, 0x80000000); 1751 } 1752 return 0; 1753 } 1754 1755 static int 1756 core99_wake_up(void) 1757 { 1758 struct macio_chip *macio; 1759 int i; 1760 1761 macio = &macio_chips[0]; 1762 if (macio->type != macio_keylargo && macio->type != macio_pangea && 1763 macio->type != macio_intrepid) 1764 return -ENODEV; 1765 1766 /* 1767 * Wakeup the host bridge 1768 */ 1769 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL); 1770 udelay(10); 1771 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING); 1772 udelay(10); 1773 1774 /* 1775 * Restore KeyLargo 1776 */ 1777 1778 if (macio->type == macio_keylargo) { 1779 MACIO_OUT32(KEYLARGO_MBCR, save_mbcr); 1780 (void)MACIO_IN32(KEYLARGO_MBCR); udelay(10); 1781 } 1782 MACIO_OUT32(KEYLARGO_FCR0, save_fcr[0]); 1783 (void)MACIO_IN32(KEYLARGO_FCR0); udelay(10); 1784 MACIO_OUT32(KEYLARGO_FCR1, save_fcr[1]); 1785 (void)MACIO_IN32(KEYLARGO_FCR1); udelay(10); 1786 MACIO_OUT32(KEYLARGO_FCR2, save_fcr[2]); 1787 (void)MACIO_IN32(KEYLARGO_FCR2); udelay(10); 1788 MACIO_OUT32(KEYLARGO_FCR3, save_fcr[3]); 1789 (void)MACIO_IN32(KEYLARGO_FCR3); udelay(10); 1790 MACIO_OUT32(KEYLARGO_FCR4, save_fcr[4]); 1791 (void)MACIO_IN32(KEYLARGO_FCR4); udelay(10); 1792 if (macio->type == macio_pangea || macio->type == macio_intrepid) { 1793 MACIO_OUT32(KEYLARGO_FCR5, save_fcr[5]); 1794 (void)MACIO_IN32(KEYLARGO_FCR5); udelay(10); 1795 } 1796 1797 dbdma_restore(macio, save_dbdma); 1798 1799 MACIO_OUT32(KEYLARGO_GPIO_LEVELS0, save_gpio_levels[0]); 1800 MACIO_OUT32(KEYLARGO_GPIO_LEVELS1, save_gpio_levels[1]); 1801 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++) 1802 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+i, save_gpio_extint[i]); 1803 for (i=0; i<KEYLARGO_GPIO_CNT; i++) 1804 MACIO_OUT8(KEYLARGO_GPIO_0+i, save_gpio_normal[i]); 1805 1806 /* FIXME more black magic with OpenPIC ... */ 1807 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) { 1808 MACIO_BIC(0x506e0, 0x00400000); 1809 MACIO_BIC(0x506e0, 0x80000000); 1810 } 1811 1812 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl); 1813 udelay(100); 1814 1815 return 0; 1816 } 1817 1818 #endif /* CONFIG_PM */ 1819 1820 static long 1821 core99_sleep_state(struct device_node *node, long param, long value) 1822 { 1823 /* Param == 1 means to enter the "fake sleep" mode that is 1824 * used for CPU speed switch 1825 */ 1826 if (param == 1) { 1827 if (value == 1) { 1828 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING); 1829 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_IDLE2); 1830 } else { 1831 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL); 1832 udelay(10); 1833 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING); 1834 udelay(10); 1835 } 1836 return 0; 1837 } 1838 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0) 1839 return -EPERM; 1840 1841 #ifdef CONFIG_PM 1842 if (value == 1) 1843 return core99_sleep(); 1844 else if (value == 0) 1845 return core99_wake_up(); 1846 1847 #endif /* CONFIG_PM */ 1848 return 0; 1849 } 1850 1851 #endif /* CONFIG_PPC64 */ 1852 1853 static long 1854 generic_dev_can_wake(struct device_node *node, long param, long value) 1855 { 1856 /* Todo: eventually check we are really dealing with on-board 1857 * video device ... 1858 */ 1859 1860 if (pmac_mb.board_flags & PMAC_MB_MAY_SLEEP) 1861 pmac_mb.board_flags |= PMAC_MB_CAN_SLEEP; 1862 return 0; 1863 } 1864 1865 static long generic_get_mb_info(struct device_node *node, long param, long value) 1866 { 1867 switch(param) { 1868 case PMAC_MB_INFO_MODEL: 1869 return pmac_mb.model_id; 1870 case PMAC_MB_INFO_FLAGS: 1871 return pmac_mb.board_flags; 1872 case PMAC_MB_INFO_NAME: 1873 /* hack hack hack... but should work */ 1874 *((const char **)value) = pmac_mb.model_name; 1875 return 0; 1876 } 1877 return -EINVAL; 1878 } 1879 1880 1881 /* 1882 * Table definitions 1883 */ 1884 1885 /* Used on any machine 1886 */ 1887 static struct feature_table_entry any_features[] = { 1888 { PMAC_FTR_GET_MB_INFO, generic_get_mb_info }, 1889 { PMAC_FTR_DEVICE_CAN_WAKE, generic_dev_can_wake }, 1890 { 0, NULL } 1891 }; 1892 1893 #ifndef CONFIG_PPC64 1894 1895 /* OHare based motherboards. Currently, we only use these on the 1896 * 2400,3400 and 3500 series powerbooks. Some older desktops seem 1897 * to have issues with turning on/off those asic cells 1898 */ 1899 static struct feature_table_entry ohare_features[] = { 1900 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable }, 1901 { PMAC_FTR_SWIM3_ENABLE, ohare_floppy_enable }, 1902 { PMAC_FTR_MESH_ENABLE, ohare_mesh_enable }, 1903 { PMAC_FTR_IDE_ENABLE, ohare_ide_enable}, 1904 { PMAC_FTR_IDE_RESET, ohare_ide_reset}, 1905 { PMAC_FTR_SLEEP_STATE, ohare_sleep_state }, 1906 { 0, NULL } 1907 }; 1908 1909 /* Heathrow desktop machines (Beige G3). 1910 * Separated as some features couldn't be properly tested 1911 * and the serial port control bits appear to confuse it. 1912 */ 1913 static struct feature_table_entry heathrow_desktop_features[] = { 1914 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable }, 1915 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable }, 1916 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable }, 1917 { PMAC_FTR_IDE_RESET, heathrow_ide_reset }, 1918 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable }, 1919 { 0, NULL } 1920 }; 1921 1922 /* Heathrow based laptop, that is the Wallstreet and mainstreet 1923 * powerbooks. 1924 */ 1925 static struct feature_table_entry heathrow_laptop_features[] = { 1926 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable }, 1927 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable }, 1928 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable }, 1929 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable }, 1930 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable }, 1931 { PMAC_FTR_IDE_RESET, heathrow_ide_reset }, 1932 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable }, 1933 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable }, 1934 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state }, 1935 { 0, NULL } 1936 }; 1937 1938 /* Paddington based machines 1939 * The lombard (101) powerbook, first iMac models, B&W G3 and Yikes G4. 1940 */ 1941 static struct feature_table_entry paddington_features[] = { 1942 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable }, 1943 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable }, 1944 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable }, 1945 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable }, 1946 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable }, 1947 { PMAC_FTR_IDE_RESET, heathrow_ide_reset }, 1948 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable }, 1949 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable }, 1950 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state }, 1951 { 0, NULL } 1952 }; 1953 1954 /* Core99 & MacRISC 2 machines (all machines released since the 1955 * iBook (included), that is all AGP machines, except pangea 1956 * chipset. The pangea chipset is the "combo" UniNorth/KeyLargo 1957 * used on iBook2 & iMac "flow power". 1958 */ 1959 static struct feature_table_entry core99_features[] = { 1960 { PMAC_FTR_SCC_ENABLE, core99_scc_enable }, 1961 { PMAC_FTR_MODEM_ENABLE, core99_modem_enable }, 1962 { PMAC_FTR_IDE_ENABLE, core99_ide_enable }, 1963 { PMAC_FTR_IDE_RESET, core99_ide_reset }, 1964 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable }, 1965 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset }, 1966 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable }, 1967 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable }, 1968 { PMAC_FTR_USB_ENABLE, core99_usb_enable }, 1969 { PMAC_FTR_1394_ENABLE, core99_firewire_enable }, 1970 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power }, 1971 #ifdef CONFIG_PM 1972 { PMAC_FTR_SLEEP_STATE, core99_sleep_state }, 1973 #endif 1974 #ifdef CONFIG_SMP 1975 { PMAC_FTR_RESET_CPU, core99_reset_cpu }, 1976 #endif /* CONFIG_SMP */ 1977 { PMAC_FTR_READ_GPIO, core99_read_gpio }, 1978 { PMAC_FTR_WRITE_GPIO, core99_write_gpio }, 1979 { 0, NULL } 1980 }; 1981 1982 /* RackMac 1983 */ 1984 static struct feature_table_entry rackmac_features[] = { 1985 { PMAC_FTR_SCC_ENABLE, core99_scc_enable }, 1986 { PMAC_FTR_IDE_ENABLE, core99_ide_enable }, 1987 { PMAC_FTR_IDE_RESET, core99_ide_reset }, 1988 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable }, 1989 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset }, 1990 { PMAC_FTR_USB_ENABLE, core99_usb_enable }, 1991 { PMAC_FTR_1394_ENABLE, core99_firewire_enable }, 1992 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power }, 1993 { PMAC_FTR_SLEEP_STATE, core99_sleep_state }, 1994 #ifdef CONFIG_SMP 1995 { PMAC_FTR_RESET_CPU, core99_reset_cpu }, 1996 #endif /* CONFIG_SMP */ 1997 { PMAC_FTR_READ_GPIO, core99_read_gpio }, 1998 { PMAC_FTR_WRITE_GPIO, core99_write_gpio }, 1999 { 0, NULL } 2000 }; 2001 2002 /* Pangea features 2003 */ 2004 static struct feature_table_entry pangea_features[] = { 2005 { PMAC_FTR_SCC_ENABLE, core99_scc_enable }, 2006 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable }, 2007 { PMAC_FTR_IDE_ENABLE, core99_ide_enable }, 2008 { PMAC_FTR_IDE_RESET, core99_ide_reset }, 2009 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable }, 2010 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset }, 2011 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable }, 2012 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable }, 2013 { PMAC_FTR_USB_ENABLE, core99_usb_enable }, 2014 { PMAC_FTR_1394_ENABLE, core99_firewire_enable }, 2015 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power }, 2016 { PMAC_FTR_SLEEP_STATE, core99_sleep_state }, 2017 { PMAC_FTR_READ_GPIO, core99_read_gpio }, 2018 { PMAC_FTR_WRITE_GPIO, core99_write_gpio }, 2019 { 0, NULL } 2020 }; 2021 2022 /* Intrepid features 2023 */ 2024 static struct feature_table_entry intrepid_features[] = { 2025 { PMAC_FTR_SCC_ENABLE, core99_scc_enable }, 2026 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable }, 2027 { PMAC_FTR_IDE_ENABLE, core99_ide_enable }, 2028 { PMAC_FTR_IDE_RESET, core99_ide_reset }, 2029 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable }, 2030 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset }, 2031 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable }, 2032 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable }, 2033 { PMAC_FTR_USB_ENABLE, core99_usb_enable }, 2034 { PMAC_FTR_1394_ENABLE, core99_firewire_enable }, 2035 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power }, 2036 { PMAC_FTR_SLEEP_STATE, core99_sleep_state }, 2037 { PMAC_FTR_READ_GPIO, core99_read_gpio }, 2038 { PMAC_FTR_WRITE_GPIO, core99_write_gpio }, 2039 { PMAC_FTR_AACK_DELAY_ENABLE, intrepid_aack_delay_enable }, 2040 { 0, NULL } 2041 }; 2042 2043 #else /* CONFIG_PPC64 */ 2044 2045 /* G5 features 2046 */ 2047 static struct feature_table_entry g5_features[] = { 2048 { PMAC_FTR_GMAC_ENABLE, g5_gmac_enable }, 2049 { PMAC_FTR_1394_ENABLE, g5_fw_enable }, 2050 { PMAC_FTR_ENABLE_MPIC, g5_mpic_enable }, 2051 { PMAC_FTR_GMAC_PHY_RESET, g5_eth_phy_reset }, 2052 { PMAC_FTR_SOUND_CHIP_ENABLE, g5_i2s_enable }, 2053 #ifdef CONFIG_SMP 2054 { PMAC_FTR_RESET_CPU, g5_reset_cpu }, 2055 #endif /* CONFIG_SMP */ 2056 { PMAC_FTR_READ_GPIO, core99_read_gpio }, 2057 { PMAC_FTR_WRITE_GPIO, core99_write_gpio }, 2058 { 0, NULL } 2059 }; 2060 2061 #endif /* CONFIG_PPC64 */ 2062 2063 static struct pmac_mb_def pmac_mb_defs[] = { 2064 #ifndef CONFIG_PPC64 2065 /* 2066 * Desktops 2067 */ 2068 2069 { "AAPL,8500", "PowerMac 8500/8600", 2070 PMAC_TYPE_PSURGE, NULL, 2071 0 2072 }, 2073 { "AAPL,9500", "PowerMac 9500/9600", 2074 PMAC_TYPE_PSURGE, NULL, 2075 0 2076 }, 2077 { "AAPL,7200", "PowerMac 7200", 2078 PMAC_TYPE_PSURGE, NULL, 2079 0 2080 }, 2081 { "AAPL,7300", "PowerMac 7200/7300", 2082 PMAC_TYPE_PSURGE, NULL, 2083 0 2084 }, 2085 { "AAPL,7500", "PowerMac 7500", 2086 PMAC_TYPE_PSURGE, NULL, 2087 0 2088 }, 2089 { "AAPL,ShinerESB", "Apple Network Server", 2090 PMAC_TYPE_ANS, NULL, 2091 0 2092 }, 2093 { "AAPL,e407", "Alchemy", 2094 PMAC_TYPE_ALCHEMY, NULL, 2095 0 2096 }, 2097 { "AAPL,e411", "Gazelle", 2098 PMAC_TYPE_GAZELLE, NULL, 2099 0 2100 }, 2101 { "AAPL,Gossamer", "PowerMac G3 (Gossamer)", 2102 PMAC_TYPE_GOSSAMER, heathrow_desktop_features, 2103 0 2104 }, 2105 { "AAPL,PowerMac G3", "PowerMac G3 (Silk)", 2106 PMAC_TYPE_SILK, heathrow_desktop_features, 2107 0 2108 }, 2109 { "PowerMac1,1", "Blue&White G3", 2110 PMAC_TYPE_YOSEMITE, paddington_features, 2111 0 2112 }, 2113 { "PowerMac1,2", "PowerMac G4 PCI Graphics", 2114 PMAC_TYPE_YIKES, paddington_features, 2115 0 2116 }, 2117 { "PowerMac2,1", "iMac FireWire", 2118 PMAC_TYPE_FW_IMAC, core99_features, 2119 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99 2120 }, 2121 { "PowerMac2,2", "iMac FireWire", 2122 PMAC_TYPE_FW_IMAC, core99_features, 2123 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99 2124 }, 2125 { "PowerMac3,1", "PowerMac G4 AGP Graphics", 2126 PMAC_TYPE_SAWTOOTH, core99_features, 2127 PMAC_MB_OLD_CORE99 2128 }, 2129 { "PowerMac3,2", "PowerMac G4 AGP Graphics", 2130 PMAC_TYPE_SAWTOOTH, core99_features, 2131 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99 2132 }, 2133 { "PowerMac3,3", "PowerMac G4 AGP Graphics", 2134 PMAC_TYPE_SAWTOOTH, core99_features, 2135 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99 2136 }, 2137 { "PowerMac3,4", "PowerMac G4 Silver", 2138 PMAC_TYPE_QUICKSILVER, core99_features, 2139 PMAC_MB_MAY_SLEEP 2140 }, 2141 { "PowerMac3,5", "PowerMac G4 Silver", 2142 PMAC_TYPE_QUICKSILVER, core99_features, 2143 PMAC_MB_MAY_SLEEP 2144 }, 2145 { "PowerMac3,6", "PowerMac G4 Windtunnel", 2146 PMAC_TYPE_WINDTUNNEL, core99_features, 2147 PMAC_MB_MAY_SLEEP, 2148 }, 2149 { "PowerMac4,1", "iMac \"Flower Power\"", 2150 PMAC_TYPE_PANGEA_IMAC, pangea_features, 2151 PMAC_MB_MAY_SLEEP 2152 }, 2153 { "PowerMac4,2", "Flat panel iMac", 2154 PMAC_TYPE_FLAT_PANEL_IMAC, pangea_features, 2155 PMAC_MB_CAN_SLEEP 2156 }, 2157 { "PowerMac4,4", "eMac", 2158 PMAC_TYPE_EMAC, core99_features, 2159 PMAC_MB_MAY_SLEEP 2160 }, 2161 { "PowerMac5,1", "PowerMac G4 Cube", 2162 PMAC_TYPE_CUBE, core99_features, 2163 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99 2164 }, 2165 { "PowerMac6,1", "Flat panel iMac", 2166 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2167 PMAC_MB_MAY_SLEEP, 2168 }, 2169 { "PowerMac6,3", "Flat panel iMac", 2170 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2171 PMAC_MB_MAY_SLEEP, 2172 }, 2173 { "PowerMac6,4", "eMac", 2174 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2175 PMAC_MB_MAY_SLEEP, 2176 }, 2177 { "PowerMac10,1", "Mac mini", 2178 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2179 PMAC_MB_MAY_SLEEP, 2180 }, 2181 { "PowerMac10,2", "Mac mini (Late 2005)", 2182 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2183 PMAC_MB_MAY_SLEEP, 2184 }, 2185 { "iMac,1", "iMac (first generation)", 2186 PMAC_TYPE_ORIG_IMAC, paddington_features, 2187 0 2188 }, 2189 2190 /* 2191 * Xserve's 2192 */ 2193 2194 { "RackMac1,1", "XServe", 2195 PMAC_TYPE_RACKMAC, rackmac_features, 2196 0, 2197 }, 2198 { "RackMac1,2", "XServe rev. 2", 2199 PMAC_TYPE_RACKMAC, rackmac_features, 2200 0, 2201 }, 2202 2203 /* 2204 * Laptops 2205 */ 2206 2207 { "AAPL,3400/2400", "PowerBook 3400", 2208 PMAC_TYPE_HOOPER, ohare_features, 2209 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE 2210 }, 2211 { "AAPL,3500", "PowerBook 3500", 2212 PMAC_TYPE_KANGA, ohare_features, 2213 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE 2214 }, 2215 { "AAPL,PowerBook1998", "PowerBook Wallstreet", 2216 PMAC_TYPE_WALLSTREET, heathrow_laptop_features, 2217 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE 2218 }, 2219 { "PowerBook1,1", "PowerBook 101 (Lombard)", 2220 PMAC_TYPE_101_PBOOK, paddington_features, 2221 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE 2222 }, 2223 { "PowerBook2,1", "iBook (first generation)", 2224 PMAC_TYPE_ORIG_IBOOK, core99_features, 2225 PMAC_MB_CAN_SLEEP | PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE 2226 }, 2227 { "PowerBook2,2", "iBook FireWire", 2228 PMAC_TYPE_FW_IBOOK, core99_features, 2229 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | 2230 PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE 2231 }, 2232 { "PowerBook3,1", "PowerBook Pismo", 2233 PMAC_TYPE_PISMO, core99_features, 2234 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | 2235 PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE 2236 }, 2237 { "PowerBook3,2", "PowerBook Titanium", 2238 PMAC_TYPE_TITANIUM, core99_features, 2239 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2240 }, 2241 { "PowerBook3,3", "PowerBook Titanium II", 2242 PMAC_TYPE_TITANIUM2, core99_features, 2243 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2244 }, 2245 { "PowerBook3,4", "PowerBook Titanium III", 2246 PMAC_TYPE_TITANIUM3, core99_features, 2247 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2248 }, 2249 { "PowerBook3,5", "PowerBook Titanium IV", 2250 PMAC_TYPE_TITANIUM4, core99_features, 2251 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2252 }, 2253 { "PowerBook4,1", "iBook 2", 2254 PMAC_TYPE_IBOOK2, pangea_features, 2255 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2256 }, 2257 { "PowerBook4,2", "iBook 2", 2258 PMAC_TYPE_IBOOK2, pangea_features, 2259 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2260 }, 2261 { "PowerBook4,3", "iBook 2 rev. 2", 2262 PMAC_TYPE_IBOOK2, pangea_features, 2263 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2264 }, 2265 { "PowerBook5,1", "PowerBook G4 17\"", 2266 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2267 PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2268 }, 2269 { "PowerBook5,2", "PowerBook G4 15\"", 2270 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2271 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2272 }, 2273 { "PowerBook5,3", "PowerBook G4 17\"", 2274 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2275 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2276 }, 2277 { "PowerBook5,4", "PowerBook G4 15\"", 2278 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2279 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2280 }, 2281 { "PowerBook5,5", "PowerBook G4 17\"", 2282 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2283 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2284 }, 2285 { "PowerBook5,6", "PowerBook G4 15\"", 2286 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2287 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2288 }, 2289 { "PowerBook5,7", "PowerBook G4 17\"", 2290 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2291 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2292 }, 2293 { "PowerBook5,8", "PowerBook G4 15\"", 2294 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2295 PMAC_MB_MAY_SLEEP | PMAC_MB_MOBILE, 2296 }, 2297 { "PowerBook5,9", "PowerBook G4 17\"", 2298 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2299 PMAC_MB_MAY_SLEEP | PMAC_MB_MOBILE, 2300 }, 2301 { "PowerBook6,1", "PowerBook G4 12\"", 2302 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2303 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2304 }, 2305 { "PowerBook6,2", "PowerBook G4", 2306 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2307 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2308 }, 2309 { "PowerBook6,3", "iBook G4", 2310 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2311 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2312 }, 2313 { "PowerBook6,4", "PowerBook G4 12\"", 2314 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2315 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2316 }, 2317 { "PowerBook6,5", "iBook G4", 2318 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2319 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2320 }, 2321 { "PowerBook6,7", "iBook G4", 2322 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2323 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2324 }, 2325 { "PowerBook6,8", "PowerBook G4 12\"", 2326 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2327 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2328 }, 2329 #else /* CONFIG_PPC64 */ 2330 { "PowerMac7,2", "PowerMac G5", 2331 PMAC_TYPE_POWERMAC_G5, g5_features, 2332 0, 2333 }, 2334 #ifdef CONFIG_PPC64 2335 { "PowerMac7,3", "PowerMac G5", 2336 PMAC_TYPE_POWERMAC_G5, g5_features, 2337 0, 2338 }, 2339 { "PowerMac8,1", "iMac G5", 2340 PMAC_TYPE_IMAC_G5, g5_features, 2341 0, 2342 }, 2343 { "PowerMac9,1", "PowerMac G5", 2344 PMAC_TYPE_POWERMAC_G5_U3L, g5_features, 2345 0, 2346 }, 2347 { "PowerMac11,2", "PowerMac G5 Dual Core", 2348 PMAC_TYPE_POWERMAC_G5_U3L, g5_features, 2349 0, 2350 }, 2351 { "PowerMac12,1", "iMac G5 (iSight)", 2352 PMAC_TYPE_POWERMAC_G5_U3L, g5_features, 2353 0, 2354 }, 2355 { "RackMac3,1", "XServe G5", 2356 PMAC_TYPE_XSERVE_G5, g5_features, 2357 0, 2358 }, 2359 #endif /* CONFIG_PPC64 */ 2360 #endif /* CONFIG_PPC64 */ 2361 }; 2362 2363 /* 2364 * The toplevel feature_call callback 2365 */ 2366 long pmac_do_feature_call(unsigned int selector, ...) 2367 { 2368 struct device_node *node; 2369 long param, value; 2370 int i; 2371 feature_call func = NULL; 2372 va_list args; 2373 2374 if (pmac_mb.features) 2375 for (i=0; pmac_mb.features[i].function; i++) 2376 if (pmac_mb.features[i].selector == selector) { 2377 func = pmac_mb.features[i].function; 2378 break; 2379 } 2380 if (!func) 2381 for (i=0; any_features[i].function; i++) 2382 if (any_features[i].selector == selector) { 2383 func = any_features[i].function; 2384 break; 2385 } 2386 if (!func) 2387 return -ENODEV; 2388 2389 va_start(args, selector); 2390 node = (struct device_node*)va_arg(args, void*); 2391 param = va_arg(args, long); 2392 value = va_arg(args, long); 2393 va_end(args); 2394 2395 return func(node, param, value); 2396 } 2397 2398 static int __init probe_motherboard(void) 2399 { 2400 int i; 2401 struct macio_chip *macio = &macio_chips[0]; 2402 const char *model = NULL; 2403 struct device_node *dt; 2404 int ret = 0; 2405 2406 /* Lookup known motherboard type in device-tree. First try an 2407 * exact match on the "model" property, then try a "compatible" 2408 * match is none is found. 2409 */ 2410 dt = of_find_node_by_name(NULL, "device-tree"); 2411 if (dt != NULL) 2412 model = of_get_property(dt, "model", NULL); 2413 for(i=0; model && i<ARRAY_SIZE(pmac_mb_defs); i++) { 2414 if (strcmp(model, pmac_mb_defs[i].model_string) == 0) { 2415 pmac_mb = pmac_mb_defs[i]; 2416 goto found; 2417 } 2418 } 2419 for(i=0; i<ARRAY_SIZE(pmac_mb_defs); i++) { 2420 if (of_machine_is_compatible(pmac_mb_defs[i].model_string)) { 2421 pmac_mb = pmac_mb_defs[i]; 2422 goto found; 2423 } 2424 } 2425 2426 /* Fallback to selection depending on mac-io chip type */ 2427 switch(macio->type) { 2428 #ifndef CONFIG_PPC64 2429 case macio_grand_central: 2430 pmac_mb.model_id = PMAC_TYPE_PSURGE; 2431 pmac_mb.model_name = "Unknown PowerSurge"; 2432 break; 2433 case macio_ohare: 2434 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_OHARE; 2435 pmac_mb.model_name = "Unknown OHare-based"; 2436 break; 2437 case macio_heathrow: 2438 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_HEATHROW; 2439 pmac_mb.model_name = "Unknown Heathrow-based"; 2440 pmac_mb.features = heathrow_desktop_features; 2441 break; 2442 case macio_paddington: 2443 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PADDINGTON; 2444 pmac_mb.model_name = "Unknown Paddington-based"; 2445 pmac_mb.features = paddington_features; 2446 break; 2447 case macio_keylargo: 2448 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_CORE99; 2449 pmac_mb.model_name = "Unknown Keylargo-based"; 2450 pmac_mb.features = core99_features; 2451 break; 2452 case macio_pangea: 2453 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PANGEA; 2454 pmac_mb.model_name = "Unknown Pangea-based"; 2455 pmac_mb.features = pangea_features; 2456 break; 2457 case macio_intrepid: 2458 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_INTREPID; 2459 pmac_mb.model_name = "Unknown Intrepid-based"; 2460 pmac_mb.features = intrepid_features; 2461 break; 2462 #else /* CONFIG_PPC64 */ 2463 case macio_keylargo2: 2464 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_K2; 2465 pmac_mb.model_name = "Unknown K2-based"; 2466 pmac_mb.features = g5_features; 2467 break; 2468 case macio_shasta: 2469 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_SHASTA; 2470 pmac_mb.model_name = "Unknown Shasta-based"; 2471 pmac_mb.features = g5_features; 2472 break; 2473 #endif /* CONFIG_PPC64 */ 2474 default: 2475 ret = -ENODEV; 2476 goto done; 2477 } 2478 found: 2479 #ifndef CONFIG_PPC64 2480 /* Fixup Hooper vs. Comet */ 2481 if (pmac_mb.model_id == PMAC_TYPE_HOOPER) { 2482 u32 __iomem * mach_id_ptr = ioremap(0xf3000034, 4); 2483 if (!mach_id_ptr) { 2484 ret = -ENODEV; 2485 goto done; 2486 } 2487 /* Here, I used to disable the media-bay on comet. It 2488 * appears this is wrong, the floppy connector is actually 2489 * a kind of media-bay and works with the current driver. 2490 */ 2491 if (__raw_readl(mach_id_ptr) & 0x20000000UL) 2492 pmac_mb.model_id = PMAC_TYPE_COMET; 2493 iounmap(mach_id_ptr); 2494 } 2495 2496 /* Set default value of powersave_nap on machines that support it. 2497 * It appears that uninorth rev 3 has a problem with it, we don't 2498 * enable it on those. In theory, the flush-on-lock property is 2499 * supposed to be set when not supported, but I'm not very confident 2500 * that all Apple OF revs did it properly, I do it the paranoid way. 2501 */ 2502 if (uninorth_base && uninorth_rev > 3) { 2503 struct device_node *np; 2504 2505 for_each_of_cpu_node(np) { 2506 int cpu_count = 1; 2507 2508 /* Nap mode not supported on SMP */ 2509 if (of_property_read_bool(np, "flush-on-lock") || 2510 (cpu_count > 1)) { 2511 powersave_nap = 0; 2512 of_node_put(np); 2513 break; 2514 } 2515 2516 cpu_count++; 2517 powersave_nap = 1; 2518 } 2519 } 2520 if (powersave_nap) 2521 printk(KERN_DEBUG "Processor NAP mode on idle enabled.\n"); 2522 2523 /* On CPUs that support it (750FX), lowspeed by default during 2524 * NAP mode 2525 */ 2526 powersave_lowspeed = 1; 2527 2528 #else /* CONFIG_PPC64 */ 2529 powersave_nap = 1; 2530 #endif /* CONFIG_PPC64 */ 2531 2532 /* Check for "mobile" machine */ 2533 if (model && (strncmp(model, "PowerBook", 9) == 0 2534 || strncmp(model, "iBook", 5) == 0)) 2535 pmac_mb.board_flags |= PMAC_MB_MOBILE; 2536 2537 2538 printk(KERN_INFO "PowerMac motherboard: %s\n", pmac_mb.model_name); 2539 done: 2540 of_node_put(dt); 2541 return ret; 2542 } 2543 2544 /* Initialize the Core99 UniNorth host bridge and memory controller 2545 */ 2546 static void __init probe_uninorth(void) 2547 { 2548 struct resource res; 2549 unsigned long actrl; 2550 2551 /* Locate core99 Uni-N */ 2552 uninorth_node = of_find_node_by_name(NULL, "uni-n"); 2553 uninorth_maj = 1; 2554 2555 /* Locate G5 u3 */ 2556 if (uninorth_node == NULL) { 2557 uninorth_node = of_find_node_by_name(NULL, "u3"); 2558 uninorth_maj = 3; 2559 } 2560 /* Locate G5 u4 */ 2561 if (uninorth_node == NULL) { 2562 uninorth_node = of_find_node_by_name(NULL, "u4"); 2563 uninorth_maj = 4; 2564 } 2565 if (uninorth_node == NULL) { 2566 uninorth_maj = 0; 2567 return; 2568 } 2569 2570 if (of_address_to_resource(uninorth_node, 0, &res)) 2571 return; 2572 2573 uninorth_base = ioremap(res.start, 0x40000); 2574 if (uninorth_base == NULL) 2575 return; 2576 uninorth_rev = in_be32(UN_REG(UNI_N_VERSION)); 2577 if (uninorth_maj == 3 || uninorth_maj == 4) { 2578 u3_ht_base = ioremap(res.start + U3_HT_CONFIG_BASE, 0x1000); 2579 if (u3_ht_base == NULL) { 2580 iounmap(uninorth_base); 2581 return; 2582 } 2583 } 2584 2585 printk(KERN_INFO "Found %s memory controller & host bridge" 2586 " @ 0x%08x revision: 0x%02x\n", uninorth_maj == 3 ? "U3" : 2587 uninorth_maj == 4 ? "U4" : "UniNorth", 2588 (unsigned int)res.start, uninorth_rev); 2589 printk(KERN_INFO "Mapped at 0x%08lx\n", (unsigned long)uninorth_base); 2590 2591 /* Set the arbitrer QAck delay according to what Apple does 2592 */ 2593 if (uninorth_rev < 0x11) { 2594 actrl = UN_IN(UNI_N_ARB_CTRL) & ~UNI_N_ARB_CTRL_QACK_DELAY_MASK; 2595 actrl |= ((uninorth_rev < 3) ? UNI_N_ARB_CTRL_QACK_DELAY105 : 2596 UNI_N_ARB_CTRL_QACK_DELAY) << 2597 UNI_N_ARB_CTRL_QACK_DELAY_SHIFT; 2598 UN_OUT(UNI_N_ARB_CTRL, actrl); 2599 } 2600 2601 /* Some more magic as done by them in recent MacOS X on UniNorth 2602 * revs 1.5 to 2.O and Pangea. Seem to toggle the UniN Maxbus/PCI 2603 * memory timeout 2604 */ 2605 if ((uninorth_rev >= 0x11 && uninorth_rev <= 0x24) || 2606 uninorth_rev == 0xc0) 2607 UN_OUT(0x2160, UN_IN(0x2160) & 0x00ffffff); 2608 } 2609 2610 static void __init probe_one_macio(const char *name, const char *compat, int type) 2611 { 2612 struct device_node* node; 2613 int i; 2614 volatile u32 __iomem *base; 2615 const u32 *addrp, *revp; 2616 phys_addr_t addr; 2617 u64 size; 2618 2619 for_each_node_by_name(node, name) { 2620 if (!compat) 2621 break; 2622 if (of_device_is_compatible(node, compat)) 2623 break; 2624 } 2625 if (!node) 2626 return; 2627 for(i=0; i<MAX_MACIO_CHIPS; i++) { 2628 if (!macio_chips[i].of_node) 2629 break; 2630 if (macio_chips[i].of_node == node) 2631 goto out_put; 2632 } 2633 2634 if (i >= MAX_MACIO_CHIPS) { 2635 printk(KERN_ERR "pmac_feature: Please increase MAX_MACIO_CHIPS !\n"); 2636 printk(KERN_ERR "pmac_feature: %pOF skipped\n", node); 2637 goto out_put; 2638 } 2639 addrp = of_get_pci_address(node, 0, &size, NULL); 2640 if (addrp == NULL) { 2641 printk(KERN_ERR "pmac_feature: %pOF: can't find base !\n", 2642 node); 2643 goto out_put; 2644 } 2645 addr = of_translate_address(node, addrp); 2646 if (addr == 0) { 2647 printk(KERN_ERR "pmac_feature: %pOF, can't translate base !\n", 2648 node); 2649 goto out_put; 2650 } 2651 base = ioremap(addr, (unsigned long)size); 2652 if (!base) { 2653 printk(KERN_ERR "pmac_feature: %pOF, can't map mac-io chip !\n", 2654 node); 2655 goto out_put; 2656 } 2657 if (type == macio_keylargo || type == macio_keylargo2) { 2658 const u32 *did = of_get_property(node, "device-id", NULL); 2659 if (*did == 0x00000025) 2660 type = macio_pangea; 2661 if (*did == 0x0000003e) 2662 type = macio_intrepid; 2663 if (*did == 0x0000004f) 2664 type = macio_shasta; 2665 } 2666 macio_chips[i].of_node = node; 2667 macio_chips[i].type = type; 2668 macio_chips[i].base = base; 2669 macio_chips[i].flags = MACIO_FLAG_SCCA_ON | MACIO_FLAG_SCCB_ON; 2670 macio_chips[i].name = macio_names[type]; 2671 revp = of_get_property(node, "revision-id", NULL); 2672 if (revp) 2673 macio_chips[i].rev = *revp; 2674 printk(KERN_INFO "Found a %s mac-io controller, rev: %d, mapped at 0x%p\n", 2675 macio_names[type], macio_chips[i].rev, macio_chips[i].base); 2676 2677 return; 2678 2679 out_put: 2680 of_node_put(node); 2681 } 2682 2683 static int __init 2684 probe_macios(void) 2685 { 2686 /* Warning, ordering is important */ 2687 probe_one_macio("gc", NULL, macio_grand_central); 2688 probe_one_macio("ohare", NULL, macio_ohare); 2689 probe_one_macio("pci106b,7", NULL, macio_ohareII); 2690 probe_one_macio("mac-io", "keylargo", macio_keylargo); 2691 probe_one_macio("mac-io", "paddington", macio_paddington); 2692 probe_one_macio("mac-io", "gatwick", macio_gatwick); 2693 probe_one_macio("mac-io", "heathrow", macio_heathrow); 2694 probe_one_macio("mac-io", "K2-Keylargo", macio_keylargo2); 2695 2696 /* Make sure the "main" macio chip appear first */ 2697 if (macio_chips[0].type == macio_gatwick 2698 && macio_chips[1].type == macio_heathrow) { 2699 struct macio_chip temp = macio_chips[0]; 2700 macio_chips[0] = macio_chips[1]; 2701 macio_chips[1] = temp; 2702 } 2703 if (macio_chips[0].type == macio_ohareII 2704 && macio_chips[1].type == macio_ohare) { 2705 struct macio_chip temp = macio_chips[0]; 2706 macio_chips[0] = macio_chips[1]; 2707 macio_chips[1] = temp; 2708 } 2709 macio_chips[0].lbus.index = 0; 2710 macio_chips[1].lbus.index = 1; 2711 2712 return (macio_chips[0].of_node == NULL) ? -ENODEV : 0; 2713 } 2714 2715 static void __init 2716 initial_serial_shutdown(struct device_node *np) 2717 { 2718 int len; 2719 const struct slot_names_prop { 2720 int count; 2721 char name[1]; 2722 } *slots; 2723 const char *conn; 2724 int port_type = PMAC_SCC_ASYNC; 2725 int modem = 0; 2726 2727 slots = of_get_property(np, "slot-names", &len); 2728 conn = of_get_property(np, "AAPL,connector", &len); 2729 if (conn && (strcmp(conn, "infrared") == 0)) 2730 port_type = PMAC_SCC_IRDA; 2731 else if (of_device_is_compatible(np, "cobalt")) 2732 modem = 1; 2733 else if (slots && slots->count > 0) { 2734 if (strcmp(slots->name, "IrDA") == 0) 2735 port_type = PMAC_SCC_IRDA; 2736 else if (strcmp(slots->name, "Modem") == 0) 2737 modem = 1; 2738 } 2739 if (modem) 2740 pmac_call_feature(PMAC_FTR_MODEM_ENABLE, np, 0, 0); 2741 pmac_call_feature(PMAC_FTR_SCC_ENABLE, np, port_type, 0); 2742 } 2743 2744 static void __init 2745 set_initial_features(void) 2746 { 2747 struct device_node *np; 2748 2749 /* That hack appears to be necessary for some StarMax motherboards 2750 * but I'm not too sure it was audited for side-effects on other 2751 * ohare based machines... 2752 * Since I still have difficulties figuring the right way to 2753 * differentiate them all and since that hack was there for a long 2754 * time, I'll keep it around 2755 */ 2756 if (macio_chips[0].type == macio_ohare) { 2757 struct macio_chip *macio = &macio_chips[0]; 2758 np = of_find_node_by_name(NULL, "via-pmu"); 2759 if (np) 2760 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE); 2761 else 2762 MACIO_OUT32(OHARE_FCR, STARMAX_FEATURES); 2763 of_node_put(np); 2764 } else if (macio_chips[1].type == macio_ohare) { 2765 struct macio_chip *macio = &macio_chips[1]; 2766 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE); 2767 } 2768 2769 #ifdef CONFIG_PPC64 2770 if (macio_chips[0].type == macio_keylargo2 || 2771 macio_chips[0].type == macio_shasta) { 2772 #ifndef CONFIG_SMP 2773 /* On SMP machines running UP, we have the second CPU eating 2774 * bus cycles. We need to take it off the bus. This is done 2775 * from pmac_smp for SMP kernels running on one CPU 2776 */ 2777 np = of_find_node_by_type(NULL, "cpu"); 2778 if (np != NULL) 2779 np = of_find_node_by_type(np, "cpu"); 2780 if (np != NULL) { 2781 g5_phy_disable_cpu1(); 2782 of_node_put(np); 2783 } 2784 #endif /* CONFIG_SMP */ 2785 /* Enable GMAC for now for PCI probing. It will be disabled 2786 * later on after PCI probe 2787 */ 2788 for_each_node_by_name(np, "ethernet") 2789 if (of_device_is_compatible(np, "K2-GMAC")) 2790 g5_gmac_enable(np, 0, 1); 2791 2792 /* Enable FW before PCI probe. Will be disabled later on 2793 * Note: We should have a batter way to check that we are 2794 * dealing with uninorth internal cell and not a PCI cell 2795 * on the external PCI. The code below works though. 2796 */ 2797 for_each_node_by_name(np, "firewire") { 2798 if (of_device_is_compatible(np, "pci106b,5811")) { 2799 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED; 2800 g5_fw_enable(np, 0, 1); 2801 } 2802 } 2803 } 2804 #else /* CONFIG_PPC64 */ 2805 2806 if (macio_chips[0].type == macio_keylargo || 2807 macio_chips[0].type == macio_pangea || 2808 macio_chips[0].type == macio_intrepid) { 2809 /* Enable GMAC for now for PCI probing. It will be disabled 2810 * later on after PCI probe 2811 */ 2812 for_each_node_by_name(np, "ethernet") { 2813 if (np->parent 2814 && of_device_is_compatible(np->parent, "uni-north") 2815 && of_device_is_compatible(np, "gmac")) 2816 core99_gmac_enable(np, 0, 1); 2817 } 2818 2819 /* Enable FW before PCI probe. Will be disabled later on 2820 * Note: We should have a batter way to check that we are 2821 * dealing with uninorth internal cell and not a PCI cell 2822 * on the external PCI. The code below works though. 2823 */ 2824 for_each_node_by_name(np, "firewire") { 2825 if (np->parent 2826 && of_device_is_compatible(np->parent, "uni-north") 2827 && (of_device_is_compatible(np, "pci106b,18") || 2828 of_device_is_compatible(np, "pci106b,30") || 2829 of_device_is_compatible(np, "pci11c1,5811"))) { 2830 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED; 2831 core99_firewire_enable(np, 0, 1); 2832 } 2833 } 2834 2835 /* Enable ATA-100 before PCI probe. */ 2836 for_each_node_by_name(np, "ata-6") { 2837 if (np->parent 2838 && of_device_is_compatible(np->parent, "uni-north") 2839 && of_device_is_compatible(np, "kauai-ata")) { 2840 core99_ata100_enable(np, 1); 2841 } 2842 } 2843 2844 /* Switch airport off */ 2845 for_each_node_by_name(np, "radio") { 2846 if (np->parent == macio_chips[0].of_node) { 2847 macio_chips[0].flags |= MACIO_FLAG_AIRPORT_ON; 2848 core99_airport_enable(np, 0, 0); 2849 } 2850 } 2851 } 2852 2853 /* On all machines that support sound PM, switch sound off */ 2854 if (macio_chips[0].of_node) 2855 pmac_do_feature_call(PMAC_FTR_SOUND_CHIP_ENABLE, 2856 macio_chips[0].of_node, 0, 0); 2857 2858 /* While on some desktop G3s, we turn it back on */ 2859 if (macio_chips[0].of_node && macio_chips[0].type == macio_heathrow 2860 && (pmac_mb.model_id == PMAC_TYPE_GOSSAMER || 2861 pmac_mb.model_id == PMAC_TYPE_SILK)) { 2862 struct macio_chip *macio = &macio_chips[0]; 2863 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE); 2864 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N); 2865 } 2866 2867 #endif /* CONFIG_PPC64 */ 2868 2869 /* On all machines, switch modem & serial ports off */ 2870 for_each_node_by_name(np, "ch-a") 2871 initial_serial_shutdown(np); 2872 for_each_node_by_name(np, "ch-b") 2873 initial_serial_shutdown(np); 2874 } 2875 2876 void __init 2877 pmac_feature_init(void) 2878 { 2879 /* Detect the UniNorth memory controller */ 2880 probe_uninorth(); 2881 2882 /* Probe mac-io controllers */ 2883 if (probe_macios()) { 2884 printk(KERN_WARNING "No mac-io chip found\n"); 2885 return; 2886 } 2887 2888 /* Probe machine type */ 2889 if (probe_motherboard()) 2890 printk(KERN_WARNING "Unknown PowerMac !\n"); 2891 2892 /* Set some initial features (turn off some chips that will 2893 * be later turned on) 2894 */ 2895 set_initial_features(); 2896 } 2897 2898 #if 0 2899 static void dump_HT_speeds(char *name, u32 cfg, u32 frq) 2900 { 2901 int freqs[16] = { 200,300,400,500,600,800,1000,0,0,0,0,0,0,0,0,0 }; 2902 int bits[8] = { 8,16,0,32,2,4,0,0 }; 2903 int freq = (frq >> 8) & 0xf; 2904 2905 if (freqs[freq] == 0) 2906 printk("%s: Unknown HT link frequency %x\n", name, freq); 2907 else 2908 printk("%s: %d MHz on main link, (%d in / %d out) bits width\n", 2909 name, freqs[freq], 2910 bits[(cfg >> 28) & 0x7], bits[(cfg >> 24) & 0x7]); 2911 } 2912 2913 void __init pmac_check_ht_link(void) 2914 { 2915 u32 ufreq, freq, ucfg, cfg; 2916 struct device_node *pcix_node; 2917 u8 px_bus, px_devfn; 2918 struct pci_controller *px_hose; 2919 2920 (void)in_be32(u3_ht_base + U3_HT_LINK_COMMAND); 2921 ucfg = cfg = in_be32(u3_ht_base + U3_HT_LINK_CONFIG); 2922 ufreq = freq = in_be32(u3_ht_base + U3_HT_LINK_FREQ); 2923 dump_HT_speeds("U3 HyperTransport", cfg, freq); 2924 2925 pcix_node = of_find_compatible_node(NULL, "pci", "pci-x"); 2926 if (pcix_node == NULL) { 2927 printk("No PCI-X bridge found\n"); 2928 return; 2929 } 2930 if (pci_device_from_OF_node(pcix_node, &px_bus, &px_devfn) != 0) { 2931 printk("PCI-X bridge found but not matched to pci\n"); 2932 return; 2933 } 2934 px_hose = pci_find_hose_for_OF_device(pcix_node); 2935 if (px_hose == NULL) { 2936 printk("PCI-X bridge found but not matched to host\n"); 2937 return; 2938 } 2939 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc4, &cfg); 2940 early_read_config_dword(px_hose, px_bus, px_devfn, 0xcc, &freq); 2941 dump_HT_speeds("PCI-X HT Uplink", cfg, freq); 2942 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc8, &cfg); 2943 early_read_config_dword(px_hose, px_bus, px_devfn, 0xd0, &freq); 2944 dump_HT_speeds("PCI-X HT Downlink", cfg, freq); 2945 } 2946 #endif /* 0 */ 2947 2948 /* 2949 * Early video resume hook 2950 */ 2951 2952 static void (*pmac_early_vresume_proc)(void *data); 2953 static void *pmac_early_vresume_data; 2954 2955 void pmac_set_early_video_resume(void (*proc)(void *data), void *data) 2956 { 2957 if (!machine_is(powermac)) 2958 return; 2959 preempt_disable(); 2960 pmac_early_vresume_proc = proc; 2961 pmac_early_vresume_data = data; 2962 preempt_enable(); 2963 } 2964 EXPORT_SYMBOL(pmac_set_early_video_resume); 2965 2966 void pmac_call_early_video_resume(void) 2967 { 2968 if (pmac_early_vresume_proc) 2969 pmac_early_vresume_proc(pmac_early_vresume_data); 2970 } 2971 2972 /* 2973 * AGP related suspend/resume code 2974 */ 2975 2976 static struct pci_dev *pmac_agp_bridge; 2977 static int (*pmac_agp_suspend)(struct pci_dev *bridge); 2978 static int (*pmac_agp_resume)(struct pci_dev *bridge); 2979 2980 void pmac_register_agp_pm(struct pci_dev *bridge, 2981 int (*suspend)(struct pci_dev *bridge), 2982 int (*resume)(struct pci_dev *bridge)) 2983 { 2984 if (suspend || resume) { 2985 pmac_agp_bridge = bridge; 2986 pmac_agp_suspend = suspend; 2987 pmac_agp_resume = resume; 2988 return; 2989 } 2990 if (bridge != pmac_agp_bridge) 2991 return; 2992 pmac_agp_suspend = pmac_agp_resume = NULL; 2993 return; 2994 } 2995 EXPORT_SYMBOL(pmac_register_agp_pm); 2996 2997 void pmac_suspend_agp_for_card(struct pci_dev *dev) 2998 { 2999 if (pmac_agp_bridge == NULL || pmac_agp_suspend == NULL) 3000 return; 3001 if (pmac_agp_bridge->bus != dev->bus) 3002 return; 3003 pmac_agp_suspend(pmac_agp_bridge); 3004 } 3005 EXPORT_SYMBOL(pmac_suspend_agp_for_card); 3006 3007 void pmac_resume_agp_for_card(struct pci_dev *dev) 3008 { 3009 if (pmac_agp_bridge == NULL || pmac_agp_resume == NULL) 3010 return; 3011 if (pmac_agp_bridge->bus != dev->bus) 3012 return; 3013 pmac_agp_resume(pmac_agp_bridge); 3014 } 3015 EXPORT_SYMBOL(pmac_resume_agp_for_card); 3016 3017 int pmac_get_uninorth_variant(void) 3018 { 3019 return uninorth_maj; 3020 } 3021