xref: /linux/arch/powerpc/platforms/powernv/setup.c (revision f86fd32d) 
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * PowerNV setup code.
4  *
5  * Copyright 2011 IBM Corp.
6  */
7 
8 #undef DEBUG
9 
10 #include <linux/cpu.h>
11 #include <linux/errno.h>
12 #include <linux/sched.h>
13 #include <linux/kernel.h>
14 #include <linux/tty.h>
15 #include <linux/reboot.h>
16 #include <linux/init.h>
17 #include <linux/console.h>
18 #include <linux/delay.h>
19 #include <linux/irq.h>
20 #include <linux/seq_file.h>
21 #include <linux/of.h>
22 #include <linux/of_fdt.h>
23 #include <linux/interrupt.h>
24 #include <linux/bug.h>
25 #include <linux/pci.h>
26 #include <linux/cpufreq.h>
27 #include <linux/memblock.h>
28 
29 #include <asm/machdep.h>
30 #include <asm/firmware.h>
31 #include <asm/xics.h>
32 #include <asm/xive.h>
33 #include <asm/opal.h>
34 #include <asm/kexec.h>
35 #include <asm/smp.h>
36 #include <asm/tm.h>
37 #include <asm/setup.h>
38 #include <asm/security_features.h>
39 
40 #include "powernv.h"
41 
42 
43 static bool fw_feature_is(const char *state, const char *name,
44 			  struct device_node *fw_features)
45 {
46 	struct device_node *np;
47 	bool rc = false;
48 
49 	np = of_get_child_by_name(fw_features, name);
50 	if (np) {
51 		rc = of_property_read_bool(np, state);
52 		of_node_put(np);
53 	}
54 
55 	return rc;
56 }
57 
58 static void init_fw_feat_flags(struct device_node *np)
59 {
60 	if (fw_feature_is("enabled", "inst-spec-barrier-ori31,31,0", np))
61 		security_ftr_set(SEC_FTR_SPEC_BAR_ORI31);
62 
63 	if (fw_feature_is("enabled", "fw-bcctrl-serialized", np))
64 		security_ftr_set(SEC_FTR_BCCTRL_SERIALISED);
65 
66 	if (fw_feature_is("enabled", "inst-l1d-flush-ori30,30,0", np))
67 		security_ftr_set(SEC_FTR_L1D_FLUSH_ORI30);
68 
69 	if (fw_feature_is("enabled", "inst-l1d-flush-trig2", np))
70 		security_ftr_set(SEC_FTR_L1D_FLUSH_TRIG2);
71 
72 	if (fw_feature_is("enabled", "fw-l1d-thread-split", np))
73 		security_ftr_set(SEC_FTR_L1D_THREAD_PRIV);
74 
75 	if (fw_feature_is("enabled", "fw-count-cache-disabled", np))
76 		security_ftr_set(SEC_FTR_COUNT_CACHE_DISABLED);
77 
78 	if (fw_feature_is("enabled", "fw-count-cache-flush-bcctr2,0,0", np))
79 		security_ftr_set(SEC_FTR_BCCTR_FLUSH_ASSIST);
80 
81 	if (fw_feature_is("enabled", "needs-count-cache-flush-on-context-switch", np))
82 		security_ftr_set(SEC_FTR_FLUSH_COUNT_CACHE);
83 
84 	/*
85 	 * The features below are enabled by default, so we instead look to see
86 	 * if firmware has *disabled* them, and clear them if so.
87 	 */
88 	if (fw_feature_is("disabled", "speculation-policy-favor-security", np))
89 		security_ftr_clear(SEC_FTR_FAVOUR_SECURITY);
90 
91 	if (fw_feature_is("disabled", "needs-l1d-flush-msr-pr-0-to-1", np))
92 		security_ftr_clear(SEC_FTR_L1D_FLUSH_PR);
93 
94 	if (fw_feature_is("disabled", "needs-l1d-flush-msr-hv-1-to-0", np))
95 		security_ftr_clear(SEC_FTR_L1D_FLUSH_HV);
96 
97 	if (fw_feature_is("disabled", "needs-spec-barrier-for-bound-checks", np))
98 		security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR);
99 }
100 
101 static void pnv_setup_rfi_flush(void)
102 {
103 	struct device_node *np, *fw_features;
104 	enum l1d_flush_type type;
105 	bool enable;
106 
107 	/* Default to fallback in case fw-features are not available */
108 	type = L1D_FLUSH_FALLBACK;
109 
110 	np = of_find_node_by_name(NULL, "ibm,opal");
111 	fw_features = of_get_child_by_name(np, "fw-features");
112 	of_node_put(np);
113 
114 	if (fw_features) {
115 		init_fw_feat_flags(fw_features);
116 		of_node_put(fw_features);
117 
118 		if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2))
119 			type = L1D_FLUSH_MTTRIG;
120 
121 		if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30))
122 			type = L1D_FLUSH_ORI;
123 	}
124 
125 	enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \
126 		 (security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR)   || \
127 		  security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV));
128 
129 	setup_rfi_flush(type, enable);
130 	setup_count_cache_flush();
131 }
132 
133 static void __init pnv_setup_arch(void)
134 {
135 	set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT);
136 
137 	pnv_setup_rfi_flush();
138 	setup_stf_barrier();
139 
140 	/* Initialize SMP */
141 	pnv_smp_init();
142 
143 	/* Setup PCI */
144 	pnv_pci_init();
145 
146 	/* Setup RTC and NVRAM callbacks */
147 	if (firmware_has_feature(FW_FEATURE_OPAL))
148 		opal_nvram_init();
149 
150 	/* Enable NAP mode */
151 	powersave_nap = 1;
152 
153 	/* XXX PMCS */
154 }
155 
156 static void __init pnv_init(void)
157 {
158 	/*
159 	 * Initialize the LPC bus now so that legacy serial
160 	 * ports can be found on it
161 	 */
162 	opal_lpc_init();
163 
164 #ifdef CONFIG_HVC_OPAL
165 	if (firmware_has_feature(FW_FEATURE_OPAL))
166 		hvc_opal_init_early();
167 	else
168 #endif
169 		add_preferred_console("hvc", 0, NULL);
170 
171 	if (!radix_enabled()) {
172 		int i;
173 
174 		/* Allocate per cpu area to save old slb contents during MCE */
175 		for_each_possible_cpu(i)
176 			paca_ptrs[i]->mce_faulty_slbs = memblock_alloc_node(mmu_slb_size, __alignof__(*paca_ptrs[i]->mce_faulty_slbs), cpu_to_node(i));
177 	}
178 }
179 
180 static void __init pnv_init_IRQ(void)
181 {
182 	/* Try using a XIVE if available, otherwise use a XICS */
183 	if (!xive_native_init())
184 		xics_init();
185 
186 	WARN_ON(!ppc_md.get_irq);
187 }
188 
189 static void pnv_show_cpuinfo(struct seq_file *m)
190 {
191 	struct device_node *root;
192 	const char *model = "";
193 
194 	root = of_find_node_by_path("/");
195 	if (root)
196 		model = of_get_property(root, "model", NULL);
197 	seq_printf(m, "machine\t\t: PowerNV %s\n", model);
198 	if (firmware_has_feature(FW_FEATURE_OPAL))
199 		seq_printf(m, "firmware\t: OPAL\n");
200 	else
201 		seq_printf(m, "firmware\t: BML\n");
202 	of_node_put(root);
203 	if (radix_enabled())
204 		seq_printf(m, "MMU\t\t: Radix\n");
205 	else
206 		seq_printf(m, "MMU\t\t: Hash\n");
207 }
208 
209 static void pnv_prepare_going_down(void)
210 {
211 	/*
212 	 * Disable all notifiers from OPAL, we can't
213 	 * service interrupts anymore anyway
214 	 */
215 	opal_event_shutdown();
216 
217 	/* Print flash update message if one is scheduled. */
218 	opal_flash_update_print_message();
219 
220 	smp_send_stop();
221 
222 	hard_irq_disable();
223 }
224 
225 static void  __noreturn pnv_restart(char *cmd)
226 {
227 	long rc;
228 
229 	pnv_prepare_going_down();
230 
231 	do {
232 		if (!cmd)
233 			rc = opal_cec_reboot();
234 		else if (strcmp(cmd, "full") == 0)
235 			rc = opal_cec_reboot2(OPAL_REBOOT_FULL_IPL, NULL);
236 		else if (strcmp(cmd, "mpipl") == 0)
237 			rc = opal_cec_reboot2(OPAL_REBOOT_MPIPL, NULL);
238 		else if (strcmp(cmd, "error") == 0)
239 			rc = opal_cec_reboot2(OPAL_REBOOT_PLATFORM_ERROR, NULL);
240 		else
241 			rc = OPAL_UNSUPPORTED;
242 
243 		if (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
244 			/* Opal is busy wait for some time and retry */
245 			opal_poll_events(NULL);
246 			mdelay(10);
247 
248 		} else	if (cmd && rc) {
249 			/* Unknown error while issuing reboot */
250 			if (rc == OPAL_UNSUPPORTED)
251 				pr_err("Unsupported '%s' reboot.\n", cmd);
252 			else
253 				pr_err("Unable to issue '%s' reboot. Err=%ld\n",
254 				       cmd, rc);
255 			pr_info("Forcing a cec-reboot\n");
256 			cmd = NULL;
257 			rc = OPAL_BUSY;
258 
259 		} else if (rc != OPAL_SUCCESS) {
260 			/* Unknown error while issuing cec-reboot */
261 			pr_err("Unable to reboot. Err=%ld\n", rc);
262 		}
263 
264 	} while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT);
265 
266 	for (;;)
267 		opal_poll_events(NULL);
268 }
269 
270 static void __noreturn pnv_power_off(void)
271 {
272 	long rc = OPAL_BUSY;
273 
274 	pnv_prepare_going_down();
275 
276 	while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
277 		rc = opal_cec_power_down(0);
278 		if (rc == OPAL_BUSY_EVENT)
279 			opal_poll_events(NULL);
280 		else
281 			mdelay(10);
282 	}
283 	for (;;)
284 		opal_poll_events(NULL);
285 }
286 
287 static void __noreturn pnv_halt(void)
288 {
289 	pnv_power_off();
290 }
291 
292 static void pnv_progress(char *s, unsigned short hex)
293 {
294 }
295 
296 static void pnv_shutdown(void)
297 {
298 	/* Let the PCI code clear up IODA tables */
299 	pnv_pci_shutdown();
300 
301 	/*
302 	 * Stop OPAL activity: Unregister all OPAL interrupts so they
303 	 * don't fire up while we kexec and make sure all potentially
304 	 * DMA'ing ops are complete (such as dump retrieval).
305 	 */
306 	opal_shutdown();
307 }
308 
309 #ifdef CONFIG_KEXEC_CORE
310 static void pnv_kexec_wait_secondaries_down(void)
311 {
312 	int my_cpu, i, notified = -1;
313 
314 	my_cpu = get_cpu();
315 
316 	for_each_online_cpu(i) {
317 		uint8_t status;
318 		int64_t rc, timeout = 1000;
319 
320 		if (i == my_cpu)
321 			continue;
322 
323 		for (;;) {
324 			rc = opal_query_cpu_status(get_hard_smp_processor_id(i),
325 						   &status);
326 			if (rc != OPAL_SUCCESS || status != OPAL_THREAD_STARTED)
327 				break;
328 			barrier();
329 			if (i != notified) {
330 				printk(KERN_INFO "kexec: waiting for cpu %d "
331 				       "(physical %d) to enter OPAL\n",
332 				       i, paca_ptrs[i]->hw_cpu_id);
333 				notified = i;
334 			}
335 
336 			/*
337 			 * On crash secondaries might be unreachable or hung,
338 			 * so timeout if we've waited too long
339 			 * */
340 			mdelay(1);
341 			if (timeout-- == 0) {
342 				printk(KERN_ERR "kexec: timed out waiting for "
343 				       "cpu %d (physical %d) to enter OPAL\n",
344 				       i, paca_ptrs[i]->hw_cpu_id);
345 				break;
346 			}
347 		}
348 	}
349 }
350 
351 static void pnv_kexec_cpu_down(int crash_shutdown, int secondary)
352 {
353 	u64 reinit_flags;
354 
355 	if (xive_enabled())
356 		xive_teardown_cpu();
357 	else
358 		xics_kexec_teardown_cpu(secondary);
359 
360 	/* On OPAL, we return all CPUs to firmware */
361 	if (!firmware_has_feature(FW_FEATURE_OPAL))
362 		return;
363 
364 	if (secondary) {
365 		/* Return secondary CPUs to firmware on OPAL v3 */
366 		mb();
367 		get_paca()->kexec_state = KEXEC_STATE_REAL_MODE;
368 		mb();
369 
370 		/* Return the CPU to OPAL */
371 		opal_return_cpu();
372 	} else {
373 		/* Primary waits for the secondaries to have reached OPAL */
374 		pnv_kexec_wait_secondaries_down();
375 
376 		/* Switch XIVE back to emulation mode */
377 		if (xive_enabled())
378 			xive_shutdown();
379 
380 		/*
381 		 * We might be running as little-endian - now that interrupts
382 		 * are disabled, reset the HILE bit to big-endian so we don't
383 		 * take interrupts in the wrong endian later
384 		 *
385 		 * We reinit to enable both radix and hash on P9 to ensure
386 		 * the mode used by the next kernel is always supported.
387 		 */
388 		reinit_flags = OPAL_REINIT_CPUS_HILE_BE;
389 		if (cpu_has_feature(CPU_FTR_ARCH_300))
390 			reinit_flags |= OPAL_REINIT_CPUS_MMU_RADIX |
391 				OPAL_REINIT_CPUS_MMU_HASH;
392 		opal_reinit_cpus(reinit_flags);
393 	}
394 }
395 #endif /* CONFIG_KEXEC_CORE */
396 
397 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
398 static unsigned long pnv_memory_block_size(void)
399 {
400 	return 256UL * 1024 * 1024;
401 }
402 #endif
403 
404 static void __init pnv_setup_machdep_opal(void)
405 {
406 	ppc_md.get_boot_time = opal_get_boot_time;
407 	ppc_md.restart = pnv_restart;
408 	pm_power_off = pnv_power_off;
409 	ppc_md.halt = pnv_halt;
410 	/* ppc_md.system_reset_exception gets filled in by pnv_smp_init() */
411 	ppc_md.machine_check_exception = opal_machine_check;
412 	ppc_md.mce_check_early_recovery = opal_mce_check_early_recovery;
413 	if (opal_check_token(OPAL_HANDLE_HMI2))
414 		ppc_md.hmi_exception_early = opal_hmi_exception_early2;
415 	else
416 		ppc_md.hmi_exception_early = opal_hmi_exception_early;
417 	ppc_md.handle_hmi_exception = opal_handle_hmi_exception;
418 }
419 
420 static int __init pnv_probe(void)
421 {
422 	if (!of_machine_is_compatible("ibm,powernv"))
423 		return 0;
424 
425 	if (firmware_has_feature(FW_FEATURE_OPAL))
426 		pnv_setup_machdep_opal();
427 
428 	pr_debug("PowerNV detected !\n");
429 
430 	pnv_init();
431 
432 	return 1;
433 }
434 
435 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
436 void __init pnv_tm_init(void)
437 {
438 	if (!firmware_has_feature(FW_FEATURE_OPAL) ||
439 	    !pvr_version_is(PVR_POWER9) ||
440 	    early_cpu_has_feature(CPU_FTR_TM))
441 		return;
442 
443 	if (opal_reinit_cpus(OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED) != OPAL_SUCCESS)
444 		return;
445 
446 	pr_info("Enabling TM (Transactional Memory) with Suspend Disabled\n");
447 	cur_cpu_spec->cpu_features |= CPU_FTR_TM;
448 	/* Make sure "normal" HTM is off (it should be) */
449 	cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_HTM;
450 	/* Turn on no suspend mode, and HTM no SC */
451 	cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NO_SUSPEND | \
452 					    PPC_FEATURE2_HTM_NOSC;
453 	tm_suspend_disabled = true;
454 }
455 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
456 
457 /*
458  * Returns the cpu frequency for 'cpu' in Hz. This is used by
459  * /proc/cpuinfo
460  */
461 static unsigned long pnv_get_proc_freq(unsigned int cpu)
462 {
463 	unsigned long ret_freq;
464 
465 	ret_freq = cpufreq_get(cpu) * 1000ul;
466 
467 	/*
468 	 * If the backend cpufreq driver does not exist,
469          * then fallback to old way of reporting the clockrate.
470 	 */
471 	if (!ret_freq)
472 		ret_freq = ppc_proc_freq;
473 	return ret_freq;
474 }
475 
476 static long pnv_machine_check_early(struct pt_regs *regs)
477 {
478 	long handled = 0;
479 
480 	if (cur_cpu_spec && cur_cpu_spec->machine_check_early)
481 		handled = cur_cpu_spec->machine_check_early(regs);
482 
483 	return handled;
484 }
485 
486 define_machine(powernv) {
487 	.name			= "PowerNV",
488 	.probe			= pnv_probe,
489 	.setup_arch		= pnv_setup_arch,
490 	.init_IRQ		= pnv_init_IRQ,
491 	.show_cpuinfo		= pnv_show_cpuinfo,
492 	.get_proc_freq          = pnv_get_proc_freq,
493 	.progress		= pnv_progress,
494 	.machine_shutdown	= pnv_shutdown,
495 	.power_save             = NULL,
496 	.calibrate_decr		= generic_calibrate_decr,
497 	.machine_check_early	= pnv_machine_check_early,
498 #ifdef CONFIG_KEXEC_CORE
499 	.kexec_cpu_down		= pnv_kexec_cpu_down,
500 #endif
501 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
502 	.memory_block_size	= pnv_memory_block_size,
503 #endif
504 };
505