144b24b74SMartyn Welch /*
244b24b74SMartyn Welch * Interrupt handling for GE FPGA based PIC
344b24b74SMartyn Welch *
444b24b74SMartyn Welch * Author: Martyn Welch <martyn.welch@ge.com>
544b24b74SMartyn Welch *
644b24b74SMartyn Welch * 2008 (c) GE Intelligent Platforms Embedded Systems, Inc.
744b24b74SMartyn Welch *
844b24b74SMartyn Welch * This file is licensed under the terms of the GNU General Public License
944b24b74SMartyn Welch * version 2. This program is licensed "as is" without any warranty of any
1044b24b74SMartyn Welch * kind, whether express or implied.
1144b24b74SMartyn Welch */
1244b24b74SMartyn Welch
1344b24b74SMartyn Welch #include <linux/stddef.h>
1444b24b74SMartyn Welch #include <linux/kernel.h>
1544b24b74SMartyn Welch #include <linux/init.h>
1644b24b74SMartyn Welch #include <linux/irq.h>
17e6f6390aSChristophe Leroy #include <linux/irqdomain.h>
1844b24b74SMartyn Welch #include <linux/interrupt.h>
19e6f6390aSChristophe Leroy #include <linux/of_address.h>
20e6f6390aSChristophe Leroy #include <linux/of_irq.h>
2144b24b74SMartyn Welch #include <linux/spinlock.h>
2244b24b74SMartyn Welch
2344b24b74SMartyn Welch #include <asm/byteorder.h>
2444b24b74SMartyn Welch #include <asm/io.h>
2544b24b74SMartyn Welch #include <asm/irq.h>
2644b24b74SMartyn Welch
2744b24b74SMartyn Welch #include "ge_pic.h"
2844b24b74SMartyn Welch
2944b24b74SMartyn Welch #define DEBUG
3044b24b74SMartyn Welch #undef DEBUG
3144b24b74SMartyn Welch
3244b24b74SMartyn Welch #ifdef DEBUG
3344b24b74SMartyn Welch #define DBG(fmt...) do { printk(KERN_DEBUG "gef_pic: " fmt); } while (0)
3444b24b74SMartyn Welch #else
3544b24b74SMartyn Welch #define DBG(fmt...) do { } while (0)
3644b24b74SMartyn Welch #endif
3744b24b74SMartyn Welch
3844b24b74SMartyn Welch #define GEF_PIC_NUM_IRQS 32
3944b24b74SMartyn Welch
4044b24b74SMartyn Welch /* Interrupt Controller Interface Registers */
4144b24b74SMartyn Welch #define GEF_PIC_INTR_STATUS 0x0000
4244b24b74SMartyn Welch
4344b24b74SMartyn Welch #define GEF_PIC_INTR_MASK(cpu) (0x0010 + (0x4 * cpu))
4444b24b74SMartyn Welch #define GEF_PIC_CPU0_INTR_MASK GEF_PIC_INTR_MASK(0)
4544b24b74SMartyn Welch #define GEF_PIC_CPU1_INTR_MASK GEF_PIC_INTR_MASK(1)
4644b24b74SMartyn Welch
4744b24b74SMartyn Welch #define GEF_PIC_MCP_MASK(cpu) (0x0018 + (0x4 * cpu))
4844b24b74SMartyn Welch #define GEF_PIC_CPU0_MCP_MASK GEF_PIC_MCP_MASK(0)
4944b24b74SMartyn Welch #define GEF_PIC_CPU1_MCP_MASK GEF_PIC_MCP_MASK(1)
5044b24b74SMartyn Welch
5144b24b74SMartyn Welch
5244b24b74SMartyn Welch static DEFINE_RAW_SPINLOCK(gef_pic_lock);
5344b24b74SMartyn Welch
5444b24b74SMartyn Welch static void __iomem *gef_pic_irq_reg_base;
555375871dSLinus Torvalds static struct irq_domain *gef_pic_irq_host;
5644b24b74SMartyn Welch static int gef_pic_cascade_irq;
5744b24b74SMartyn Welch
5844b24b74SMartyn Welch /*
5944b24b74SMartyn Welch * Interrupt Controller Handling
6044b24b74SMartyn Welch *
6144b24b74SMartyn Welch * The interrupt controller handles interrupts for most on board interrupts,
6244b24b74SMartyn Welch * apart from PCI interrupts. For example on SBC610:
6344b24b74SMartyn Welch *
6444b24b74SMartyn Welch * 17:31 RO Reserved
6544b24b74SMartyn Welch * 16 RO PCI Express Doorbell 3 Status
6644b24b74SMartyn Welch * 15 RO PCI Express Doorbell 2 Status
6744b24b74SMartyn Welch * 14 RO PCI Express Doorbell 1 Status
6844b24b74SMartyn Welch * 13 RO PCI Express Doorbell 0 Status
6944b24b74SMartyn Welch * 12 RO Real Time Clock Interrupt Status
7044b24b74SMartyn Welch * 11 RO Temperature Interrupt Status
7144b24b74SMartyn Welch * 10 RO Temperature Critical Interrupt Status
7244b24b74SMartyn Welch * 9 RO Ethernet PHY1 Interrupt Status
7344b24b74SMartyn Welch * 8 RO Ethernet PHY3 Interrupt Status
7444b24b74SMartyn Welch * 7 RO PEX8548 Interrupt Status
7544b24b74SMartyn Welch * 6 RO Reserved
7644b24b74SMartyn Welch * 5 RO Watchdog 0 Interrupt Status
7744b24b74SMartyn Welch * 4 RO Watchdog 1 Interrupt Status
7844b24b74SMartyn Welch * 3 RO AXIS Message FIFO A Interrupt Status
7944b24b74SMartyn Welch * 2 RO AXIS Message FIFO B Interrupt Status
8044b24b74SMartyn Welch * 1 RO AXIS Message FIFO C Interrupt Status
8144b24b74SMartyn Welch * 0 RO AXIS Message FIFO D Interrupt Status
8244b24b74SMartyn Welch *
8344b24b74SMartyn Welch * Interrupts can be forwarded to one of two output lines. Nothing
8444b24b74SMartyn Welch * clever is done, so if the masks are incorrectly set, a single input
8544b24b74SMartyn Welch * interrupt could generate interrupts on both output lines!
8644b24b74SMartyn Welch *
8744b24b74SMartyn Welch * The dual lines are there to allow the chained interrupts to be easily
8844b24b74SMartyn Welch * passed into two different cores. We currently do not use this functionality
8944b24b74SMartyn Welch * in this driver.
9044b24b74SMartyn Welch *
9144b24b74SMartyn Welch * Controller can also be configured to generate Machine checks (MCP), again on
9244b24b74SMartyn Welch * two lines, to be attached to two different cores. It is suggested that these
9344b24b74SMartyn Welch * should be masked out.
9444b24b74SMartyn Welch */
9544b24b74SMartyn Welch
gef_pic_cascade(struct irq_desc * desc)96bd0b9ac4SThomas Gleixner static void gef_pic_cascade(struct irq_desc *desc)
9744b24b74SMartyn Welch {
9844b24b74SMartyn Welch struct irq_chip *chip = irq_desc_get_chip(desc);
9944b24b74SMartyn Welch unsigned int cascade_irq;
10044b24b74SMartyn Welch
10144b24b74SMartyn Welch /*
10244b24b74SMartyn Welch * See if we actually have an interrupt, call generic handling code if
10344b24b74SMartyn Welch * we do.
10444b24b74SMartyn Welch */
10544b24b74SMartyn Welch cascade_irq = gef_pic_get_irq();
10644b24b74SMartyn Welch
107ef24ba70SMichael Ellerman if (cascade_irq)
10844b24b74SMartyn Welch generic_handle_irq(cascade_irq);
10944b24b74SMartyn Welch
11044b24b74SMartyn Welch chip->irq_eoi(&desc->irq_data);
11144b24b74SMartyn Welch }
11244b24b74SMartyn Welch
gef_pic_mask(struct irq_data * d)11344b24b74SMartyn Welch static void gef_pic_mask(struct irq_data *d)
11444b24b74SMartyn Welch {
11544b24b74SMartyn Welch unsigned long flags;
11644b24b74SMartyn Welch unsigned int hwirq = irqd_to_hwirq(d);
11744b24b74SMartyn Welch u32 mask;
11844b24b74SMartyn Welch
11944b24b74SMartyn Welch raw_spin_lock_irqsave(&gef_pic_lock, flags);
12044b24b74SMartyn Welch mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
12144b24b74SMartyn Welch mask &= ~(1 << hwirq);
12244b24b74SMartyn Welch out_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0), mask);
12344b24b74SMartyn Welch raw_spin_unlock_irqrestore(&gef_pic_lock, flags);
12444b24b74SMartyn Welch }
12544b24b74SMartyn Welch
gef_pic_mask_ack(struct irq_data * d)12644b24b74SMartyn Welch static void gef_pic_mask_ack(struct irq_data *d)
12744b24b74SMartyn Welch {
12844b24b74SMartyn Welch /* Don't think we actually have to do anything to ack an interrupt,
12944b24b74SMartyn Welch * we just need to clear down the devices interrupt and it will go away
13044b24b74SMartyn Welch */
13144b24b74SMartyn Welch gef_pic_mask(d);
13244b24b74SMartyn Welch }
13344b24b74SMartyn Welch
gef_pic_unmask(struct irq_data * d)13444b24b74SMartyn Welch static void gef_pic_unmask(struct irq_data *d)
13544b24b74SMartyn Welch {
13644b24b74SMartyn Welch unsigned long flags;
13744b24b74SMartyn Welch unsigned int hwirq = irqd_to_hwirq(d);
13844b24b74SMartyn Welch u32 mask;
13944b24b74SMartyn Welch
14044b24b74SMartyn Welch raw_spin_lock_irqsave(&gef_pic_lock, flags);
14144b24b74SMartyn Welch mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
14244b24b74SMartyn Welch mask |= (1 << hwirq);
14344b24b74SMartyn Welch out_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0), mask);
14444b24b74SMartyn Welch raw_spin_unlock_irqrestore(&gef_pic_lock, flags);
14544b24b74SMartyn Welch }
14644b24b74SMartyn Welch
14744b24b74SMartyn Welch static struct irq_chip gef_pic_chip = {
14844b24b74SMartyn Welch .name = "gefp",
14944b24b74SMartyn Welch .irq_mask = gef_pic_mask,
15044b24b74SMartyn Welch .irq_mask_ack = gef_pic_mask_ack,
15144b24b74SMartyn Welch .irq_unmask = gef_pic_unmask,
15244b24b74SMartyn Welch };
15344b24b74SMartyn Welch
15444b24b74SMartyn Welch
1551fd02f66SJulia Lawall /* When an interrupt is being configured, this call allows some flexibility
15644b24b74SMartyn Welch * in deciding which irq_chip structure is used
15744b24b74SMartyn Welch */
gef_pic_host_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hwirq)1585375871dSLinus Torvalds static int gef_pic_host_map(struct irq_domain *h, unsigned int virq,
15944b24b74SMartyn Welch irq_hw_number_t hwirq)
16044b24b74SMartyn Welch {
16144b24b74SMartyn Welch /* All interrupts are LEVEL sensitive */
16244b24b74SMartyn Welch irq_set_status_flags(virq, IRQ_LEVEL);
16344b24b74SMartyn Welch irq_set_chip_and_handler(virq, &gef_pic_chip, handle_level_irq);
16444b24b74SMartyn Welch
16544b24b74SMartyn Welch return 0;
16644b24b74SMartyn Welch }
16744b24b74SMartyn Welch
gef_pic_host_xlate(struct irq_domain * h,struct device_node * ct,const u32 * intspec,unsigned int intsize,irq_hw_number_t * out_hwirq,unsigned int * out_flags)1685375871dSLinus Torvalds static int gef_pic_host_xlate(struct irq_domain *h, struct device_node *ct,
16944b24b74SMartyn Welch const u32 *intspec, unsigned int intsize,
17044b24b74SMartyn Welch irq_hw_number_t *out_hwirq, unsigned int *out_flags)
17144b24b74SMartyn Welch {
17244b24b74SMartyn Welch
17344b24b74SMartyn Welch *out_hwirq = intspec[0];
17444b24b74SMartyn Welch if (intsize > 1)
17544b24b74SMartyn Welch *out_flags = intspec[1];
17644b24b74SMartyn Welch else
17744b24b74SMartyn Welch *out_flags = IRQ_TYPE_LEVEL_HIGH;
17844b24b74SMartyn Welch
17944b24b74SMartyn Welch return 0;
18044b24b74SMartyn Welch }
18144b24b74SMartyn Welch
1825375871dSLinus Torvalds static const struct irq_domain_ops gef_pic_host_ops = {
18344b24b74SMartyn Welch .map = gef_pic_host_map,
18444b24b74SMartyn Welch .xlate = gef_pic_host_xlate,
18544b24b74SMartyn Welch };
18644b24b74SMartyn Welch
18744b24b74SMartyn Welch
18844b24b74SMartyn Welch /*
18944b24b74SMartyn Welch * Initialisation of PIC, this should be called in BSP
19044b24b74SMartyn Welch */
gef_pic_init(struct device_node * np)19144b24b74SMartyn Welch void __init gef_pic_init(struct device_node *np)
19244b24b74SMartyn Welch {
19344b24b74SMartyn Welch unsigned long flags;
19444b24b74SMartyn Welch
19544b24b74SMartyn Welch /* Map the devices registers into memory */
19644b24b74SMartyn Welch gef_pic_irq_reg_base = of_iomap(np, 0);
19744b24b74SMartyn Welch
19844b24b74SMartyn Welch raw_spin_lock_irqsave(&gef_pic_lock, flags);
19944b24b74SMartyn Welch
20044b24b74SMartyn Welch /* Initialise everything as masked. */
20144b24b74SMartyn Welch out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU0_INTR_MASK, 0);
20244b24b74SMartyn Welch out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU1_INTR_MASK, 0);
20344b24b74SMartyn Welch
20444b24b74SMartyn Welch out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU0_MCP_MASK, 0);
20544b24b74SMartyn Welch out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU1_MCP_MASK, 0);
20644b24b74SMartyn Welch
20744b24b74SMartyn Welch raw_spin_unlock_irqrestore(&gef_pic_lock, flags);
20844b24b74SMartyn Welch
20944b24b74SMartyn Welch /* Map controller */
21044b24b74SMartyn Welch gef_pic_cascade_irq = irq_of_parse_and_map(np, 0);
211ef24ba70SMichael Ellerman if (!gef_pic_cascade_irq) {
21244b24b74SMartyn Welch printk(KERN_ERR "SBC610: failed to map cascade interrupt");
21344b24b74SMartyn Welch return;
21444b24b74SMartyn Welch }
21544b24b74SMartyn Welch
2165375871dSLinus Torvalds /* Setup an irq_domain structure */
2175375871dSLinus Torvalds gef_pic_irq_host = irq_domain_add_linear(np, GEF_PIC_NUM_IRQS,
2185375871dSLinus Torvalds &gef_pic_host_ops, NULL);
21944b24b74SMartyn Welch if (gef_pic_irq_host == NULL)
22044b24b74SMartyn Welch return;
22144b24b74SMartyn Welch
22244b24b74SMartyn Welch /* Chain with parent controller */
22344b24b74SMartyn Welch irq_set_chained_handler(gef_pic_cascade_irq, gef_pic_cascade);
22444b24b74SMartyn Welch }
22544b24b74SMartyn Welch
22644b24b74SMartyn Welch /*
22744b24b74SMartyn Welch * This is called when we receive an interrupt with apparently comes from this
228ef24ba70SMichael Ellerman * chip - check, returning the highest interrupt generated or return 0.
22944b24b74SMartyn Welch */
gef_pic_get_irq(void)23044b24b74SMartyn Welch unsigned int gef_pic_get_irq(void)
23144b24b74SMartyn Welch {
23244b24b74SMartyn Welch u32 cause, mask, active;
233ef24ba70SMichael Ellerman unsigned int virq = 0;
23444b24b74SMartyn Welch int hwirq;
23544b24b74SMartyn Welch
23644b24b74SMartyn Welch cause = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_STATUS);
23744b24b74SMartyn Welch
23844b24b74SMartyn Welch mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
23944b24b74SMartyn Welch
24044b24b74SMartyn Welch active = cause & mask;
24144b24b74SMartyn Welch
24244b24b74SMartyn Welch if (active) {
24344b24b74SMartyn Welch for (hwirq = GEF_PIC_NUM_IRQS - 1; hwirq > -1; hwirq--) {
24444b24b74SMartyn Welch if (active & (0x1 << hwirq))
24544b24b74SMartyn Welch break;
24644b24b74SMartyn Welch }
24744b24b74SMartyn Welch virq = irq_linear_revmap(gef_pic_irq_host,
24844b24b74SMartyn Welch (irq_hw_number_t)hwirq);
24944b24b74SMartyn Welch }
25044b24b74SMartyn Welch
25144b24b74SMartyn Welch return virq;
25244b24b74SMartyn Welch }
25344b24b74SMartyn Welch
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