1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2020-2021 Microchip Technology Inc */
3
4/dts-v1/;
5
6#include "mpfs.dtsi"
7#include "mpfs-icicle-kit-fabric.dtsi"
8
9/* Clock frequency (in Hz) of the rtcclk */
10#define RTCCLK_FREQ		1000000
11
12/ {
13	model = "Microchip PolarFire-SoC Icicle Kit";
14	compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
15		     "microchip,mpfs";
16
17	aliases {
18		ethernet0 = &mac1;
19		serial0 = &mmuart0;
20		serial1 = &mmuart1;
21		serial2 = &mmuart2;
22		serial3 = &mmuart3;
23		serial4 = &mmuart4;
24	};
25
26	chosen {
27		stdout-path = "serial1:115200n8";
28	};
29
30	cpus {
31		timebase-frequency = <RTCCLK_FREQ>;
32	};
33
34	ddrc_cache_lo: memory@80000000 {
35		device_type = "memory";
36		reg = <0x0 0x80000000 0x0 0x40000000>;
37		status = "okay";
38	};
39
40	ddrc_cache_hi: memory@1000000000 {
41		device_type = "memory";
42		reg = <0x10 0x40000000 0x0 0x40000000>;
43		status = "okay";
44	};
45
46	reserved-memory {
47		#address-cells = <2>;
48		#size-cells = <2>;
49		ranges;
50
51		hss_payload: region@BFC00000 {
52			reg = <0x0 0xBFC00000 0x0 0x400000>;
53			no-map;
54		};
55	};
56};
57
58&core_pwm0 {
59	status = "okay";
60};
61
62&gpio2 {
63	interrupts = <53>, <53>, <53>, <53>,
64		     <53>, <53>, <53>, <53>,
65		     <53>, <53>, <53>, <53>,
66		     <53>, <53>, <53>, <53>,
67		     <53>, <53>, <53>, <53>,
68		     <53>, <53>, <53>, <53>,
69		     <53>, <53>, <53>, <53>,
70		     <53>, <53>, <53>, <53>;
71	status = "okay";
72};
73
74&i2c0 {
75	status = "okay";
76};
77
78&i2c1 {
79	status = "okay";
80};
81
82&i2c2 {
83	status = "okay";
84};
85
86&mac0 {
87	phy-mode = "sgmii";
88	phy-handle = <&phy0>;
89	status = "okay";
90};
91
92&mac1 {
93	phy-mode = "sgmii";
94	phy-handle = <&phy1>;
95	status = "okay";
96
97	phy1: ethernet-phy@9 {
98		reg = <9>;
99	};
100
101	phy0: ethernet-phy@8 {
102		reg = <8>;
103	};
104};
105
106&mbox {
107	status = "okay";
108};
109
110&mmc {
111	bus-width = <4>;
112	disable-wp;
113	cap-sd-highspeed;
114	cap-mmc-highspeed;
115	mmc-ddr-1_8v;
116	mmc-hs200-1_8v;
117	sd-uhs-sdr12;
118	sd-uhs-sdr25;
119	sd-uhs-sdr50;
120	sd-uhs-sdr104;
121	status = "okay";
122};
123
124&mmuart1 {
125	status = "okay";
126};
127
128&mmuart2 {
129	status = "okay";
130};
131
132&mmuart3 {
133	status = "okay";
134};
135
136&mmuart4 {
137	status = "okay";
138};
139
140&pcie {
141	status = "okay";
142};
143
144&qspi {
145	status = "okay";
146};
147
148&refclk {
149	clock-frequency = <125000000>;
150};
151
152&rtc {
153	status = "okay";
154};
155
156&spi0 {
157	status = "okay";
158};
159
160&spi1 {
161	status = "okay";
162};
163
164&syscontroller {
165	status = "okay";
166};
167
168&usb {
169	status = "okay";
170	dr_mode = "host";
171};
172