1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/Five SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>
9
10#define SOC_PERIPHERAL_IRQ(nr)	(nr + 32)
11
12#include <arm64/renesas/r9a07g043.dtsi>
13
14/ {
15	cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18		timebase-frequency = <12000000>;
19
20		cpu0: cpu@0 {
21			compatible = "andestech,ax45mp", "riscv";
22			device_type = "cpu";
23			#cooling-cells = <2>;
24			reg = <0x0>;
25			status = "okay";
26			riscv,isa = "rv64imafdc";
27			mmu-type = "riscv,sv39";
28			i-cache-size = <0x8000>;
29			i-cache-line-size = <0x40>;
30			d-cache-size = <0x8000>;
31			d-cache-line-size = <0x40>;
32			next-level-cache = <&l2cache>;
33			clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
34			operating-points-v2 = <&cluster0_opp>;
35
36			cpu0_intc: interrupt-controller {
37				#interrupt-cells = <1>;
38				compatible = "riscv,cpu-intc";
39				interrupt-controller;
40			};
41		};
42	};
43};
44
45&soc {
46	dma-noncoherent;
47	interrupt-parent = <&plic>;
48
49	plic: interrupt-controller@12c00000 {
50		compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
51		#interrupt-cells = <2>;
52		#address-cells = <0>;
53		riscv,ndev = <511>;
54		interrupt-controller;
55		reg = <0x0 0x12c00000 0 0x400000>;
56		clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
57		power-domains = <&cpg>;
58		resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
59		interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
60	};
61
62	l2cache: cache-controller@13400000 {
63		compatible = "andestech,ax45mp-cache", "cache";
64		reg = <0x0 0x13400000 0x0 0x100000>;
65		interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
66		cache-size = <0x40000>;
67		cache-line-size = <64>;
68		cache-sets = <1024>;
69		cache-unified;
70		cache-level = <2>;
71	};
72};
73