1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2021 Sifive. 4 */ 5 #ifndef ASM_ERRATA_LIST_H 6 #define ASM_ERRATA_LIST_H 7 8 #include <asm/alternative.h> 9 #include <asm/csr.h> 10 #include <asm/insn-def.h> 11 #include <asm/hwcap.h> 12 #include <asm/vendorid_list.h> 13 14 #ifdef CONFIG_ERRATA_ANDES 15 #define ERRATA_ANDES_NO_IOCP 0 16 #define ERRATA_ANDES_NUMBER 1 17 #endif 18 19 #ifdef CONFIG_ERRATA_SIFIVE 20 #define ERRATA_SIFIVE_CIP_453 0 21 #define ERRATA_SIFIVE_CIP_1200 1 22 #define ERRATA_SIFIVE_NUMBER 2 23 #endif 24 25 #ifdef CONFIG_ERRATA_THEAD 26 #define ERRATA_THEAD_PBMT 0 27 #define ERRATA_THEAD_PMU 1 28 #define ERRATA_THEAD_NUMBER 2 29 #endif 30 31 #ifdef __ASSEMBLY__ 32 33 #define ALT_INSN_FAULT(x) \ 34 ALTERNATIVE(__stringify(RISCV_PTR do_trap_insn_fault), \ 35 __stringify(RISCV_PTR sifive_cip_453_insn_fault_trp), \ 36 SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \ 37 CONFIG_ERRATA_SIFIVE_CIP_453) 38 39 #define ALT_PAGE_FAULT(x) \ 40 ALTERNATIVE(__stringify(RISCV_PTR do_page_fault), \ 41 __stringify(RISCV_PTR sifive_cip_453_page_fault_trp), \ 42 SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \ 43 CONFIG_ERRATA_SIFIVE_CIP_453) 44 #else /* !__ASSEMBLY__ */ 45 46 #define ALT_FLUSH_TLB_PAGE(x) \ 47 asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \ 48 ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200) \ 49 : : "r" (addr) : "memory") 50 51 /* 52 * _val is marked as "will be overwritten", so need to set it to 0 53 * in the default case. 54 */ 55 #define ALT_SVPBMT_SHIFT 61 56 #define ALT_THEAD_PBMT_SHIFT 59 57 #define ALT_SVPBMT(_val, prot) \ 58 asm(ALTERNATIVE_2("li %0, 0\t\nnop", \ 59 "li %0, %1\t\nslli %0,%0,%3", 0, \ 60 RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \ 61 "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, \ 62 ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \ 63 : "=r"(_val) \ 64 : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \ 65 "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT), \ 66 "I"(ALT_SVPBMT_SHIFT), \ 67 "I"(ALT_THEAD_PBMT_SHIFT)) 68 69 #ifdef CONFIG_ERRATA_THEAD_PBMT 70 /* 71 * IO/NOCACHE memory types are handled together with svpbmt, 72 * so on T-Head chips, check if no other memory type is set, 73 * and set the non-0 PMA type if applicable. 74 */ 75 #define ALT_THEAD_PMA(_val) \ 76 asm volatile(ALTERNATIVE( \ 77 __nops(7), \ 78 "li t3, %1\n\t" \ 79 "slli t3, t3, %3\n\t" \ 80 "and t3, %0, t3\n\t" \ 81 "bne t3, zero, 2f\n\t" \ 82 "li t3, %2\n\t" \ 83 "slli t3, t3, %3\n\t" \ 84 "or %0, %0, t3\n\t" \ 85 "2:", THEAD_VENDOR_ID, \ 86 ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \ 87 : "+r"(_val) \ 88 : "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT), \ 89 "I"(_PAGE_PMA_THEAD >> ALT_THEAD_PBMT_SHIFT), \ 90 "I"(ALT_THEAD_PBMT_SHIFT) \ 91 : "t3") 92 #else 93 #define ALT_THEAD_PMA(_val) 94 #endif 95 96 #define ALT_CMO_OP(_op, _start, _size, _cachesize) \ 97 asm volatile(ALTERNATIVE( \ 98 __nops(5), \ 99 "mv a0, %1\n\t" \ 100 "j 2f\n\t" \ 101 "3:\n\t" \ 102 CBO_##_op(a0) \ 103 "add a0, a0, %0\n\t" \ 104 "2:\n\t" \ 105 "bltu a0, %2, 3b\n\t", \ 106 0, RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM) \ 107 : : "r"(_cachesize), \ 108 "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \ 109 "r"((unsigned long)(_start) + (_size)) \ 110 : "a0") 111 112 #define THEAD_C9XX_RV_IRQ_PMU 17 113 #define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5 114 115 #endif /* __ASSEMBLY__ */ 116 117 #endif 118