1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_PGTABLE_H 7 #define _ASM_RISCV_PGTABLE_H 8 9 #include <linux/mmzone.h> 10 #include <linux/sizes.h> 11 12 #include <asm/pgtable-bits.h> 13 14 #ifndef CONFIG_MMU 15 #define KERNEL_LINK_ADDR PAGE_OFFSET 16 #define KERN_VIRT_SIZE (UL(-1)) 17 #else 18 19 #define ADDRESS_SPACE_END (UL(-1)) 20 21 #ifdef CONFIG_64BIT 22 /* Leave 2GB for kernel and BPF at the end of the address space */ 23 #define KERNEL_LINK_ADDR (ADDRESS_SPACE_END - SZ_2G + 1) 24 #else 25 #define KERNEL_LINK_ADDR PAGE_OFFSET 26 #endif 27 28 /* Number of entries in the page global directory */ 29 #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) 30 /* Number of entries in the page table */ 31 #define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t)) 32 33 /* 34 * Half of the kernel address space (1/4 of the entries of the page global 35 * directory) is for the direct mapping. 36 */ 37 #define KERN_VIRT_SIZE ((PTRS_PER_PGD / 2 * PGDIR_SIZE) / 2) 38 39 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) 40 #define VMALLOC_END PAGE_OFFSET 41 #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) 42 43 #define BPF_JIT_REGION_SIZE (SZ_128M) 44 #ifdef CONFIG_64BIT 45 #define BPF_JIT_REGION_START (BPF_JIT_REGION_END - BPF_JIT_REGION_SIZE) 46 #define BPF_JIT_REGION_END (MODULES_END) 47 #else 48 #define BPF_JIT_REGION_START (PAGE_OFFSET - BPF_JIT_REGION_SIZE) 49 #define BPF_JIT_REGION_END (VMALLOC_END) 50 #endif 51 52 /* Modules always live before the kernel */ 53 #ifdef CONFIG_64BIT 54 /* This is used to define the end of the KASAN shadow region */ 55 #define MODULES_LOWEST_VADDR (KERNEL_LINK_ADDR - SZ_2G) 56 #define MODULES_VADDR (PFN_ALIGN((unsigned long)&_end) - SZ_2G) 57 #define MODULES_END (PFN_ALIGN((unsigned long)&_start)) 58 #endif 59 60 /* 61 * Roughly size the vmemmap space to be large enough to fit enough 62 * struct pages to map half the virtual address space. Then 63 * position vmemmap directly below the VMALLOC region. 64 */ 65 #define VA_BITS_SV32 32 66 #ifdef CONFIG_64BIT 67 #define VA_BITS_SV39 39 68 #define VA_BITS_SV48 48 69 #define VA_BITS_SV57 57 70 71 #define VA_BITS (pgtable_l5_enabled ? \ 72 VA_BITS_SV57 : (pgtable_l4_enabled ? VA_BITS_SV48 : VA_BITS_SV39)) 73 #else 74 #define VA_BITS VA_BITS_SV32 75 #endif 76 77 #define VMEMMAP_SHIFT \ 78 (VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT) 79 #define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT) 80 #define VMEMMAP_END VMALLOC_START 81 #define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE) 82 83 /* 84 * Define vmemmap for pfn_to_page & page_to_pfn calls. Needed if kernel 85 * is configured with CONFIG_SPARSEMEM_VMEMMAP enabled. 86 */ 87 #define vmemmap ((struct page *)VMEMMAP_START) 88 89 #define PCI_IO_SIZE SZ_16M 90 #define PCI_IO_END VMEMMAP_START 91 #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) 92 93 #define FIXADDR_TOP PCI_IO_START 94 #ifdef CONFIG_64BIT 95 #define MAX_FDT_SIZE PMD_SIZE 96 #define FIX_FDT_SIZE (MAX_FDT_SIZE + SZ_2M) 97 #define FIXADDR_SIZE (PMD_SIZE + FIX_FDT_SIZE) 98 #else 99 #define MAX_FDT_SIZE PGDIR_SIZE 100 #define FIX_FDT_SIZE MAX_FDT_SIZE 101 #define FIXADDR_SIZE (PGDIR_SIZE + FIX_FDT_SIZE) 102 #endif 103 #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) 104 105 #endif 106 107 #ifdef CONFIG_XIP_KERNEL 108 #define XIP_OFFSET SZ_32M 109 #define XIP_OFFSET_MASK (SZ_32M - 1) 110 #else 111 #define XIP_OFFSET 0 112 #endif 113 114 #ifndef __ASSEMBLY__ 115 116 #include <asm/page.h> 117 #include <asm/tlbflush.h> 118 #include <linux/mm_types.h> 119 #include <asm/compat.h> 120 121 #define __page_val_to_pfn(_val) (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT) 122 123 #ifdef CONFIG_64BIT 124 #include <asm/pgtable-64.h> 125 126 #define VA_USER_SV39 (UL(1) << (VA_BITS_SV39 - 1)) 127 #define VA_USER_SV48 (UL(1) << (VA_BITS_SV48 - 1)) 128 #define VA_USER_SV57 (UL(1) << (VA_BITS_SV57 - 1)) 129 130 #ifdef CONFIG_COMPAT 131 #define MMAP_VA_BITS_64 ((VA_BITS >= VA_BITS_SV48) ? VA_BITS_SV48 : VA_BITS) 132 #define MMAP_MIN_VA_BITS_64 (VA_BITS_SV39) 133 #define MMAP_VA_BITS (is_compat_task() ? VA_BITS_SV32 : MMAP_VA_BITS_64) 134 #define MMAP_MIN_VA_BITS (is_compat_task() ? VA_BITS_SV32 : MMAP_MIN_VA_BITS_64) 135 #else 136 #define MMAP_VA_BITS ((VA_BITS >= VA_BITS_SV48) ? VA_BITS_SV48 : VA_BITS) 137 #define MMAP_MIN_VA_BITS (VA_BITS_SV39) 138 #endif /* CONFIG_COMPAT */ 139 140 #else 141 #include <asm/pgtable-32.h> 142 #endif /* CONFIG_64BIT */ 143 144 #include <linux/page_table_check.h> 145 146 #ifdef CONFIG_XIP_KERNEL 147 #define XIP_FIXUP(addr) ({ \ 148 uintptr_t __a = (uintptr_t)(addr); \ 149 (__a >= CONFIG_XIP_PHYS_ADDR && \ 150 __a < CONFIG_XIP_PHYS_ADDR + XIP_OFFSET * 2) ? \ 151 __a - CONFIG_XIP_PHYS_ADDR + CONFIG_PHYS_RAM_BASE - XIP_OFFSET :\ 152 __a; \ 153 }) 154 #else 155 #define XIP_FIXUP(addr) (addr) 156 #endif /* CONFIG_XIP_KERNEL */ 157 158 struct pt_alloc_ops { 159 pte_t *(*get_pte_virt)(phys_addr_t pa); 160 phys_addr_t (*alloc_pte)(uintptr_t va); 161 #ifndef __PAGETABLE_PMD_FOLDED 162 pmd_t *(*get_pmd_virt)(phys_addr_t pa); 163 phys_addr_t (*alloc_pmd)(uintptr_t va); 164 pud_t *(*get_pud_virt)(phys_addr_t pa); 165 phys_addr_t (*alloc_pud)(uintptr_t va); 166 p4d_t *(*get_p4d_virt)(phys_addr_t pa); 167 phys_addr_t (*alloc_p4d)(uintptr_t va); 168 #endif 169 }; 170 171 extern struct pt_alloc_ops pt_ops __initdata; 172 173 #ifdef CONFIG_MMU 174 /* Number of PGD entries that a user-mode program can use */ 175 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 176 177 /* Page protection bits */ 178 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER) 179 180 #define PAGE_NONE __pgprot(_PAGE_PROT_NONE | _PAGE_READ) 181 #define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ) 182 #define PAGE_WRITE __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_WRITE) 183 #define PAGE_EXEC __pgprot(_PAGE_BASE | _PAGE_EXEC) 184 #define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 185 #define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \ 186 _PAGE_EXEC | _PAGE_WRITE) 187 188 #define PAGE_COPY PAGE_READ 189 #define PAGE_COPY_EXEC PAGE_READ_EXEC 190 #define PAGE_SHARED PAGE_WRITE 191 #define PAGE_SHARED_EXEC PAGE_WRITE_EXEC 192 193 #define _PAGE_KERNEL (_PAGE_READ \ 194 | _PAGE_WRITE \ 195 | _PAGE_PRESENT \ 196 | _PAGE_ACCESSED \ 197 | _PAGE_DIRTY \ 198 | _PAGE_GLOBAL) 199 200 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 201 #define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE) 202 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL | _PAGE_EXEC) 203 #define PAGE_KERNEL_READ_EXEC __pgprot((_PAGE_KERNEL & ~_PAGE_WRITE) \ 204 | _PAGE_EXEC) 205 206 #define PAGE_TABLE __pgprot(_PAGE_TABLE) 207 208 #define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO) 209 #define PAGE_KERNEL_IO __pgprot(_PAGE_IOREMAP) 210 211 extern pgd_t swapper_pg_dir[]; 212 extern pgd_t trampoline_pg_dir[]; 213 extern pgd_t early_pg_dir[]; 214 215 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 216 static inline int pmd_present(pmd_t pmd) 217 { 218 /* 219 * Checking for _PAGE_LEAF is needed too because: 220 * When splitting a THP, split_huge_page() will temporarily clear 221 * the present bit, in this situation, pmd_present() and 222 * pmd_trans_huge() still needs to return true. 223 */ 224 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE | _PAGE_LEAF)); 225 } 226 #else 227 static inline int pmd_present(pmd_t pmd) 228 { 229 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 230 } 231 #endif 232 233 static inline int pmd_none(pmd_t pmd) 234 { 235 return (pmd_val(pmd) == 0); 236 } 237 238 static inline int pmd_bad(pmd_t pmd) 239 { 240 return !pmd_present(pmd) || (pmd_val(pmd) & _PAGE_LEAF); 241 } 242 243 #define pmd_leaf pmd_leaf 244 static inline int pmd_leaf(pmd_t pmd) 245 { 246 return pmd_present(pmd) && (pmd_val(pmd) & _PAGE_LEAF); 247 } 248 249 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 250 { 251 WRITE_ONCE(*pmdp, pmd); 252 } 253 254 static inline void pmd_clear(pmd_t *pmdp) 255 { 256 set_pmd(pmdp, __pmd(0)); 257 } 258 259 static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot) 260 { 261 unsigned long prot_val = pgprot_val(prot); 262 263 ALT_THEAD_PMA(prot_val); 264 265 return __pgd((pfn << _PAGE_PFN_SHIFT) | prot_val); 266 } 267 268 static inline unsigned long _pgd_pfn(pgd_t pgd) 269 { 270 return __page_val_to_pfn(pgd_val(pgd)); 271 } 272 273 static inline struct page *pmd_page(pmd_t pmd) 274 { 275 return pfn_to_page(__page_val_to_pfn(pmd_val(pmd))); 276 } 277 278 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 279 { 280 return (unsigned long)pfn_to_virt(__page_val_to_pfn(pmd_val(pmd))); 281 } 282 283 static inline pte_t pmd_pte(pmd_t pmd) 284 { 285 return __pte(pmd_val(pmd)); 286 } 287 288 static inline pte_t pud_pte(pud_t pud) 289 { 290 return __pte(pud_val(pud)); 291 } 292 293 #ifdef CONFIG_RISCV_ISA_SVNAPOT 294 #include <asm/cpufeature.h> 295 296 static __always_inline bool has_svnapot(void) 297 { 298 return riscv_has_extension_likely(RISCV_ISA_EXT_SVNAPOT); 299 } 300 301 static inline unsigned long pte_napot(pte_t pte) 302 { 303 return pte_val(pte) & _PAGE_NAPOT; 304 } 305 306 static inline pte_t pte_mknapot(pte_t pte, unsigned int order) 307 { 308 int pos = order - 1 + _PAGE_PFN_SHIFT; 309 unsigned long napot_bit = BIT(pos); 310 unsigned long napot_mask = ~GENMASK(pos, _PAGE_PFN_SHIFT); 311 312 return __pte((pte_val(pte) & napot_mask) | napot_bit | _PAGE_NAPOT); 313 } 314 315 #else 316 317 static __always_inline bool has_svnapot(void) { return false; } 318 319 static inline unsigned long pte_napot(pte_t pte) 320 { 321 return 0; 322 } 323 324 #endif /* CONFIG_RISCV_ISA_SVNAPOT */ 325 326 /* Yields the page frame number (PFN) of a page table entry */ 327 static inline unsigned long pte_pfn(pte_t pte) 328 { 329 unsigned long res = __page_val_to_pfn(pte_val(pte)); 330 331 if (has_svnapot() && pte_napot(pte)) 332 res = res & (res - 1UL); 333 334 return res; 335 } 336 337 #define pte_page(x) pfn_to_page(pte_pfn(x)) 338 339 /* Constructs a page table entry */ 340 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 341 { 342 unsigned long prot_val = pgprot_val(prot); 343 344 ALT_THEAD_PMA(prot_val); 345 346 return __pte((pfn << _PAGE_PFN_SHIFT) | prot_val); 347 } 348 349 #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) 350 351 static inline int pte_present(pte_t pte) 352 { 353 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 354 } 355 356 static inline int pte_none(pte_t pte) 357 { 358 return (pte_val(pte) == 0); 359 } 360 361 static inline int pte_write(pte_t pte) 362 { 363 return pte_val(pte) & _PAGE_WRITE; 364 } 365 366 static inline int pte_exec(pte_t pte) 367 { 368 return pte_val(pte) & _PAGE_EXEC; 369 } 370 371 static inline int pte_user(pte_t pte) 372 { 373 return pte_val(pte) & _PAGE_USER; 374 } 375 376 static inline int pte_huge(pte_t pte) 377 { 378 return pte_present(pte) && (pte_val(pte) & _PAGE_LEAF); 379 } 380 381 static inline int pte_dirty(pte_t pte) 382 { 383 return pte_val(pte) & _PAGE_DIRTY; 384 } 385 386 static inline int pte_young(pte_t pte) 387 { 388 return pte_val(pte) & _PAGE_ACCESSED; 389 } 390 391 static inline int pte_special(pte_t pte) 392 { 393 return pte_val(pte) & _PAGE_SPECIAL; 394 } 395 396 /* static inline pte_t pte_rdprotect(pte_t pte) */ 397 398 static inline pte_t pte_wrprotect(pte_t pte) 399 { 400 return __pte(pte_val(pte) & ~(_PAGE_WRITE)); 401 } 402 403 /* static inline pte_t pte_mkread(pte_t pte) */ 404 405 static inline pte_t pte_mkwrite_novma(pte_t pte) 406 { 407 return __pte(pte_val(pte) | _PAGE_WRITE); 408 } 409 410 /* static inline pte_t pte_mkexec(pte_t pte) */ 411 412 static inline pte_t pte_mkdirty(pte_t pte) 413 { 414 return __pte(pte_val(pte) | _PAGE_DIRTY); 415 } 416 417 static inline pte_t pte_mkclean(pte_t pte) 418 { 419 return __pte(pte_val(pte) & ~(_PAGE_DIRTY)); 420 } 421 422 static inline pte_t pte_mkyoung(pte_t pte) 423 { 424 return __pte(pte_val(pte) | _PAGE_ACCESSED); 425 } 426 427 static inline pte_t pte_mkold(pte_t pte) 428 { 429 return __pte(pte_val(pte) & ~(_PAGE_ACCESSED)); 430 } 431 432 static inline pte_t pte_mkspecial(pte_t pte) 433 { 434 return __pte(pte_val(pte) | _PAGE_SPECIAL); 435 } 436 437 static inline pte_t pte_mkhuge(pte_t pte) 438 { 439 return pte; 440 } 441 442 #ifdef CONFIG_NUMA_BALANCING 443 /* 444 * See the comment in include/asm-generic/pgtable.h 445 */ 446 static inline int pte_protnone(pte_t pte) 447 { 448 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)) == _PAGE_PROT_NONE; 449 } 450 451 static inline int pmd_protnone(pmd_t pmd) 452 { 453 return pte_protnone(pmd_pte(pmd)); 454 } 455 #endif 456 457 /* Modify page protection bits */ 458 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 459 { 460 unsigned long newprot_val = pgprot_val(newprot); 461 462 ALT_THEAD_PMA(newprot_val); 463 464 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | newprot_val); 465 } 466 467 #define pgd_ERROR(e) \ 468 pr_err("%s:%d: bad pgd " PTE_FMT ".\n", __FILE__, __LINE__, pgd_val(e)) 469 470 471 /* Commit new configuration to MMU hardware */ 472 static inline void update_mmu_cache_range(struct vm_fault *vmf, 473 struct vm_area_struct *vma, unsigned long address, 474 pte_t *ptep, unsigned int nr) 475 { 476 /* 477 * The kernel assumes that TLBs don't cache invalid entries, but 478 * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a 479 * cache flush; it is necessary even after writing invalid entries. 480 * Relying on flush_tlb_fix_spurious_fault would suffice, but 481 * the extra traps reduce performance. So, eagerly SFENCE.VMA. 482 */ 483 while (nr--) 484 local_flush_tlb_page(address + nr * PAGE_SIZE); 485 } 486 #define update_mmu_cache(vma, addr, ptep) \ 487 update_mmu_cache_range(NULL, vma, addr, ptep, 1) 488 489 #define __HAVE_ARCH_UPDATE_MMU_TLB 490 #define update_mmu_tlb update_mmu_cache 491 492 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 493 unsigned long address, pmd_t *pmdp) 494 { 495 pte_t *ptep = (pte_t *)pmdp; 496 497 update_mmu_cache(vma, address, ptep); 498 } 499 500 #define __HAVE_ARCH_PTE_SAME 501 static inline int pte_same(pte_t pte_a, pte_t pte_b) 502 { 503 return pte_val(pte_a) == pte_val(pte_b); 504 } 505 506 /* 507 * Certain architectures need to do special things when PTEs within 508 * a page table are directly modified. Thus, the following hook is 509 * made available. 510 */ 511 static inline void set_pte(pte_t *ptep, pte_t pteval) 512 { 513 WRITE_ONCE(*ptep, pteval); 514 } 515 516 void flush_icache_pte(pte_t pte); 517 518 static inline void __set_pte_at(pte_t *ptep, pte_t pteval) 519 { 520 if (pte_present(pteval) && pte_exec(pteval)) 521 flush_icache_pte(pteval); 522 523 set_pte(ptep, pteval); 524 } 525 526 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 527 pte_t *ptep, pte_t pteval, unsigned int nr) 528 { 529 page_table_check_ptes_set(mm, ptep, pteval, nr); 530 531 for (;;) { 532 __set_pte_at(ptep, pteval); 533 if (--nr == 0) 534 break; 535 ptep++; 536 pte_val(pteval) += 1 << _PAGE_PFN_SHIFT; 537 } 538 } 539 #define set_ptes set_ptes 540 541 static inline void pte_clear(struct mm_struct *mm, 542 unsigned long addr, pte_t *ptep) 543 { 544 __set_pte_at(ptep, __pte(0)); 545 } 546 547 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS /* defined in mm/pgtable.c */ 548 extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address, 549 pte_t *ptep, pte_t entry, int dirty); 550 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG /* defined in mm/pgtable.c */ 551 extern int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long address, 552 pte_t *ptep); 553 554 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 555 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 556 unsigned long address, pte_t *ptep) 557 { 558 pte_t pte = __pte(atomic_long_xchg((atomic_long_t *)ptep, 0)); 559 560 page_table_check_pte_clear(mm, pte); 561 562 return pte; 563 } 564 565 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 566 static inline void ptep_set_wrprotect(struct mm_struct *mm, 567 unsigned long address, pte_t *ptep) 568 { 569 atomic_long_and(~(unsigned long)_PAGE_WRITE, (atomic_long_t *)ptep); 570 } 571 572 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 573 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 574 unsigned long address, pte_t *ptep) 575 { 576 /* 577 * This comment is borrowed from x86, but applies equally to RISC-V: 578 * 579 * Clearing the accessed bit without a TLB flush 580 * doesn't cause data corruption. [ It could cause incorrect 581 * page aging and the (mistaken) reclaim of hot pages, but the 582 * chance of that should be relatively low. ] 583 * 584 * So as a performance optimization don't flush the TLB when 585 * clearing the accessed bit, it will eventually be flushed by 586 * a context switch or a VM operation anyway. [ In the rare 587 * event of it not getting flushed for a long time the delay 588 * shouldn't really matter because there's no real memory 589 * pressure for swapout to react to. ] 590 */ 591 return ptep_test_and_clear_young(vma, address, ptep); 592 } 593 594 #define pgprot_noncached pgprot_noncached 595 static inline pgprot_t pgprot_noncached(pgprot_t _prot) 596 { 597 unsigned long prot = pgprot_val(_prot); 598 599 prot &= ~_PAGE_MTMASK; 600 prot |= _PAGE_IO; 601 602 return __pgprot(prot); 603 } 604 605 #define pgprot_writecombine pgprot_writecombine 606 static inline pgprot_t pgprot_writecombine(pgprot_t _prot) 607 { 608 unsigned long prot = pgprot_val(_prot); 609 610 prot &= ~_PAGE_MTMASK; 611 prot |= _PAGE_NOCACHE; 612 613 return __pgprot(prot); 614 } 615 616 /* 617 * THP functions 618 */ 619 static inline pmd_t pte_pmd(pte_t pte) 620 { 621 return __pmd(pte_val(pte)); 622 } 623 624 static inline pmd_t pmd_mkhuge(pmd_t pmd) 625 { 626 return pmd; 627 } 628 629 static inline pmd_t pmd_mkinvalid(pmd_t pmd) 630 { 631 return __pmd(pmd_val(pmd) & ~(_PAGE_PRESENT|_PAGE_PROT_NONE)); 632 } 633 634 #define __pmd_to_phys(pmd) (__page_val_to_pfn(pmd_val(pmd)) << PAGE_SHIFT) 635 636 static inline unsigned long pmd_pfn(pmd_t pmd) 637 { 638 return ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT); 639 } 640 641 #define __pud_to_phys(pud) (__page_val_to_pfn(pud_val(pud)) << PAGE_SHIFT) 642 643 static inline unsigned long pud_pfn(pud_t pud) 644 { 645 return ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT); 646 } 647 648 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 649 { 650 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 651 } 652 653 #define pmd_write pmd_write 654 static inline int pmd_write(pmd_t pmd) 655 { 656 return pte_write(pmd_pte(pmd)); 657 } 658 659 #define pmd_dirty pmd_dirty 660 static inline int pmd_dirty(pmd_t pmd) 661 { 662 return pte_dirty(pmd_pte(pmd)); 663 } 664 665 #define pmd_young pmd_young 666 static inline int pmd_young(pmd_t pmd) 667 { 668 return pte_young(pmd_pte(pmd)); 669 } 670 671 static inline int pmd_user(pmd_t pmd) 672 { 673 return pte_user(pmd_pte(pmd)); 674 } 675 676 static inline pmd_t pmd_mkold(pmd_t pmd) 677 { 678 return pte_pmd(pte_mkold(pmd_pte(pmd))); 679 } 680 681 static inline pmd_t pmd_mkyoung(pmd_t pmd) 682 { 683 return pte_pmd(pte_mkyoung(pmd_pte(pmd))); 684 } 685 686 static inline pmd_t pmd_mkwrite_novma(pmd_t pmd) 687 { 688 return pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))); 689 } 690 691 static inline pmd_t pmd_wrprotect(pmd_t pmd) 692 { 693 return pte_pmd(pte_wrprotect(pmd_pte(pmd))); 694 } 695 696 static inline pmd_t pmd_mkclean(pmd_t pmd) 697 { 698 return pte_pmd(pte_mkclean(pmd_pte(pmd))); 699 } 700 701 static inline pmd_t pmd_mkdirty(pmd_t pmd) 702 { 703 return pte_pmd(pte_mkdirty(pmd_pte(pmd))); 704 } 705 706 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 707 pmd_t *pmdp, pmd_t pmd) 708 { 709 page_table_check_pmd_set(mm, pmdp, pmd); 710 return __set_pte_at((pte_t *)pmdp, pmd_pte(pmd)); 711 } 712 713 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 714 pud_t *pudp, pud_t pud) 715 { 716 page_table_check_pud_set(mm, pudp, pud); 717 return __set_pte_at((pte_t *)pudp, pud_pte(pud)); 718 } 719 720 #ifdef CONFIG_PAGE_TABLE_CHECK 721 static inline bool pte_user_accessible_page(pte_t pte) 722 { 723 return pte_present(pte) && pte_user(pte); 724 } 725 726 static inline bool pmd_user_accessible_page(pmd_t pmd) 727 { 728 return pmd_leaf(pmd) && pmd_user(pmd); 729 } 730 731 static inline bool pud_user_accessible_page(pud_t pud) 732 { 733 return pud_leaf(pud) && pud_user(pud); 734 } 735 #endif 736 737 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 738 static inline int pmd_trans_huge(pmd_t pmd) 739 { 740 return pmd_leaf(pmd); 741 } 742 743 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 744 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 745 unsigned long address, pmd_t *pmdp, 746 pmd_t entry, int dirty) 747 { 748 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 749 } 750 751 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 752 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 753 unsigned long address, pmd_t *pmdp) 754 { 755 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 756 } 757 758 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 759 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 760 unsigned long address, pmd_t *pmdp) 761 { 762 pmd_t pmd = __pmd(atomic_long_xchg((atomic_long_t *)pmdp, 0)); 763 764 page_table_check_pmd_clear(mm, pmd); 765 766 return pmd; 767 } 768 769 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 770 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 771 unsigned long address, pmd_t *pmdp) 772 { 773 ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 774 } 775 776 #define pmdp_establish pmdp_establish 777 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 778 unsigned long address, pmd_t *pmdp, pmd_t pmd) 779 { 780 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 781 return __pmd(atomic_long_xchg((atomic_long_t *)pmdp, pmd_val(pmd))); 782 } 783 784 #define pmdp_collapse_flush pmdp_collapse_flush 785 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 786 unsigned long address, pmd_t *pmdp); 787 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 788 789 /* 790 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that 791 * are !pte_none() && !pte_present(). 792 * 793 * Format of swap PTE: 794 * bit 0: _PAGE_PRESENT (zero) 795 * bit 1 to 3: _PAGE_LEAF (zero) 796 * bit 5: _PAGE_PROT_NONE (zero) 797 * bit 6: exclusive marker 798 * bits 7 to 11: swap type 799 * bits 12 to XLEN-1: swap offset 800 */ 801 #define __SWP_TYPE_SHIFT 7 802 #define __SWP_TYPE_BITS 5 803 #define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1) 804 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 805 806 #define MAX_SWAPFILES_CHECK() \ 807 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 808 809 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 810 #define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) 811 #define __swp_entry(type, offset) ((swp_entry_t) \ 812 { (((type) & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT) | \ 813 ((offset) << __SWP_OFFSET_SHIFT) }) 814 815 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 816 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 817 818 static inline int pte_swp_exclusive(pte_t pte) 819 { 820 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 821 } 822 823 static inline pte_t pte_swp_mkexclusive(pte_t pte) 824 { 825 return __pte(pte_val(pte) | _PAGE_SWP_EXCLUSIVE); 826 } 827 828 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 829 { 830 return __pte(pte_val(pte) & ~_PAGE_SWP_EXCLUSIVE); 831 } 832 833 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 834 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 835 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 836 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 837 838 /* 839 * In the RV64 Linux scheme, we give the user half of the virtual-address space 840 * and give the kernel the other (upper) half. 841 */ 842 #ifdef CONFIG_64BIT 843 #define KERN_VIRT_START (-(BIT(VA_BITS)) + TASK_SIZE) 844 #else 845 #define KERN_VIRT_START FIXADDR_START 846 #endif 847 848 /* 849 * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32. 850 * Note that PGDIR_SIZE must evenly divide TASK_SIZE. 851 * Task size is: 852 * - 0x9fc00000 (~2.5GB) for RV32. 853 * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu 854 * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu 855 * - 0x100000000000000 ( 64PB) for RV64 using SV57 mmu 856 * 857 * Note that PGDIR_SIZE must evenly divide TASK_SIZE since "RISC-V 858 * Instruction Set Manual Volume II: Privileged Architecture" states that 859 * "load and store effective addresses, which are 64bits, must have bits 860 * 63–48 all equal to bit 47, or else a page-fault exception will occur." 861 * Similarly for SV57, bits 63–57 must be equal to bit 56. 862 */ 863 #ifdef CONFIG_64BIT 864 #define TASK_SIZE_64 (PGDIR_SIZE * PTRS_PER_PGD / 2) 865 #define TASK_SIZE_MIN (PGDIR_SIZE_L3 * PTRS_PER_PGD / 2) 866 867 #ifdef CONFIG_COMPAT 868 #define TASK_SIZE_32 (_AC(0x80000000, UL)) 869 #define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \ 870 TASK_SIZE_32 : TASK_SIZE_64) 871 #else 872 #define TASK_SIZE TASK_SIZE_64 873 #endif 874 875 #else 876 #define TASK_SIZE FIXADDR_START 877 #define TASK_SIZE_MIN TASK_SIZE 878 #endif 879 880 #else /* CONFIG_MMU */ 881 882 #define PAGE_SHARED __pgprot(0) 883 #define PAGE_KERNEL __pgprot(0) 884 #define swapper_pg_dir NULL 885 #define TASK_SIZE 0xffffffffUL 886 #define VMALLOC_START _AC(0, UL) 887 #define VMALLOC_END TASK_SIZE 888 889 #endif /* !CONFIG_MMU */ 890 891 extern char _start[]; 892 extern void *_dtb_early_va; 893 extern uintptr_t _dtb_early_pa; 894 #if defined(CONFIG_XIP_KERNEL) && defined(CONFIG_MMU) 895 #define dtb_early_va (*(void **)XIP_FIXUP(&_dtb_early_va)) 896 #define dtb_early_pa (*(uintptr_t *)XIP_FIXUP(&_dtb_early_pa)) 897 #else 898 #define dtb_early_va _dtb_early_va 899 #define dtb_early_pa _dtb_early_pa 900 #endif /* CONFIG_XIP_KERNEL */ 901 extern u64 satp_mode; 902 903 void paging_init(void); 904 void misc_mem_init(void); 905 906 /* 907 * ZERO_PAGE is a global shared page that is always zero, 908 * used for zero-mapped memory areas, etc. 909 */ 910 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 911 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 912 913 #endif /* !__ASSEMBLY__ */ 914 915 #endif /* _ASM_RISCV_PGTABLE_H */ 916