1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Renesas Solutions Highlander R7785RP Support.
4  *
5  * Copyright (C) 2002  Atom Create Engineering Co., Ltd.
6  * Copyright (C) 2006 - 2008  Paul Mundt
7  * Copyright (C) 2007  Magnus Damm
8  */
9 #include <linux/init.h>
10 #include <linux/irq.h>
11 #include <linux/io.h>
12 #include <mach/highlander.h>
13 
14 enum {
15 	UNUSED = 0,
16 
17 	/* FPGA specific interrupt sources */
18 	CF,		/* Compact Flash */
19 	SMBUS,		/* SMBUS */
20 	TP,		/* Touch panel */
21 	RTC,		/* RTC Alarm */
22 	TH_ALERT,	/* Temperature sensor */
23 	AX88796,	/* Ethernet controller */
24 
25 	/* external bus connector */
26 	EXT0, EXT1, EXT2, EXT3, EXT4, EXT5, EXT6, EXT7,
27 };
28 
29 static struct intc_vect vectors[] __initdata = {
30 	INTC_IRQ(CF, IRQ_CF),
31 	INTC_IRQ(SMBUS, IRQ_SMBUS),
32 	INTC_IRQ(TP, IRQ_TP),
33 	INTC_IRQ(RTC, IRQ_RTC),
34 	INTC_IRQ(TH_ALERT, IRQ_TH_ALERT),
35 
36 	INTC_IRQ(EXT0, IRQ_EXT0), INTC_IRQ(EXT1, IRQ_EXT1),
37 	INTC_IRQ(EXT2, IRQ_EXT2), INTC_IRQ(EXT3, IRQ_EXT3),
38 
39 	INTC_IRQ(EXT4, IRQ_EXT4), INTC_IRQ(EXT5, IRQ_EXT5),
40 	INTC_IRQ(EXT6, IRQ_EXT6), INTC_IRQ(EXT7, IRQ_EXT7),
41 
42 	INTC_IRQ(AX88796, IRQ_AX88796),
43 };
44 
45 static struct intc_mask_reg mask_registers[] __initdata = {
46 	{ 0xa4000010, 0, 16, /* IRLMCR1 */
47 	  { 0, 0, 0, 0, CF, AX88796, SMBUS, TP,
48 	    RTC, 0, TH_ALERT, 0, 0, 0, 0, 0 } },
49 	{ 0xa4000012, 0, 16, /* IRLMCR2 */
50 	  { 0, 0, 0, 0, 0, 0, 0, 0,
51 	    EXT7, EXT6, EXT5, EXT4, EXT3, EXT2, EXT1, EXT0 } },
52 };
53 
54 static unsigned char irl2irq[HL_NR_IRL] __initdata = {
55 	0, IRQ_CF, IRQ_EXT4, IRQ_EXT5,
56 	IRQ_EXT6, IRQ_EXT7, IRQ_SMBUS, IRQ_TP,
57 	IRQ_RTC, IRQ_TH_ALERT, IRQ_AX88796, IRQ_EXT0,
58 	IRQ_EXT1, IRQ_EXT2, IRQ_EXT3,
59 };
60 
61 static DECLARE_INTC_DESC(intc_desc, "r7785rp", vectors,
62 			 NULL, mask_registers, NULL, NULL);
63 
64 unsigned char * __init highlander_plat_irq_setup(void)
65 {
66 	if ((__raw_readw(0xa4000158) & 0xf000) != 0x1000)
67 		return NULL;
68 
69 	printk(KERN_INFO "Using r7785rp interrupt controller.\n");
70 
71 	__raw_writew(0x0000, PA_IRLSSR1);	/* FPGA IRLSSR1(CF_CD clear) */
72 
73 	/* Setup the FPGA IRL */
74 	__raw_writew(0x0000, PA_IRLPRA);	/* FPGA IRLA */
75 	__raw_writew(0xe598, PA_IRLPRB);	/* FPGA IRLB */
76 	__raw_writew(0x7060, PA_IRLPRC);	/* FPGA IRLC */
77 	__raw_writew(0x0000, PA_IRLPRD);	/* FPGA IRLD */
78 	__raw_writew(0x4321, PA_IRLPRE);	/* FPGA IRLE */
79 	__raw_writew(0xdcba, PA_IRLPRF);	/* FPGA IRLF */
80 
81 	register_intc_controller(&intc_desc);
82 	return irl2irq;
83 }
84