1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2f15cbe6fSPaul Mundt /* 3f15cbe6fSPaul Mundt * sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver. 4f15cbe6fSPaul Mundt * 5f15cbe6fSPaul Mundt * (c) 2006-2008 MSC Vertriebsges.m.b.H., 6f15cbe6fSPaul Mundt * Manuel Lauss <mano@roarinelk.homelinux.net> 7f15cbe6fSPaul Mundt * (c) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> 8f15cbe6fSPaul Mundt */ 9f15cbe6fSPaul Mundt 10f15cbe6fSPaul Mundt #ifndef _ASM_SH_SH7760FB_H 11f15cbe6fSPaul Mundt #define _ASM_SH_SH7760FB_H 12f15cbe6fSPaul Mundt 13f15cbe6fSPaul Mundt /* 14f15cbe6fSPaul Mundt * some bits of the colormap registers should be written as zero. 15f15cbe6fSPaul Mundt * create a mask for that. 16f15cbe6fSPaul Mundt */ 17f15cbe6fSPaul Mundt #define SH7760FB_PALETTE_MASK 0x00f8fcf8 18f15cbe6fSPaul Mundt 19f15cbe6fSPaul Mundt /* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */ 20f15cbe6fSPaul Mundt #define SH7760FB_DMA_MASK 0x0C000000 21f15cbe6fSPaul Mundt 22f15cbe6fSPaul Mundt /* palette */ 23f15cbe6fSPaul Mundt #define LDPR(x) (((x) << 2)) 24f15cbe6fSPaul Mundt 25f15cbe6fSPaul Mundt /* framebuffer registers and bits */ 26f15cbe6fSPaul Mundt #define LDICKR 0x400 27f15cbe6fSPaul Mundt #define LDMTR 0x402 28f15cbe6fSPaul Mundt /* see sh7760fb.h for LDMTR bits */ 29f15cbe6fSPaul Mundt #define LDDFR 0x404 30f15cbe6fSPaul Mundt #define LDDFR_PABD (1 << 8) 31f15cbe6fSPaul Mundt #define LDDFR_COLOR_MASK 0x7F 32f15cbe6fSPaul Mundt #define LDSMR 0x406 33f15cbe6fSPaul Mundt #define LDSMR_ROT (1 << 13) 34f15cbe6fSPaul Mundt #define LDSARU 0x408 35f15cbe6fSPaul Mundt #define LDSARL 0x40c 36f15cbe6fSPaul Mundt #define LDLAOR 0x410 37f15cbe6fSPaul Mundt #define LDPALCR 0x412 38f15cbe6fSPaul Mundt #define LDPALCR_PALS (1 << 4) 39f15cbe6fSPaul Mundt #define LDPALCR_PALEN (1 << 0) 40f15cbe6fSPaul Mundt #define LDHCNR 0x414 41f15cbe6fSPaul Mundt #define LDHSYNR 0x416 42f15cbe6fSPaul Mundt #define LDVDLNR 0x418 43f15cbe6fSPaul Mundt #define LDVTLNR 0x41a 44f15cbe6fSPaul Mundt #define LDVSYNR 0x41c 45f15cbe6fSPaul Mundt #define LDACLNR 0x41e 46f15cbe6fSPaul Mundt #define LDINTR 0x420 47f15cbe6fSPaul Mundt #define LDPMMR 0x424 48f15cbe6fSPaul Mundt #define LDPSPR 0x426 49f15cbe6fSPaul Mundt #define LDCNTR 0x428 50f15cbe6fSPaul Mundt #define LDCNTR_DON (1 << 0) 51f15cbe6fSPaul Mundt #define LDCNTR_DON2 (1 << 4) 52f15cbe6fSPaul Mundt 53f15cbe6fSPaul Mundt #ifdef CONFIG_CPU_SUBTYPE_SH7763 54f15cbe6fSPaul Mundt # define LDLIRNR 0x440 55f15cbe6fSPaul Mundt /* LDINTR bit */ 56f15cbe6fSPaul Mundt # define LDINTR_MINTEN (1 << 15) 57f15cbe6fSPaul Mundt # define LDINTR_FINTEN (1 << 14) 58f15cbe6fSPaul Mundt # define LDINTR_VSINTEN (1 << 13) 59f15cbe6fSPaul Mundt # define LDINTR_VEINTEN (1 << 12) 60f15cbe6fSPaul Mundt # define LDINTR_MINTS (1 << 11) 61f15cbe6fSPaul Mundt # define LDINTR_FINTS (1 << 10) 62f15cbe6fSPaul Mundt # define LDINTR_VSINTS (1 << 9) 63f15cbe6fSPaul Mundt # define LDINTR_VEINTS (1 << 8) 64f15cbe6fSPaul Mundt # define VINT_START (LDINTR_VSINTEN) 65f15cbe6fSPaul Mundt # define VINT_CHECK (LDINTR_VSINTS) 66f15cbe6fSPaul Mundt #else 67f15cbe6fSPaul Mundt /* LDINTR bit */ 68f15cbe6fSPaul Mundt # define LDINTR_VINTSEL (1 << 12) 69f15cbe6fSPaul Mundt # define LDINTR_VINTE (1 << 8) 70f15cbe6fSPaul Mundt # define LDINTR_VINTS (1 << 0) 71f15cbe6fSPaul Mundt # define VINT_START (LDINTR_VINTSEL) 72f15cbe6fSPaul Mundt # define VINT_CHECK (LDINTR_VINTS) 73f15cbe6fSPaul Mundt #endif 74f15cbe6fSPaul Mundt 75f15cbe6fSPaul Mundt /* HSYNC polarity inversion */ 76f15cbe6fSPaul Mundt #define LDMTR_FLMPOL (1 << 15) 77f15cbe6fSPaul Mundt 78f15cbe6fSPaul Mundt /* VSYNC polarity inversion */ 79f15cbe6fSPaul Mundt #define LDMTR_CL1POL (1 << 14) 80f15cbe6fSPaul Mundt 81f15cbe6fSPaul Mundt /* DISPLAY-ENABLE polarity inversion */ 82f15cbe6fSPaul Mundt #define LDMTR_DISPEN_LOWACT (1 << 13) 83f15cbe6fSPaul Mundt 84f15cbe6fSPaul Mundt /* DISPLAY DATA BUS polarity inversion */ 85f15cbe6fSPaul Mundt #define LDMTR_DPOL_LOWACT (1 << 12) 86f15cbe6fSPaul Mundt 87f15cbe6fSPaul Mundt /* AC modulation signal enable */ 88f15cbe6fSPaul Mundt #define LDMTR_MCNT (1 << 10) 89f15cbe6fSPaul Mundt 90f15cbe6fSPaul Mundt /* Disable output of HSYNC during VSYNC period */ 91f15cbe6fSPaul Mundt #define LDMTR_CL1CNT (1 << 9) 92f15cbe6fSPaul Mundt 93f15cbe6fSPaul Mundt /* Disable output of VSYNC during VSYNC period */ 94f15cbe6fSPaul Mundt #define LDMTR_CL2CNT (1 << 8) 95f15cbe6fSPaul Mundt 96f15cbe6fSPaul Mundt /* Display types supported by the LCDC */ 97f15cbe6fSPaul Mundt #define LDMTR_STN_MONO_4 0x00 98f15cbe6fSPaul Mundt #define LDMTR_STN_MONO_8 0x01 99f15cbe6fSPaul Mundt #define LDMTR_STN_COLOR_4 0x08 100f15cbe6fSPaul Mundt #define LDMTR_STN_COLOR_8 0x09 101f15cbe6fSPaul Mundt #define LDMTR_STN_COLOR_12 0x0A 102f15cbe6fSPaul Mundt #define LDMTR_STN_COLOR_16 0x0B 103f15cbe6fSPaul Mundt #define LDMTR_DSTN_MONO_8 0x11 104f15cbe6fSPaul Mundt #define LDMTR_DSTN_MONO_16 0x13 105f15cbe6fSPaul Mundt #define LDMTR_DSTN_COLOR_8 0x19 106f15cbe6fSPaul Mundt #define LDMTR_DSTN_COLOR_12 0x1A 107f15cbe6fSPaul Mundt #define LDMTR_DSTN_COLOR_16 0x1B 108f15cbe6fSPaul Mundt #define LDMTR_TFT_COLOR_16 0x2B 109f15cbe6fSPaul Mundt 110f15cbe6fSPaul Mundt /* framebuffer color layout */ 111f15cbe6fSPaul Mundt #define LDDFR_1BPP_MONO 0x00 112f15cbe6fSPaul Mundt #define LDDFR_2BPP_MONO 0x01 113f15cbe6fSPaul Mundt #define LDDFR_4BPP_MONO 0x02 114f15cbe6fSPaul Mundt #define LDDFR_6BPP_MONO 0x04 115f15cbe6fSPaul Mundt #define LDDFR_4BPP 0x0A 116f15cbe6fSPaul Mundt #define LDDFR_8BPP 0x0C 117f15cbe6fSPaul Mundt #define LDDFR_16BPP_RGB555 0x1D 118f15cbe6fSPaul Mundt #define LDDFR_16BPP_RGB565 0x2D 119f15cbe6fSPaul Mundt 120f15cbe6fSPaul Mundt /* LCDC Pixclock sources */ 121f15cbe6fSPaul Mundt #define LCDC_CLKSRC_BUSCLOCK 0 122f15cbe6fSPaul Mundt #define LCDC_CLKSRC_PERIPHERAL 1 123f15cbe6fSPaul Mundt #define LCDC_CLKSRC_EXTERNAL 2 124f15cbe6fSPaul Mundt 125f15cbe6fSPaul Mundt #define LDICKR_CLKSRC(x) \ 126f15cbe6fSPaul Mundt (((x) & 3) << 12) 127f15cbe6fSPaul Mundt 128f15cbe6fSPaul Mundt /* LCDC pixclock input divider. Set to 1 at a minimum! */ 129f15cbe6fSPaul Mundt #define LDICKR_CLKDIV(x) \ 130f15cbe6fSPaul Mundt ((x) & 0x1f) 131f15cbe6fSPaul Mundt 132f15cbe6fSPaul Mundt struct sh7760fb_platdata { 133f15cbe6fSPaul Mundt 134f15cbe6fSPaul Mundt /* Set this member to a valid fb_videmode for the display you 135f15cbe6fSPaul Mundt * wish to use. The following members must be initialized: 136f15cbe6fSPaul Mundt * xres, yres, hsync_len, vsync_len, sync, 137f15cbe6fSPaul Mundt * {left,right,upper,lower}_margin. 138f15cbe6fSPaul Mundt * The driver uses the above members to calculate register values 139f15cbe6fSPaul Mundt * and memory requirements. Other members are ignored but may 140f15cbe6fSPaul Mundt * be used by other framebuffer layer components. 141f15cbe6fSPaul Mundt */ 142f15cbe6fSPaul Mundt struct fb_videomode *def_mode; 143f15cbe6fSPaul Mundt 144f15cbe6fSPaul Mundt /* LDMTR includes display type and signal polarity. The 145f15cbe6fSPaul Mundt * HSYNC/VSYNC polarities are derived from the fb_var_screeninfo 146f15cbe6fSPaul Mundt * data above; however the polarities of the following signals 147f15cbe6fSPaul Mundt * must be encoded in the ldmtr member: 148f15cbe6fSPaul Mundt * Display Enable signal (default high-active) DISPEN_LOWACT 149f15cbe6fSPaul Mundt * Display Data signals (default high-active) DPOL_LOWACT 150f15cbe6fSPaul Mundt * AC Modulation signal (default off) MCNT 151f15cbe6fSPaul Mundt * Hsync-During-Vsync suppression (default off) CL1CNT 152f15cbe6fSPaul Mundt * Vsync-during-vsync suppression (default off) CL2CNT 153f15cbe6fSPaul Mundt * NOTE: also set a display type! 154f15cbe6fSPaul Mundt * (one of LDMTR_{STN,DSTN,TFT}_{MONO,COLOR}_{4,8,12,16}) 155f15cbe6fSPaul Mundt */ 156f15cbe6fSPaul Mundt u16 ldmtr; 157f15cbe6fSPaul Mundt 158f15cbe6fSPaul Mundt /* LDDFR controls framebuffer image format (depth, organization) 159f15cbe6fSPaul Mundt * Use ONE of the LDDFR_?BPP_* macros! 160f15cbe6fSPaul Mundt */ 161f15cbe6fSPaul Mundt u16 lddfr; 162f15cbe6fSPaul Mundt 163f15cbe6fSPaul Mundt /* LDPMMR and LDPSPR control the timing of the power signals 164f15cbe6fSPaul Mundt * for the display. Please read the SH7760 Hardware Manual, 165f15cbe6fSPaul Mundt * Chapters 30.3.17, 30.3.18 and 30.4.6! 166f15cbe6fSPaul Mundt */ 167f15cbe6fSPaul Mundt u16 ldpmmr; 168f15cbe6fSPaul Mundt u16 ldpspr; 169f15cbe6fSPaul Mundt 170f15cbe6fSPaul Mundt /* LDACLNR contains the line numbers after which the AC modulation 171f15cbe6fSPaul Mundt * signal is to toggle. Set to ZERO for TFTs or displays which 172f15cbe6fSPaul Mundt * do not need it. (Chapter 30.3.15 in SH7760 Hardware Manual). 173f15cbe6fSPaul Mundt */ 174f15cbe6fSPaul Mundt u16 ldaclnr; 175f15cbe6fSPaul Mundt 176f15cbe6fSPaul Mundt /* LDICKR contains information on pixelclock source and config. 177f15cbe6fSPaul Mundt * Please use the LDICKR_CLKSRC() and LDICKR_CLKDIV() macros. 178f15cbe6fSPaul Mundt * minimal value for CLKDIV() must be 1!. 179f15cbe6fSPaul Mundt */ 180f15cbe6fSPaul Mundt u16 ldickr; 181f15cbe6fSPaul Mundt 182f15cbe6fSPaul Mundt /* set this member to 1 if you wish to use the LCDC's hardware 183f15cbe6fSPaul Mundt * rotation function. This is limited to displays <= 320x200 184f15cbe6fSPaul Mundt * pixels resolution! 185f15cbe6fSPaul Mundt */ 186f15cbe6fSPaul Mundt int rotate; /* set to 1 to rotate 90 CCW */ 187f15cbe6fSPaul Mundt 188f15cbe6fSPaul Mundt /* set this to 1 to suppress vsync irq use. */ 189f15cbe6fSPaul Mundt int novsync; 190f15cbe6fSPaul Mundt 191f15cbe6fSPaul Mundt /* blanking hook for platform. Set this if your platform can do 192f15cbe6fSPaul Mundt * more than the LCDC in terms of blanking (e.g. disable clock 193f15cbe6fSPaul Mundt * generator / backlight power supply / etc. 194f15cbe6fSPaul Mundt */ 195f15cbe6fSPaul Mundt void (*blank) (int); 196f15cbe6fSPaul Mundt }; 197f15cbe6fSPaul Mundt 198f15cbe6fSPaul Mundt #endif /* _ASM_SH_SH7760FB_H */ 199