1*a439fe51SSam Ravnborg /* 2*a439fe51SSam Ravnborg * psr.h: This file holds the macros for masking off various parts of 3*a439fe51SSam Ravnborg * the processor status register on the Sparc. This is valid 4*a439fe51SSam Ravnborg * for Version 8. On the V9 this is renamed to the PSTATE 5*a439fe51SSam Ravnborg * register and its members are accessed as fields like 6*a439fe51SSam Ravnborg * PSTATE.PRIV for the current CPU privilege level. 7*a439fe51SSam Ravnborg * 8*a439fe51SSam Ravnborg * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu) 9*a439fe51SSam Ravnborg */ 10*a439fe51SSam Ravnborg 11*a439fe51SSam Ravnborg #ifndef __LINUX_SPARC_PSR_H 12*a439fe51SSam Ravnborg #define __LINUX_SPARC_PSR_H 13*a439fe51SSam Ravnborg 14*a439fe51SSam Ravnborg /* The Sparc PSR fields are laid out as the following: 15*a439fe51SSam Ravnborg * 16*a439fe51SSam Ravnborg * ------------------------------------------------------------------------ 17*a439fe51SSam Ravnborg * | impl | vers | icc | resv | EC | EF | PIL | S | PS | ET | CWP | 18*a439fe51SSam Ravnborg * | 31-28 | 27-24 | 23-20 | 19-14 | 13 | 12 | 11-8 | 7 | 6 | 5 | 4-0 | 19*a439fe51SSam Ravnborg * ------------------------------------------------------------------------ 20*a439fe51SSam Ravnborg */ 21*a439fe51SSam Ravnborg #define PSR_CWP 0x0000001f /* current window pointer */ 22*a439fe51SSam Ravnborg #define PSR_ET 0x00000020 /* enable traps field */ 23*a439fe51SSam Ravnborg #define PSR_PS 0x00000040 /* previous privilege level */ 24*a439fe51SSam Ravnborg #define PSR_S 0x00000080 /* current privilege level */ 25*a439fe51SSam Ravnborg #define PSR_PIL 0x00000f00 /* processor interrupt level */ 26*a439fe51SSam Ravnborg #define PSR_EF 0x00001000 /* enable floating point */ 27*a439fe51SSam Ravnborg #define PSR_EC 0x00002000 /* enable co-processor */ 28*a439fe51SSam Ravnborg #define PSR_SYSCALL 0x00004000 /* inside of a syscall */ 29*a439fe51SSam Ravnborg #define PSR_LE 0x00008000 /* SuperSparcII little-endian */ 30*a439fe51SSam Ravnborg #define PSR_ICC 0x00f00000 /* integer condition codes */ 31*a439fe51SSam Ravnborg #define PSR_C 0x00100000 /* carry bit */ 32*a439fe51SSam Ravnborg #define PSR_V 0x00200000 /* overflow bit */ 33*a439fe51SSam Ravnborg #define PSR_Z 0x00400000 /* zero bit */ 34*a439fe51SSam Ravnborg #define PSR_N 0x00800000 /* negative bit */ 35*a439fe51SSam Ravnborg #define PSR_VERS 0x0f000000 /* cpu-version field */ 36*a439fe51SSam Ravnborg #define PSR_IMPL 0xf0000000 /* cpu-implementation field */ 37*a439fe51SSam Ravnborg 38*a439fe51SSam Ravnborg #ifdef __KERNEL__ 39*a439fe51SSam Ravnborg 40*a439fe51SSam Ravnborg #ifndef __ASSEMBLY__ 41*a439fe51SSam Ravnborg /* Get the %psr register. */ 42*a439fe51SSam Ravnborg static inline unsigned int get_psr(void) 43*a439fe51SSam Ravnborg { 44*a439fe51SSam Ravnborg unsigned int psr; 45*a439fe51SSam Ravnborg __asm__ __volatile__( 46*a439fe51SSam Ravnborg "rd %%psr, %0\n\t" 47*a439fe51SSam Ravnborg "nop\n\t" 48*a439fe51SSam Ravnborg "nop\n\t" 49*a439fe51SSam Ravnborg "nop\n\t" 50*a439fe51SSam Ravnborg : "=r" (psr) 51*a439fe51SSam Ravnborg : /* no inputs */ 52*a439fe51SSam Ravnborg : "memory"); 53*a439fe51SSam Ravnborg 54*a439fe51SSam Ravnborg return psr; 55*a439fe51SSam Ravnborg } 56*a439fe51SSam Ravnborg 57*a439fe51SSam Ravnborg static inline void put_psr(unsigned int new_psr) 58*a439fe51SSam Ravnborg { 59*a439fe51SSam Ravnborg __asm__ __volatile__( 60*a439fe51SSam Ravnborg "wr %0, 0x0, %%psr\n\t" 61*a439fe51SSam Ravnborg "nop\n\t" 62*a439fe51SSam Ravnborg "nop\n\t" 63*a439fe51SSam Ravnborg "nop\n\t" 64*a439fe51SSam Ravnborg : /* no outputs */ 65*a439fe51SSam Ravnborg : "r" (new_psr) 66*a439fe51SSam Ravnborg : "memory", "cc"); 67*a439fe51SSam Ravnborg } 68*a439fe51SSam Ravnborg 69*a439fe51SSam Ravnborg /* Get the %fsr register. Be careful, make sure the floating point 70*a439fe51SSam Ravnborg * enable bit is set in the %psr when you execute this or you will 71*a439fe51SSam Ravnborg * incur a trap. 72*a439fe51SSam Ravnborg */ 73*a439fe51SSam Ravnborg 74*a439fe51SSam Ravnborg extern unsigned int fsr_storage; 75*a439fe51SSam Ravnborg 76*a439fe51SSam Ravnborg static inline unsigned int get_fsr(void) 77*a439fe51SSam Ravnborg { 78*a439fe51SSam Ravnborg unsigned int fsr = 0; 79*a439fe51SSam Ravnborg 80*a439fe51SSam Ravnborg __asm__ __volatile__( 81*a439fe51SSam Ravnborg "st %%fsr, %1\n\t" 82*a439fe51SSam Ravnborg "ld %1, %0\n\t" 83*a439fe51SSam Ravnborg : "=r" (fsr) 84*a439fe51SSam Ravnborg : "m" (fsr_storage)); 85*a439fe51SSam Ravnborg 86*a439fe51SSam Ravnborg return fsr; 87*a439fe51SSam Ravnborg } 88*a439fe51SSam Ravnborg 89*a439fe51SSam Ravnborg #endif /* !(__ASSEMBLY__) */ 90*a439fe51SSam Ravnborg 91*a439fe51SSam Ravnborg #endif /* (__KERNEL__) */ 92*a439fe51SSam Ravnborg 93*a439fe51SSam Ravnborg #endif /* !(__LINUX_SPARC_PSR_H) */ 94