1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Per core/cpu state 4 * 5 * Used to coordinate shared registers between HT threads or 6 * among events on a single PMU. 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/stddef.h> 12 #include <linux/types.h> 13 #include <linux/init.h> 14 #include <linux/slab.h> 15 #include <linux/export.h> 16 #include <linux/nmi.h> 17 #include <linux/kvm_host.h> 18 19 #include <asm/cpufeature.h> 20 #include <asm/hardirq.h> 21 #include <asm/intel-family.h> 22 #include <asm/intel_pt.h> 23 #include <asm/apic.h> 24 #include <asm/cpu_device_id.h> 25 26 #include "../perf_event.h" 27 28 /* 29 * Intel PerfMon, used on Core and later. 30 */ 31 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 32 { 33 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 34 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 35 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 36 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 37 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 38 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 39 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 40 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 41 }; 42 43 static struct event_constraint intel_core_event_constraints[] __read_mostly = 44 { 45 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 46 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 47 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 48 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 49 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 50 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 51 EVENT_CONSTRAINT_END 52 }; 53 54 static struct event_constraint intel_core2_event_constraints[] __read_mostly = 55 { 56 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 57 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 58 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 59 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 60 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 61 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 62 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 63 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 64 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 65 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 66 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 67 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 68 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 69 EVENT_CONSTRAINT_END 70 }; 71 72 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 73 { 74 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 75 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 76 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 77 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 78 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 79 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 80 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 81 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 82 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 83 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 84 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 85 EVENT_CONSTRAINT_END 86 }; 87 88 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 89 { 90 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 91 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 92 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 93 EVENT_EXTRA_END 94 }; 95 96 static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 97 { 98 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 99 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 100 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 101 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 102 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 103 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 104 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 105 EVENT_CONSTRAINT_END 106 }; 107 108 static struct event_constraint intel_snb_event_constraints[] __read_mostly = 109 { 110 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 111 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 112 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 113 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 114 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 115 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 116 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 117 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 118 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 119 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 120 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 121 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 122 123 /* 124 * When HT is off these events can only run on the bottom 4 counters 125 * When HT is on, they are impacted by the HT bug and require EXCL access 126 */ 127 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 128 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 129 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 130 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 131 132 EVENT_CONSTRAINT_END 133 }; 134 135 static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 136 { 137 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 138 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 139 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 140 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 141 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */ 142 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 143 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 144 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 145 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 146 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 147 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 148 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 149 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 150 151 /* 152 * When HT is off these events can only run on the bottom 4 counters 153 * When HT is on, they are impacted by the HT bug and require EXCL access 154 */ 155 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 156 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 157 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 158 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 159 160 EVENT_CONSTRAINT_END 161 }; 162 163 static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 164 { 165 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 166 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 167 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 168 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 169 EVENT_EXTRA_END 170 }; 171 172 static struct event_constraint intel_v1_event_constraints[] __read_mostly = 173 { 174 EVENT_CONSTRAINT_END 175 }; 176 177 static struct event_constraint intel_gen_event_constraints[] __read_mostly = 178 { 179 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 180 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 181 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 182 EVENT_CONSTRAINT_END 183 }; 184 185 static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly = 186 { 187 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 188 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 189 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 190 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 191 FIXED_EVENT_CONSTRAINT(0x0500, 4), 192 FIXED_EVENT_CONSTRAINT(0x0600, 5), 193 FIXED_EVENT_CONSTRAINT(0x0700, 6), 194 FIXED_EVENT_CONSTRAINT(0x0800, 7), 195 FIXED_EVENT_CONSTRAINT(0x0900, 8), 196 FIXED_EVENT_CONSTRAINT(0x0a00, 9), 197 FIXED_EVENT_CONSTRAINT(0x0b00, 10), 198 FIXED_EVENT_CONSTRAINT(0x0c00, 11), 199 FIXED_EVENT_CONSTRAINT(0x0d00, 12), 200 FIXED_EVENT_CONSTRAINT(0x0e00, 13), 201 FIXED_EVENT_CONSTRAINT(0x0f00, 14), 202 FIXED_EVENT_CONSTRAINT(0x1000, 15), 203 EVENT_CONSTRAINT_END 204 }; 205 206 static struct event_constraint intel_slm_event_constraints[] __read_mostly = 207 { 208 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 209 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 210 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 211 EVENT_CONSTRAINT_END 212 }; 213 214 static struct event_constraint intel_skl_event_constraints[] = { 215 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 216 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 217 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 218 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 219 220 /* 221 * when HT is off, these can only run on the bottom 4 counters 222 */ 223 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 224 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 225 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 226 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 227 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 228 229 EVENT_CONSTRAINT_END 230 }; 231 232 static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 233 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 234 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 235 EVENT_EXTRA_END 236 }; 237 238 static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 239 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 240 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 241 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 242 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 243 EVENT_EXTRA_END 244 }; 245 246 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 247 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 248 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 249 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 250 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 251 EVENT_EXTRA_END 252 }; 253 254 static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 255 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 256 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 257 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 258 /* 259 * Note the low 8 bits eventsel code is not a continuous field, containing 260 * some #GPing bits. These are masked out. 261 */ 262 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 263 EVENT_EXTRA_END 264 }; 265 266 static struct event_constraint intel_icl_event_constraints[] = { 267 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 268 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */ 269 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 270 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 271 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 272 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 273 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 274 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 275 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 276 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 277 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf), 278 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf), 279 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */ 280 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x56, 0xf), 281 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf), 282 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */ 283 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */ 284 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ 285 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */ 286 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf), 287 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf), 288 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf), 289 INTEL_EVENT_CONSTRAINT(0xef, 0xf), 290 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf), 291 EVENT_CONSTRAINT_END 292 }; 293 294 static struct extra_reg intel_icl_extra_regs[] __read_mostly = { 295 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0), 296 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1), 297 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 298 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 299 EVENT_EXTRA_END 300 }; 301 302 static struct extra_reg intel_spr_extra_regs[] __read_mostly = { 303 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 304 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 305 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 306 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 307 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), 308 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 309 EVENT_EXTRA_END 310 }; 311 312 static struct event_constraint intel_spr_event_constraints[] = { 313 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 314 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 315 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 316 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 317 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 318 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 319 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 320 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 321 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 322 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 323 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 324 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 325 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 326 327 INTEL_EVENT_CONSTRAINT(0x2e, 0xff), 328 INTEL_EVENT_CONSTRAINT(0x3c, 0xff), 329 /* 330 * Generally event codes < 0x90 are restricted to counters 0-3. 331 * The 0x2E and 0x3C are exception, which has no restriction. 332 */ 333 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf), 334 335 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf), 336 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), 337 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf), 338 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 339 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 340 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1), 341 INTEL_EVENT_CONSTRAINT(0xce, 0x1), 342 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), 343 /* 344 * Generally event codes >= 0x90 are likely to have no restrictions. 345 * The exception are defined as above. 346 */ 347 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff), 348 349 EVENT_CONSTRAINT_END 350 }; 351 352 353 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 354 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 355 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 356 357 static struct attribute *nhm_mem_events_attrs[] = { 358 EVENT_PTR(mem_ld_nhm), 359 NULL, 360 }; 361 362 /* 363 * topdown events for Intel Core CPUs. 364 * 365 * The events are all in slots, which is a free slot in a 4 wide 366 * pipeline. Some events are already reported in slots, for cycle 367 * events we multiply by the pipeline width (4). 368 * 369 * With Hyper Threading on, topdown metrics are either summed or averaged 370 * between the threads of a core: (count_t0 + count_t1). 371 * 372 * For the average case the metric is always scaled to pipeline width, 373 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 374 */ 375 376 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 377 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 378 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 379 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 380 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 381 "event=0xe,umask=0x1"); /* uops_issued.any */ 382 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 383 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 384 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 385 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 386 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 387 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 388 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 389 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 390 "4", "2"); 391 392 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4"); 393 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80"); 394 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81"); 395 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82"); 396 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83"); 397 EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84"); 398 EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85"); 399 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86"); 400 EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87"); 401 402 static struct attribute *snb_events_attrs[] = { 403 EVENT_PTR(td_slots_issued), 404 EVENT_PTR(td_slots_retired), 405 EVENT_PTR(td_fetch_bubbles), 406 EVENT_PTR(td_total_slots), 407 EVENT_PTR(td_total_slots_scale), 408 EVENT_PTR(td_recovery_bubbles), 409 EVENT_PTR(td_recovery_bubbles_scale), 410 NULL, 411 }; 412 413 static struct attribute *snb_mem_events_attrs[] = { 414 EVENT_PTR(mem_ld_snb), 415 EVENT_PTR(mem_st_snb), 416 NULL, 417 }; 418 419 static struct event_constraint intel_hsw_event_constraints[] = { 420 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 421 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 422 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 423 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 424 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 425 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 426 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 427 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 428 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 429 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 430 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 431 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 432 433 /* 434 * When HT is off these events can only run on the bottom 4 counters 435 * When HT is on, they are impacted by the HT bug and require EXCL access 436 */ 437 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 438 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 439 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 440 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 441 442 EVENT_CONSTRAINT_END 443 }; 444 445 static struct event_constraint intel_bdw_event_constraints[] = { 446 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 447 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 448 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 449 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 450 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 451 /* 452 * when HT is off, these can only run on the bottom 4 counters 453 */ 454 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 455 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 456 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 457 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 458 EVENT_CONSTRAINT_END 459 }; 460 461 static u64 intel_pmu_event_map(int hw_event) 462 { 463 return intel_perfmon_event_map[hw_event]; 464 } 465 466 static __initconst const u64 spr_hw_cache_event_ids 467 [PERF_COUNT_HW_CACHE_MAX] 468 [PERF_COUNT_HW_CACHE_OP_MAX] 469 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 470 { 471 [ C(L1D ) ] = { 472 [ C(OP_READ) ] = { 473 [ C(RESULT_ACCESS) ] = 0x81d0, 474 [ C(RESULT_MISS) ] = 0xe124, 475 }, 476 [ C(OP_WRITE) ] = { 477 [ C(RESULT_ACCESS) ] = 0x82d0, 478 }, 479 }, 480 [ C(L1I ) ] = { 481 [ C(OP_READ) ] = { 482 [ C(RESULT_MISS) ] = 0xe424, 483 }, 484 [ C(OP_WRITE) ] = { 485 [ C(RESULT_ACCESS) ] = -1, 486 [ C(RESULT_MISS) ] = -1, 487 }, 488 }, 489 [ C(LL ) ] = { 490 [ C(OP_READ) ] = { 491 [ C(RESULT_ACCESS) ] = 0x12a, 492 [ C(RESULT_MISS) ] = 0x12a, 493 }, 494 [ C(OP_WRITE) ] = { 495 [ C(RESULT_ACCESS) ] = 0x12a, 496 [ C(RESULT_MISS) ] = 0x12a, 497 }, 498 }, 499 [ C(DTLB) ] = { 500 [ C(OP_READ) ] = { 501 [ C(RESULT_ACCESS) ] = 0x81d0, 502 [ C(RESULT_MISS) ] = 0xe12, 503 }, 504 [ C(OP_WRITE) ] = { 505 [ C(RESULT_ACCESS) ] = 0x82d0, 506 [ C(RESULT_MISS) ] = 0xe13, 507 }, 508 }, 509 [ C(ITLB) ] = { 510 [ C(OP_READ) ] = { 511 [ C(RESULT_ACCESS) ] = -1, 512 [ C(RESULT_MISS) ] = 0xe11, 513 }, 514 [ C(OP_WRITE) ] = { 515 [ C(RESULT_ACCESS) ] = -1, 516 [ C(RESULT_MISS) ] = -1, 517 }, 518 [ C(OP_PREFETCH) ] = { 519 [ C(RESULT_ACCESS) ] = -1, 520 [ C(RESULT_MISS) ] = -1, 521 }, 522 }, 523 [ C(BPU ) ] = { 524 [ C(OP_READ) ] = { 525 [ C(RESULT_ACCESS) ] = 0x4c4, 526 [ C(RESULT_MISS) ] = 0x4c5, 527 }, 528 [ C(OP_WRITE) ] = { 529 [ C(RESULT_ACCESS) ] = -1, 530 [ C(RESULT_MISS) ] = -1, 531 }, 532 [ C(OP_PREFETCH) ] = { 533 [ C(RESULT_ACCESS) ] = -1, 534 [ C(RESULT_MISS) ] = -1, 535 }, 536 }, 537 [ C(NODE) ] = { 538 [ C(OP_READ) ] = { 539 [ C(RESULT_ACCESS) ] = 0x12a, 540 [ C(RESULT_MISS) ] = 0x12a, 541 }, 542 }, 543 }; 544 545 static __initconst const u64 spr_hw_cache_extra_regs 546 [PERF_COUNT_HW_CACHE_MAX] 547 [PERF_COUNT_HW_CACHE_OP_MAX] 548 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 549 { 550 [ C(LL ) ] = { 551 [ C(OP_READ) ] = { 552 [ C(RESULT_ACCESS) ] = 0x10001, 553 [ C(RESULT_MISS) ] = 0x3fbfc00001, 554 }, 555 [ C(OP_WRITE) ] = { 556 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002, 557 [ C(RESULT_MISS) ] = 0x3f3fc00002, 558 }, 559 }, 560 [ C(NODE) ] = { 561 [ C(OP_READ) ] = { 562 [ C(RESULT_ACCESS) ] = 0x10c000001, 563 [ C(RESULT_MISS) ] = 0x3fb3000001, 564 }, 565 }, 566 }; 567 568 /* 569 * Notes on the events: 570 * - data reads do not include code reads (comparable to earlier tables) 571 * - data counts include speculative execution (except L1 write, dtlb, bpu) 572 * - remote node access includes remote memory, remote cache, remote mmio. 573 * - prefetches are not included in the counts. 574 * - icache miss does not include decoded icache 575 */ 576 577 #define SKL_DEMAND_DATA_RD BIT_ULL(0) 578 #define SKL_DEMAND_RFO BIT_ULL(1) 579 #define SKL_ANY_RESPONSE BIT_ULL(16) 580 #define SKL_SUPPLIER_NONE BIT_ULL(17) 581 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 582 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 583 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 584 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 585 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 586 SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 587 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 588 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 589 #define SKL_SPL_HIT BIT_ULL(30) 590 #define SKL_SNOOP_NONE BIT_ULL(31) 591 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 592 #define SKL_SNOOP_MISS BIT_ULL(33) 593 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 594 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 595 #define SKL_SNOOP_HITM BIT_ULL(36) 596 #define SKL_SNOOP_NON_DRAM BIT_ULL(37) 597 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 598 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 599 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 600 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 601 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 602 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 603 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 604 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 605 SKL_SNOOP_HITM|SKL_SPL_HIT) 606 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO 607 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE 608 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 609 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 610 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 611 612 static __initconst const u64 skl_hw_cache_event_ids 613 [PERF_COUNT_HW_CACHE_MAX] 614 [PERF_COUNT_HW_CACHE_OP_MAX] 615 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 616 { 617 [ C(L1D ) ] = { 618 [ C(OP_READ) ] = { 619 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 620 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 621 }, 622 [ C(OP_WRITE) ] = { 623 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 624 [ C(RESULT_MISS) ] = 0x0, 625 }, 626 [ C(OP_PREFETCH) ] = { 627 [ C(RESULT_ACCESS) ] = 0x0, 628 [ C(RESULT_MISS) ] = 0x0, 629 }, 630 }, 631 [ C(L1I ) ] = { 632 [ C(OP_READ) ] = { 633 [ C(RESULT_ACCESS) ] = 0x0, 634 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 635 }, 636 [ C(OP_WRITE) ] = { 637 [ C(RESULT_ACCESS) ] = -1, 638 [ C(RESULT_MISS) ] = -1, 639 }, 640 [ C(OP_PREFETCH) ] = { 641 [ C(RESULT_ACCESS) ] = 0x0, 642 [ C(RESULT_MISS) ] = 0x0, 643 }, 644 }, 645 [ C(LL ) ] = { 646 [ C(OP_READ) ] = { 647 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 648 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 649 }, 650 [ C(OP_WRITE) ] = { 651 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 652 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 653 }, 654 [ C(OP_PREFETCH) ] = { 655 [ C(RESULT_ACCESS) ] = 0x0, 656 [ C(RESULT_MISS) ] = 0x0, 657 }, 658 }, 659 [ C(DTLB) ] = { 660 [ C(OP_READ) ] = { 661 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 662 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 663 }, 664 [ C(OP_WRITE) ] = { 665 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 666 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 667 }, 668 [ C(OP_PREFETCH) ] = { 669 [ C(RESULT_ACCESS) ] = 0x0, 670 [ C(RESULT_MISS) ] = 0x0, 671 }, 672 }, 673 [ C(ITLB) ] = { 674 [ C(OP_READ) ] = { 675 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 676 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 677 }, 678 [ C(OP_WRITE) ] = { 679 [ C(RESULT_ACCESS) ] = -1, 680 [ C(RESULT_MISS) ] = -1, 681 }, 682 [ C(OP_PREFETCH) ] = { 683 [ C(RESULT_ACCESS) ] = -1, 684 [ C(RESULT_MISS) ] = -1, 685 }, 686 }, 687 [ C(BPU ) ] = { 688 [ C(OP_READ) ] = { 689 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 690 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 691 }, 692 [ C(OP_WRITE) ] = { 693 [ C(RESULT_ACCESS) ] = -1, 694 [ C(RESULT_MISS) ] = -1, 695 }, 696 [ C(OP_PREFETCH) ] = { 697 [ C(RESULT_ACCESS) ] = -1, 698 [ C(RESULT_MISS) ] = -1, 699 }, 700 }, 701 [ C(NODE) ] = { 702 [ C(OP_READ) ] = { 703 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 704 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 705 }, 706 [ C(OP_WRITE) ] = { 707 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 708 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 709 }, 710 [ C(OP_PREFETCH) ] = { 711 [ C(RESULT_ACCESS) ] = 0x0, 712 [ C(RESULT_MISS) ] = 0x0, 713 }, 714 }, 715 }; 716 717 static __initconst const u64 skl_hw_cache_extra_regs 718 [PERF_COUNT_HW_CACHE_MAX] 719 [PERF_COUNT_HW_CACHE_OP_MAX] 720 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 721 { 722 [ C(LL ) ] = { 723 [ C(OP_READ) ] = { 724 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 725 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 726 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 727 SKL_L3_MISS|SKL_ANY_SNOOP| 728 SKL_SUPPLIER_NONE, 729 }, 730 [ C(OP_WRITE) ] = { 731 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 732 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 733 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 734 SKL_L3_MISS|SKL_ANY_SNOOP| 735 SKL_SUPPLIER_NONE, 736 }, 737 [ C(OP_PREFETCH) ] = { 738 [ C(RESULT_ACCESS) ] = 0x0, 739 [ C(RESULT_MISS) ] = 0x0, 740 }, 741 }, 742 [ C(NODE) ] = { 743 [ C(OP_READ) ] = { 744 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 745 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 746 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 747 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 748 }, 749 [ C(OP_WRITE) ] = { 750 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 751 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 752 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 753 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 754 }, 755 [ C(OP_PREFETCH) ] = { 756 [ C(RESULT_ACCESS) ] = 0x0, 757 [ C(RESULT_MISS) ] = 0x0, 758 }, 759 }, 760 }; 761 762 #define SNB_DMND_DATA_RD (1ULL << 0) 763 #define SNB_DMND_RFO (1ULL << 1) 764 #define SNB_DMND_IFETCH (1ULL << 2) 765 #define SNB_DMND_WB (1ULL << 3) 766 #define SNB_PF_DATA_RD (1ULL << 4) 767 #define SNB_PF_RFO (1ULL << 5) 768 #define SNB_PF_IFETCH (1ULL << 6) 769 #define SNB_LLC_DATA_RD (1ULL << 7) 770 #define SNB_LLC_RFO (1ULL << 8) 771 #define SNB_LLC_IFETCH (1ULL << 9) 772 #define SNB_BUS_LOCKS (1ULL << 10) 773 #define SNB_STRM_ST (1ULL << 11) 774 #define SNB_OTHER (1ULL << 15) 775 #define SNB_RESP_ANY (1ULL << 16) 776 #define SNB_NO_SUPP (1ULL << 17) 777 #define SNB_LLC_HITM (1ULL << 18) 778 #define SNB_LLC_HITE (1ULL << 19) 779 #define SNB_LLC_HITS (1ULL << 20) 780 #define SNB_LLC_HITF (1ULL << 21) 781 #define SNB_LOCAL (1ULL << 22) 782 #define SNB_REMOTE (0xffULL << 23) 783 #define SNB_SNP_NONE (1ULL << 31) 784 #define SNB_SNP_NOT_NEEDED (1ULL << 32) 785 #define SNB_SNP_MISS (1ULL << 33) 786 #define SNB_NO_FWD (1ULL << 34) 787 #define SNB_SNP_FWD (1ULL << 35) 788 #define SNB_HITM (1ULL << 36) 789 #define SNB_NON_DRAM (1ULL << 37) 790 791 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 792 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 793 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 794 795 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 796 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 797 SNB_HITM) 798 799 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 800 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 801 802 #define SNB_L3_ACCESS SNB_RESP_ANY 803 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 804 805 static __initconst const u64 snb_hw_cache_extra_regs 806 [PERF_COUNT_HW_CACHE_MAX] 807 [PERF_COUNT_HW_CACHE_OP_MAX] 808 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 809 { 810 [ C(LL ) ] = { 811 [ C(OP_READ) ] = { 812 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 813 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 814 }, 815 [ C(OP_WRITE) ] = { 816 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 817 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 818 }, 819 [ C(OP_PREFETCH) ] = { 820 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 821 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 822 }, 823 }, 824 [ C(NODE) ] = { 825 [ C(OP_READ) ] = { 826 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 827 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 828 }, 829 [ C(OP_WRITE) ] = { 830 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 831 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 832 }, 833 [ C(OP_PREFETCH) ] = { 834 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 835 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 836 }, 837 }, 838 }; 839 840 static __initconst const u64 snb_hw_cache_event_ids 841 [PERF_COUNT_HW_CACHE_MAX] 842 [PERF_COUNT_HW_CACHE_OP_MAX] 843 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 844 { 845 [ C(L1D) ] = { 846 [ C(OP_READ) ] = { 847 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 848 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 849 }, 850 [ C(OP_WRITE) ] = { 851 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 852 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 853 }, 854 [ C(OP_PREFETCH) ] = { 855 [ C(RESULT_ACCESS) ] = 0x0, 856 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 857 }, 858 }, 859 [ C(L1I ) ] = { 860 [ C(OP_READ) ] = { 861 [ C(RESULT_ACCESS) ] = 0x0, 862 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 863 }, 864 [ C(OP_WRITE) ] = { 865 [ C(RESULT_ACCESS) ] = -1, 866 [ C(RESULT_MISS) ] = -1, 867 }, 868 [ C(OP_PREFETCH) ] = { 869 [ C(RESULT_ACCESS) ] = 0x0, 870 [ C(RESULT_MISS) ] = 0x0, 871 }, 872 }, 873 [ C(LL ) ] = { 874 [ C(OP_READ) ] = { 875 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 876 [ C(RESULT_ACCESS) ] = 0x01b7, 877 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 878 [ C(RESULT_MISS) ] = 0x01b7, 879 }, 880 [ C(OP_WRITE) ] = { 881 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 882 [ C(RESULT_ACCESS) ] = 0x01b7, 883 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 884 [ C(RESULT_MISS) ] = 0x01b7, 885 }, 886 [ C(OP_PREFETCH) ] = { 887 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 888 [ C(RESULT_ACCESS) ] = 0x01b7, 889 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 890 [ C(RESULT_MISS) ] = 0x01b7, 891 }, 892 }, 893 [ C(DTLB) ] = { 894 [ C(OP_READ) ] = { 895 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 896 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 897 }, 898 [ C(OP_WRITE) ] = { 899 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 900 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 901 }, 902 [ C(OP_PREFETCH) ] = { 903 [ C(RESULT_ACCESS) ] = 0x0, 904 [ C(RESULT_MISS) ] = 0x0, 905 }, 906 }, 907 [ C(ITLB) ] = { 908 [ C(OP_READ) ] = { 909 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 910 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 911 }, 912 [ C(OP_WRITE) ] = { 913 [ C(RESULT_ACCESS) ] = -1, 914 [ C(RESULT_MISS) ] = -1, 915 }, 916 [ C(OP_PREFETCH) ] = { 917 [ C(RESULT_ACCESS) ] = -1, 918 [ C(RESULT_MISS) ] = -1, 919 }, 920 }, 921 [ C(BPU ) ] = { 922 [ C(OP_READ) ] = { 923 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 924 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 925 }, 926 [ C(OP_WRITE) ] = { 927 [ C(RESULT_ACCESS) ] = -1, 928 [ C(RESULT_MISS) ] = -1, 929 }, 930 [ C(OP_PREFETCH) ] = { 931 [ C(RESULT_ACCESS) ] = -1, 932 [ C(RESULT_MISS) ] = -1, 933 }, 934 }, 935 [ C(NODE) ] = { 936 [ C(OP_READ) ] = { 937 [ C(RESULT_ACCESS) ] = 0x01b7, 938 [ C(RESULT_MISS) ] = 0x01b7, 939 }, 940 [ C(OP_WRITE) ] = { 941 [ C(RESULT_ACCESS) ] = 0x01b7, 942 [ C(RESULT_MISS) ] = 0x01b7, 943 }, 944 [ C(OP_PREFETCH) ] = { 945 [ C(RESULT_ACCESS) ] = 0x01b7, 946 [ C(RESULT_MISS) ] = 0x01b7, 947 }, 948 }, 949 950 }; 951 952 /* 953 * Notes on the events: 954 * - data reads do not include code reads (comparable to earlier tables) 955 * - data counts include speculative execution (except L1 write, dtlb, bpu) 956 * - remote node access includes remote memory, remote cache, remote mmio. 957 * - prefetches are not included in the counts because they are not 958 * reliably counted. 959 */ 960 961 #define HSW_DEMAND_DATA_RD BIT_ULL(0) 962 #define HSW_DEMAND_RFO BIT_ULL(1) 963 #define HSW_ANY_RESPONSE BIT_ULL(16) 964 #define HSW_SUPPLIER_NONE BIT_ULL(17) 965 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 966 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 967 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 968 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 969 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 970 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 971 HSW_L3_MISS_REMOTE_HOP2P) 972 #define HSW_SNOOP_NONE BIT_ULL(31) 973 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 974 #define HSW_SNOOP_MISS BIT_ULL(33) 975 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 976 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 977 #define HSW_SNOOP_HITM BIT_ULL(36) 978 #define HSW_SNOOP_NON_DRAM BIT_ULL(37) 979 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 980 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 981 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 982 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 983 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 984 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 985 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO 986 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 987 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 988 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE 989 990 #define BDW_L3_MISS_LOCAL BIT(26) 991 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 992 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 993 HSW_L3_MISS_REMOTE_HOP2P) 994 995 996 static __initconst const u64 hsw_hw_cache_event_ids 997 [PERF_COUNT_HW_CACHE_MAX] 998 [PERF_COUNT_HW_CACHE_OP_MAX] 999 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1000 { 1001 [ C(L1D ) ] = { 1002 [ C(OP_READ) ] = { 1003 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1004 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 1005 }, 1006 [ C(OP_WRITE) ] = { 1007 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1008 [ C(RESULT_MISS) ] = 0x0, 1009 }, 1010 [ C(OP_PREFETCH) ] = { 1011 [ C(RESULT_ACCESS) ] = 0x0, 1012 [ C(RESULT_MISS) ] = 0x0, 1013 }, 1014 }, 1015 [ C(L1I ) ] = { 1016 [ C(OP_READ) ] = { 1017 [ C(RESULT_ACCESS) ] = 0x0, 1018 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 1019 }, 1020 [ C(OP_WRITE) ] = { 1021 [ C(RESULT_ACCESS) ] = -1, 1022 [ C(RESULT_MISS) ] = -1, 1023 }, 1024 [ C(OP_PREFETCH) ] = { 1025 [ C(RESULT_ACCESS) ] = 0x0, 1026 [ C(RESULT_MISS) ] = 0x0, 1027 }, 1028 }, 1029 [ C(LL ) ] = { 1030 [ C(OP_READ) ] = { 1031 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1032 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1033 }, 1034 [ C(OP_WRITE) ] = { 1035 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1036 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1037 }, 1038 [ C(OP_PREFETCH) ] = { 1039 [ C(RESULT_ACCESS) ] = 0x0, 1040 [ C(RESULT_MISS) ] = 0x0, 1041 }, 1042 }, 1043 [ C(DTLB) ] = { 1044 [ C(OP_READ) ] = { 1045 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1046 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 1047 }, 1048 [ C(OP_WRITE) ] = { 1049 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1050 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 1051 }, 1052 [ C(OP_PREFETCH) ] = { 1053 [ C(RESULT_ACCESS) ] = 0x0, 1054 [ C(RESULT_MISS) ] = 0x0, 1055 }, 1056 }, 1057 [ C(ITLB) ] = { 1058 [ C(OP_READ) ] = { 1059 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 1060 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 1061 }, 1062 [ C(OP_WRITE) ] = { 1063 [ C(RESULT_ACCESS) ] = -1, 1064 [ C(RESULT_MISS) ] = -1, 1065 }, 1066 [ C(OP_PREFETCH) ] = { 1067 [ C(RESULT_ACCESS) ] = -1, 1068 [ C(RESULT_MISS) ] = -1, 1069 }, 1070 }, 1071 [ C(BPU ) ] = { 1072 [ C(OP_READ) ] = { 1073 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1074 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1075 }, 1076 [ C(OP_WRITE) ] = { 1077 [ C(RESULT_ACCESS) ] = -1, 1078 [ C(RESULT_MISS) ] = -1, 1079 }, 1080 [ C(OP_PREFETCH) ] = { 1081 [ C(RESULT_ACCESS) ] = -1, 1082 [ C(RESULT_MISS) ] = -1, 1083 }, 1084 }, 1085 [ C(NODE) ] = { 1086 [ C(OP_READ) ] = { 1087 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1088 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1089 }, 1090 [ C(OP_WRITE) ] = { 1091 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1092 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1093 }, 1094 [ C(OP_PREFETCH) ] = { 1095 [ C(RESULT_ACCESS) ] = 0x0, 1096 [ C(RESULT_MISS) ] = 0x0, 1097 }, 1098 }, 1099 }; 1100 1101 static __initconst const u64 hsw_hw_cache_extra_regs 1102 [PERF_COUNT_HW_CACHE_MAX] 1103 [PERF_COUNT_HW_CACHE_OP_MAX] 1104 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1105 { 1106 [ C(LL ) ] = { 1107 [ C(OP_READ) ] = { 1108 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1109 HSW_LLC_ACCESS, 1110 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1111 HSW_L3_MISS|HSW_ANY_SNOOP, 1112 }, 1113 [ C(OP_WRITE) ] = { 1114 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1115 HSW_LLC_ACCESS, 1116 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1117 HSW_L3_MISS|HSW_ANY_SNOOP, 1118 }, 1119 [ C(OP_PREFETCH) ] = { 1120 [ C(RESULT_ACCESS) ] = 0x0, 1121 [ C(RESULT_MISS) ] = 0x0, 1122 }, 1123 }, 1124 [ C(NODE) ] = { 1125 [ C(OP_READ) ] = { 1126 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1127 HSW_L3_MISS_LOCAL_DRAM| 1128 HSW_SNOOP_DRAM, 1129 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1130 HSW_L3_MISS_REMOTE| 1131 HSW_SNOOP_DRAM, 1132 }, 1133 [ C(OP_WRITE) ] = { 1134 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1135 HSW_L3_MISS_LOCAL_DRAM| 1136 HSW_SNOOP_DRAM, 1137 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1138 HSW_L3_MISS_REMOTE| 1139 HSW_SNOOP_DRAM, 1140 }, 1141 [ C(OP_PREFETCH) ] = { 1142 [ C(RESULT_ACCESS) ] = 0x0, 1143 [ C(RESULT_MISS) ] = 0x0, 1144 }, 1145 }, 1146 }; 1147 1148 static __initconst const u64 westmere_hw_cache_event_ids 1149 [PERF_COUNT_HW_CACHE_MAX] 1150 [PERF_COUNT_HW_CACHE_OP_MAX] 1151 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1152 { 1153 [ C(L1D) ] = { 1154 [ C(OP_READ) ] = { 1155 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1156 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1157 }, 1158 [ C(OP_WRITE) ] = { 1159 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1160 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1161 }, 1162 [ C(OP_PREFETCH) ] = { 1163 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1164 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1165 }, 1166 }, 1167 [ C(L1I ) ] = { 1168 [ C(OP_READ) ] = { 1169 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1170 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1171 }, 1172 [ C(OP_WRITE) ] = { 1173 [ C(RESULT_ACCESS) ] = -1, 1174 [ C(RESULT_MISS) ] = -1, 1175 }, 1176 [ C(OP_PREFETCH) ] = { 1177 [ C(RESULT_ACCESS) ] = 0x0, 1178 [ C(RESULT_MISS) ] = 0x0, 1179 }, 1180 }, 1181 [ C(LL ) ] = { 1182 [ C(OP_READ) ] = { 1183 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1184 [ C(RESULT_ACCESS) ] = 0x01b7, 1185 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1186 [ C(RESULT_MISS) ] = 0x01b7, 1187 }, 1188 /* 1189 * Use RFO, not WRITEBACK, because a write miss would typically occur 1190 * on RFO. 1191 */ 1192 [ C(OP_WRITE) ] = { 1193 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1194 [ C(RESULT_ACCESS) ] = 0x01b7, 1195 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1196 [ C(RESULT_MISS) ] = 0x01b7, 1197 }, 1198 [ C(OP_PREFETCH) ] = { 1199 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1200 [ C(RESULT_ACCESS) ] = 0x01b7, 1201 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1202 [ C(RESULT_MISS) ] = 0x01b7, 1203 }, 1204 }, 1205 [ C(DTLB) ] = { 1206 [ C(OP_READ) ] = { 1207 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1208 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1209 }, 1210 [ C(OP_WRITE) ] = { 1211 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1212 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1213 }, 1214 [ C(OP_PREFETCH) ] = { 1215 [ C(RESULT_ACCESS) ] = 0x0, 1216 [ C(RESULT_MISS) ] = 0x0, 1217 }, 1218 }, 1219 [ C(ITLB) ] = { 1220 [ C(OP_READ) ] = { 1221 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1222 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 1223 }, 1224 [ C(OP_WRITE) ] = { 1225 [ C(RESULT_ACCESS) ] = -1, 1226 [ C(RESULT_MISS) ] = -1, 1227 }, 1228 [ C(OP_PREFETCH) ] = { 1229 [ C(RESULT_ACCESS) ] = -1, 1230 [ C(RESULT_MISS) ] = -1, 1231 }, 1232 }, 1233 [ C(BPU ) ] = { 1234 [ C(OP_READ) ] = { 1235 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1236 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1237 }, 1238 [ C(OP_WRITE) ] = { 1239 [ C(RESULT_ACCESS) ] = -1, 1240 [ C(RESULT_MISS) ] = -1, 1241 }, 1242 [ C(OP_PREFETCH) ] = { 1243 [ C(RESULT_ACCESS) ] = -1, 1244 [ C(RESULT_MISS) ] = -1, 1245 }, 1246 }, 1247 [ C(NODE) ] = { 1248 [ C(OP_READ) ] = { 1249 [ C(RESULT_ACCESS) ] = 0x01b7, 1250 [ C(RESULT_MISS) ] = 0x01b7, 1251 }, 1252 [ C(OP_WRITE) ] = { 1253 [ C(RESULT_ACCESS) ] = 0x01b7, 1254 [ C(RESULT_MISS) ] = 0x01b7, 1255 }, 1256 [ C(OP_PREFETCH) ] = { 1257 [ C(RESULT_ACCESS) ] = 0x01b7, 1258 [ C(RESULT_MISS) ] = 0x01b7, 1259 }, 1260 }, 1261 }; 1262 1263 /* 1264 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1265 * See IA32 SDM Vol 3B 30.6.1.3 1266 */ 1267 1268 #define NHM_DMND_DATA_RD (1 << 0) 1269 #define NHM_DMND_RFO (1 << 1) 1270 #define NHM_DMND_IFETCH (1 << 2) 1271 #define NHM_DMND_WB (1 << 3) 1272 #define NHM_PF_DATA_RD (1 << 4) 1273 #define NHM_PF_DATA_RFO (1 << 5) 1274 #define NHM_PF_IFETCH (1 << 6) 1275 #define NHM_OFFCORE_OTHER (1 << 7) 1276 #define NHM_UNCORE_HIT (1 << 8) 1277 #define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1278 #define NHM_OTHER_CORE_HITM (1 << 10) 1279 /* reserved */ 1280 #define NHM_REMOTE_CACHE_FWD (1 << 12) 1281 #define NHM_REMOTE_DRAM (1 << 13) 1282 #define NHM_LOCAL_DRAM (1 << 14) 1283 #define NHM_NON_DRAM (1 << 15) 1284 1285 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1286 #define NHM_REMOTE (NHM_REMOTE_DRAM) 1287 1288 #define NHM_DMND_READ (NHM_DMND_DATA_RD) 1289 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1290 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1291 1292 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1293 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1294 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1295 1296 static __initconst const u64 nehalem_hw_cache_extra_regs 1297 [PERF_COUNT_HW_CACHE_MAX] 1298 [PERF_COUNT_HW_CACHE_OP_MAX] 1299 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1300 { 1301 [ C(LL ) ] = { 1302 [ C(OP_READ) ] = { 1303 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1304 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1305 }, 1306 [ C(OP_WRITE) ] = { 1307 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1308 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1309 }, 1310 [ C(OP_PREFETCH) ] = { 1311 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1312 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1313 }, 1314 }, 1315 [ C(NODE) ] = { 1316 [ C(OP_READ) ] = { 1317 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1318 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1319 }, 1320 [ C(OP_WRITE) ] = { 1321 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1322 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1323 }, 1324 [ C(OP_PREFETCH) ] = { 1325 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1326 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1327 }, 1328 }, 1329 }; 1330 1331 static __initconst const u64 nehalem_hw_cache_event_ids 1332 [PERF_COUNT_HW_CACHE_MAX] 1333 [PERF_COUNT_HW_CACHE_OP_MAX] 1334 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1335 { 1336 [ C(L1D) ] = { 1337 [ C(OP_READ) ] = { 1338 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1339 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1340 }, 1341 [ C(OP_WRITE) ] = { 1342 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1343 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1344 }, 1345 [ C(OP_PREFETCH) ] = { 1346 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1347 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1348 }, 1349 }, 1350 [ C(L1I ) ] = { 1351 [ C(OP_READ) ] = { 1352 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1353 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1354 }, 1355 [ C(OP_WRITE) ] = { 1356 [ C(RESULT_ACCESS) ] = -1, 1357 [ C(RESULT_MISS) ] = -1, 1358 }, 1359 [ C(OP_PREFETCH) ] = { 1360 [ C(RESULT_ACCESS) ] = 0x0, 1361 [ C(RESULT_MISS) ] = 0x0, 1362 }, 1363 }, 1364 [ C(LL ) ] = { 1365 [ C(OP_READ) ] = { 1366 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1367 [ C(RESULT_ACCESS) ] = 0x01b7, 1368 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1369 [ C(RESULT_MISS) ] = 0x01b7, 1370 }, 1371 /* 1372 * Use RFO, not WRITEBACK, because a write miss would typically occur 1373 * on RFO. 1374 */ 1375 [ C(OP_WRITE) ] = { 1376 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1377 [ C(RESULT_ACCESS) ] = 0x01b7, 1378 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1379 [ C(RESULT_MISS) ] = 0x01b7, 1380 }, 1381 [ C(OP_PREFETCH) ] = { 1382 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1383 [ C(RESULT_ACCESS) ] = 0x01b7, 1384 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1385 [ C(RESULT_MISS) ] = 0x01b7, 1386 }, 1387 }, 1388 [ C(DTLB) ] = { 1389 [ C(OP_READ) ] = { 1390 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1391 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1392 }, 1393 [ C(OP_WRITE) ] = { 1394 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1395 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1396 }, 1397 [ C(OP_PREFETCH) ] = { 1398 [ C(RESULT_ACCESS) ] = 0x0, 1399 [ C(RESULT_MISS) ] = 0x0, 1400 }, 1401 }, 1402 [ C(ITLB) ] = { 1403 [ C(OP_READ) ] = { 1404 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1405 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1406 }, 1407 [ C(OP_WRITE) ] = { 1408 [ C(RESULT_ACCESS) ] = -1, 1409 [ C(RESULT_MISS) ] = -1, 1410 }, 1411 [ C(OP_PREFETCH) ] = { 1412 [ C(RESULT_ACCESS) ] = -1, 1413 [ C(RESULT_MISS) ] = -1, 1414 }, 1415 }, 1416 [ C(BPU ) ] = { 1417 [ C(OP_READ) ] = { 1418 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1419 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1420 }, 1421 [ C(OP_WRITE) ] = { 1422 [ C(RESULT_ACCESS) ] = -1, 1423 [ C(RESULT_MISS) ] = -1, 1424 }, 1425 [ C(OP_PREFETCH) ] = { 1426 [ C(RESULT_ACCESS) ] = -1, 1427 [ C(RESULT_MISS) ] = -1, 1428 }, 1429 }, 1430 [ C(NODE) ] = { 1431 [ C(OP_READ) ] = { 1432 [ C(RESULT_ACCESS) ] = 0x01b7, 1433 [ C(RESULT_MISS) ] = 0x01b7, 1434 }, 1435 [ C(OP_WRITE) ] = { 1436 [ C(RESULT_ACCESS) ] = 0x01b7, 1437 [ C(RESULT_MISS) ] = 0x01b7, 1438 }, 1439 [ C(OP_PREFETCH) ] = { 1440 [ C(RESULT_ACCESS) ] = 0x01b7, 1441 [ C(RESULT_MISS) ] = 0x01b7, 1442 }, 1443 }, 1444 }; 1445 1446 static __initconst const u64 core2_hw_cache_event_ids 1447 [PERF_COUNT_HW_CACHE_MAX] 1448 [PERF_COUNT_HW_CACHE_OP_MAX] 1449 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1450 { 1451 [ C(L1D) ] = { 1452 [ C(OP_READ) ] = { 1453 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1454 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1455 }, 1456 [ C(OP_WRITE) ] = { 1457 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1458 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1459 }, 1460 [ C(OP_PREFETCH) ] = { 1461 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1462 [ C(RESULT_MISS) ] = 0, 1463 }, 1464 }, 1465 [ C(L1I ) ] = { 1466 [ C(OP_READ) ] = { 1467 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1468 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1469 }, 1470 [ C(OP_WRITE) ] = { 1471 [ C(RESULT_ACCESS) ] = -1, 1472 [ C(RESULT_MISS) ] = -1, 1473 }, 1474 [ C(OP_PREFETCH) ] = { 1475 [ C(RESULT_ACCESS) ] = 0, 1476 [ C(RESULT_MISS) ] = 0, 1477 }, 1478 }, 1479 [ C(LL ) ] = { 1480 [ C(OP_READ) ] = { 1481 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1482 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1483 }, 1484 [ C(OP_WRITE) ] = { 1485 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1486 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1487 }, 1488 [ C(OP_PREFETCH) ] = { 1489 [ C(RESULT_ACCESS) ] = 0, 1490 [ C(RESULT_MISS) ] = 0, 1491 }, 1492 }, 1493 [ C(DTLB) ] = { 1494 [ C(OP_READ) ] = { 1495 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1496 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1497 }, 1498 [ C(OP_WRITE) ] = { 1499 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1500 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1501 }, 1502 [ C(OP_PREFETCH) ] = { 1503 [ C(RESULT_ACCESS) ] = 0, 1504 [ C(RESULT_MISS) ] = 0, 1505 }, 1506 }, 1507 [ C(ITLB) ] = { 1508 [ C(OP_READ) ] = { 1509 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1510 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1511 }, 1512 [ C(OP_WRITE) ] = { 1513 [ C(RESULT_ACCESS) ] = -1, 1514 [ C(RESULT_MISS) ] = -1, 1515 }, 1516 [ C(OP_PREFETCH) ] = { 1517 [ C(RESULT_ACCESS) ] = -1, 1518 [ C(RESULT_MISS) ] = -1, 1519 }, 1520 }, 1521 [ C(BPU ) ] = { 1522 [ C(OP_READ) ] = { 1523 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1524 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1525 }, 1526 [ C(OP_WRITE) ] = { 1527 [ C(RESULT_ACCESS) ] = -1, 1528 [ C(RESULT_MISS) ] = -1, 1529 }, 1530 [ C(OP_PREFETCH) ] = { 1531 [ C(RESULT_ACCESS) ] = -1, 1532 [ C(RESULT_MISS) ] = -1, 1533 }, 1534 }, 1535 }; 1536 1537 static __initconst const u64 atom_hw_cache_event_ids 1538 [PERF_COUNT_HW_CACHE_MAX] 1539 [PERF_COUNT_HW_CACHE_OP_MAX] 1540 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1541 { 1542 [ C(L1D) ] = { 1543 [ C(OP_READ) ] = { 1544 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 1545 [ C(RESULT_MISS) ] = 0, 1546 }, 1547 [ C(OP_WRITE) ] = { 1548 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 1549 [ C(RESULT_MISS) ] = 0, 1550 }, 1551 [ C(OP_PREFETCH) ] = { 1552 [ C(RESULT_ACCESS) ] = 0x0, 1553 [ C(RESULT_MISS) ] = 0, 1554 }, 1555 }, 1556 [ C(L1I ) ] = { 1557 [ C(OP_READ) ] = { 1558 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1559 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1560 }, 1561 [ C(OP_WRITE) ] = { 1562 [ C(RESULT_ACCESS) ] = -1, 1563 [ C(RESULT_MISS) ] = -1, 1564 }, 1565 [ C(OP_PREFETCH) ] = { 1566 [ C(RESULT_ACCESS) ] = 0, 1567 [ C(RESULT_MISS) ] = 0, 1568 }, 1569 }, 1570 [ C(LL ) ] = { 1571 [ C(OP_READ) ] = { 1572 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1573 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1574 }, 1575 [ C(OP_WRITE) ] = { 1576 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1577 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1578 }, 1579 [ C(OP_PREFETCH) ] = { 1580 [ C(RESULT_ACCESS) ] = 0, 1581 [ C(RESULT_MISS) ] = 0, 1582 }, 1583 }, 1584 [ C(DTLB) ] = { 1585 [ C(OP_READ) ] = { 1586 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 1587 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 1588 }, 1589 [ C(OP_WRITE) ] = { 1590 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 1591 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 1592 }, 1593 [ C(OP_PREFETCH) ] = { 1594 [ C(RESULT_ACCESS) ] = 0, 1595 [ C(RESULT_MISS) ] = 0, 1596 }, 1597 }, 1598 [ C(ITLB) ] = { 1599 [ C(OP_READ) ] = { 1600 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1601 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 1602 }, 1603 [ C(OP_WRITE) ] = { 1604 [ C(RESULT_ACCESS) ] = -1, 1605 [ C(RESULT_MISS) ] = -1, 1606 }, 1607 [ C(OP_PREFETCH) ] = { 1608 [ C(RESULT_ACCESS) ] = -1, 1609 [ C(RESULT_MISS) ] = -1, 1610 }, 1611 }, 1612 [ C(BPU ) ] = { 1613 [ C(OP_READ) ] = { 1614 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1615 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1616 }, 1617 [ C(OP_WRITE) ] = { 1618 [ C(RESULT_ACCESS) ] = -1, 1619 [ C(RESULT_MISS) ] = -1, 1620 }, 1621 [ C(OP_PREFETCH) ] = { 1622 [ C(RESULT_ACCESS) ] = -1, 1623 [ C(RESULT_MISS) ] = -1, 1624 }, 1625 }, 1626 }; 1627 1628 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 1629 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 1630 /* no_alloc_cycles.not_delivered */ 1631 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 1632 "event=0xca,umask=0x50"); 1633 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 1634 /* uops_retired.all */ 1635 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 1636 "event=0xc2,umask=0x10"); 1637 /* uops_retired.all */ 1638 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 1639 "event=0xc2,umask=0x10"); 1640 1641 static struct attribute *slm_events_attrs[] = { 1642 EVENT_PTR(td_total_slots_slm), 1643 EVENT_PTR(td_total_slots_scale_slm), 1644 EVENT_PTR(td_fetch_bubbles_slm), 1645 EVENT_PTR(td_fetch_bubbles_scale_slm), 1646 EVENT_PTR(td_slots_issued_slm), 1647 EVENT_PTR(td_slots_retired_slm), 1648 NULL 1649 }; 1650 1651 static struct extra_reg intel_slm_extra_regs[] __read_mostly = 1652 { 1653 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1654 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 1655 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 1656 EVENT_EXTRA_END 1657 }; 1658 1659 #define SLM_DMND_READ SNB_DMND_DATA_RD 1660 #define SLM_DMND_WRITE SNB_DMND_RFO 1661 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1662 1663 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 1664 #define SLM_LLC_ACCESS SNB_RESP_ANY 1665 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 1666 1667 static __initconst const u64 slm_hw_cache_extra_regs 1668 [PERF_COUNT_HW_CACHE_MAX] 1669 [PERF_COUNT_HW_CACHE_OP_MAX] 1670 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1671 { 1672 [ C(LL ) ] = { 1673 [ C(OP_READ) ] = { 1674 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 1675 [ C(RESULT_MISS) ] = 0, 1676 }, 1677 [ C(OP_WRITE) ] = { 1678 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 1679 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 1680 }, 1681 [ C(OP_PREFETCH) ] = { 1682 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 1683 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 1684 }, 1685 }, 1686 }; 1687 1688 static __initconst const u64 slm_hw_cache_event_ids 1689 [PERF_COUNT_HW_CACHE_MAX] 1690 [PERF_COUNT_HW_CACHE_OP_MAX] 1691 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1692 { 1693 [ C(L1D) ] = { 1694 [ C(OP_READ) ] = { 1695 [ C(RESULT_ACCESS) ] = 0, 1696 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 1697 }, 1698 [ C(OP_WRITE) ] = { 1699 [ C(RESULT_ACCESS) ] = 0, 1700 [ C(RESULT_MISS) ] = 0, 1701 }, 1702 [ C(OP_PREFETCH) ] = { 1703 [ C(RESULT_ACCESS) ] = 0, 1704 [ C(RESULT_MISS) ] = 0, 1705 }, 1706 }, 1707 [ C(L1I ) ] = { 1708 [ C(OP_READ) ] = { 1709 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 1710 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 1711 }, 1712 [ C(OP_WRITE) ] = { 1713 [ C(RESULT_ACCESS) ] = -1, 1714 [ C(RESULT_MISS) ] = -1, 1715 }, 1716 [ C(OP_PREFETCH) ] = { 1717 [ C(RESULT_ACCESS) ] = 0, 1718 [ C(RESULT_MISS) ] = 0, 1719 }, 1720 }, 1721 [ C(LL ) ] = { 1722 [ C(OP_READ) ] = { 1723 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1724 [ C(RESULT_ACCESS) ] = 0x01b7, 1725 [ C(RESULT_MISS) ] = 0, 1726 }, 1727 [ C(OP_WRITE) ] = { 1728 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1729 [ C(RESULT_ACCESS) ] = 0x01b7, 1730 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1731 [ C(RESULT_MISS) ] = 0x01b7, 1732 }, 1733 [ C(OP_PREFETCH) ] = { 1734 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1735 [ C(RESULT_ACCESS) ] = 0x01b7, 1736 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1737 [ C(RESULT_MISS) ] = 0x01b7, 1738 }, 1739 }, 1740 [ C(DTLB) ] = { 1741 [ C(OP_READ) ] = { 1742 [ C(RESULT_ACCESS) ] = 0, 1743 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 1744 }, 1745 [ C(OP_WRITE) ] = { 1746 [ C(RESULT_ACCESS) ] = 0, 1747 [ C(RESULT_MISS) ] = 0, 1748 }, 1749 [ C(OP_PREFETCH) ] = { 1750 [ C(RESULT_ACCESS) ] = 0, 1751 [ C(RESULT_MISS) ] = 0, 1752 }, 1753 }, 1754 [ C(ITLB) ] = { 1755 [ C(OP_READ) ] = { 1756 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1757 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 1758 }, 1759 [ C(OP_WRITE) ] = { 1760 [ C(RESULT_ACCESS) ] = -1, 1761 [ C(RESULT_MISS) ] = -1, 1762 }, 1763 [ C(OP_PREFETCH) ] = { 1764 [ C(RESULT_ACCESS) ] = -1, 1765 [ C(RESULT_MISS) ] = -1, 1766 }, 1767 }, 1768 [ C(BPU ) ] = { 1769 [ C(OP_READ) ] = { 1770 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1771 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1772 }, 1773 [ C(OP_WRITE) ] = { 1774 [ C(RESULT_ACCESS) ] = -1, 1775 [ C(RESULT_MISS) ] = -1, 1776 }, 1777 [ C(OP_PREFETCH) ] = { 1778 [ C(RESULT_ACCESS) ] = -1, 1779 [ C(RESULT_MISS) ] = -1, 1780 }, 1781 }, 1782 }; 1783 1784 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 1785 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 1786 /* UOPS_NOT_DELIVERED.ANY */ 1787 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 1788 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 1789 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 1790 /* UOPS_RETIRED.ANY */ 1791 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 1792 /* UOPS_ISSUED.ANY */ 1793 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 1794 1795 static struct attribute *glm_events_attrs[] = { 1796 EVENT_PTR(td_total_slots_glm), 1797 EVENT_PTR(td_total_slots_scale_glm), 1798 EVENT_PTR(td_fetch_bubbles_glm), 1799 EVENT_PTR(td_recovery_bubbles_glm), 1800 EVENT_PTR(td_slots_issued_glm), 1801 EVENT_PTR(td_slots_retired_glm), 1802 NULL 1803 }; 1804 1805 static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 1806 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1807 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 1808 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 1809 EVENT_EXTRA_END 1810 }; 1811 1812 #define GLM_DEMAND_DATA_RD BIT_ULL(0) 1813 #define GLM_DEMAND_RFO BIT_ULL(1) 1814 #define GLM_ANY_RESPONSE BIT_ULL(16) 1815 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 1816 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 1817 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO 1818 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1819 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE 1820 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 1821 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 1822 1823 static __initconst const u64 glm_hw_cache_event_ids 1824 [PERF_COUNT_HW_CACHE_MAX] 1825 [PERF_COUNT_HW_CACHE_OP_MAX] 1826 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1827 [C(L1D)] = { 1828 [C(OP_READ)] = { 1829 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1830 [C(RESULT_MISS)] = 0x0, 1831 }, 1832 [C(OP_WRITE)] = { 1833 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1834 [C(RESULT_MISS)] = 0x0, 1835 }, 1836 [C(OP_PREFETCH)] = { 1837 [C(RESULT_ACCESS)] = 0x0, 1838 [C(RESULT_MISS)] = 0x0, 1839 }, 1840 }, 1841 [C(L1I)] = { 1842 [C(OP_READ)] = { 1843 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1844 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1845 }, 1846 [C(OP_WRITE)] = { 1847 [C(RESULT_ACCESS)] = -1, 1848 [C(RESULT_MISS)] = -1, 1849 }, 1850 [C(OP_PREFETCH)] = { 1851 [C(RESULT_ACCESS)] = 0x0, 1852 [C(RESULT_MISS)] = 0x0, 1853 }, 1854 }, 1855 [C(LL)] = { 1856 [C(OP_READ)] = { 1857 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1858 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1859 }, 1860 [C(OP_WRITE)] = { 1861 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1862 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1863 }, 1864 [C(OP_PREFETCH)] = { 1865 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1866 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1867 }, 1868 }, 1869 [C(DTLB)] = { 1870 [C(OP_READ)] = { 1871 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1872 [C(RESULT_MISS)] = 0x0, 1873 }, 1874 [C(OP_WRITE)] = { 1875 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1876 [C(RESULT_MISS)] = 0x0, 1877 }, 1878 [C(OP_PREFETCH)] = { 1879 [C(RESULT_ACCESS)] = 0x0, 1880 [C(RESULT_MISS)] = 0x0, 1881 }, 1882 }, 1883 [C(ITLB)] = { 1884 [C(OP_READ)] = { 1885 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1886 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1887 }, 1888 [C(OP_WRITE)] = { 1889 [C(RESULT_ACCESS)] = -1, 1890 [C(RESULT_MISS)] = -1, 1891 }, 1892 [C(OP_PREFETCH)] = { 1893 [C(RESULT_ACCESS)] = -1, 1894 [C(RESULT_MISS)] = -1, 1895 }, 1896 }, 1897 [C(BPU)] = { 1898 [C(OP_READ)] = { 1899 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1900 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1901 }, 1902 [C(OP_WRITE)] = { 1903 [C(RESULT_ACCESS)] = -1, 1904 [C(RESULT_MISS)] = -1, 1905 }, 1906 [C(OP_PREFETCH)] = { 1907 [C(RESULT_ACCESS)] = -1, 1908 [C(RESULT_MISS)] = -1, 1909 }, 1910 }, 1911 }; 1912 1913 static __initconst const u64 glm_hw_cache_extra_regs 1914 [PERF_COUNT_HW_CACHE_MAX] 1915 [PERF_COUNT_HW_CACHE_OP_MAX] 1916 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1917 [C(LL)] = { 1918 [C(OP_READ)] = { 1919 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 1920 GLM_LLC_ACCESS, 1921 [C(RESULT_MISS)] = GLM_DEMAND_READ| 1922 GLM_LLC_MISS, 1923 }, 1924 [C(OP_WRITE)] = { 1925 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 1926 GLM_LLC_ACCESS, 1927 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 1928 GLM_LLC_MISS, 1929 }, 1930 [C(OP_PREFETCH)] = { 1931 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 1932 GLM_LLC_ACCESS, 1933 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 1934 GLM_LLC_MISS, 1935 }, 1936 }, 1937 }; 1938 1939 static __initconst const u64 glp_hw_cache_event_ids 1940 [PERF_COUNT_HW_CACHE_MAX] 1941 [PERF_COUNT_HW_CACHE_OP_MAX] 1942 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1943 [C(L1D)] = { 1944 [C(OP_READ)] = { 1945 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1946 [C(RESULT_MISS)] = 0x0, 1947 }, 1948 [C(OP_WRITE)] = { 1949 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1950 [C(RESULT_MISS)] = 0x0, 1951 }, 1952 [C(OP_PREFETCH)] = { 1953 [C(RESULT_ACCESS)] = 0x0, 1954 [C(RESULT_MISS)] = 0x0, 1955 }, 1956 }, 1957 [C(L1I)] = { 1958 [C(OP_READ)] = { 1959 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1960 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1961 }, 1962 [C(OP_WRITE)] = { 1963 [C(RESULT_ACCESS)] = -1, 1964 [C(RESULT_MISS)] = -1, 1965 }, 1966 [C(OP_PREFETCH)] = { 1967 [C(RESULT_ACCESS)] = 0x0, 1968 [C(RESULT_MISS)] = 0x0, 1969 }, 1970 }, 1971 [C(LL)] = { 1972 [C(OP_READ)] = { 1973 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1974 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1975 }, 1976 [C(OP_WRITE)] = { 1977 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1978 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1979 }, 1980 [C(OP_PREFETCH)] = { 1981 [C(RESULT_ACCESS)] = 0x0, 1982 [C(RESULT_MISS)] = 0x0, 1983 }, 1984 }, 1985 [C(DTLB)] = { 1986 [C(OP_READ)] = { 1987 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1988 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 1989 }, 1990 [C(OP_WRITE)] = { 1991 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1992 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 1993 }, 1994 [C(OP_PREFETCH)] = { 1995 [C(RESULT_ACCESS)] = 0x0, 1996 [C(RESULT_MISS)] = 0x0, 1997 }, 1998 }, 1999 [C(ITLB)] = { 2000 [C(OP_READ)] = { 2001 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 2002 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 2003 }, 2004 [C(OP_WRITE)] = { 2005 [C(RESULT_ACCESS)] = -1, 2006 [C(RESULT_MISS)] = -1, 2007 }, 2008 [C(OP_PREFETCH)] = { 2009 [C(RESULT_ACCESS)] = -1, 2010 [C(RESULT_MISS)] = -1, 2011 }, 2012 }, 2013 [C(BPU)] = { 2014 [C(OP_READ)] = { 2015 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 2016 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 2017 }, 2018 [C(OP_WRITE)] = { 2019 [C(RESULT_ACCESS)] = -1, 2020 [C(RESULT_MISS)] = -1, 2021 }, 2022 [C(OP_PREFETCH)] = { 2023 [C(RESULT_ACCESS)] = -1, 2024 [C(RESULT_MISS)] = -1, 2025 }, 2026 }, 2027 }; 2028 2029 static __initconst const u64 glp_hw_cache_extra_regs 2030 [PERF_COUNT_HW_CACHE_MAX] 2031 [PERF_COUNT_HW_CACHE_OP_MAX] 2032 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2033 [C(LL)] = { 2034 [C(OP_READ)] = { 2035 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 2036 GLM_LLC_ACCESS, 2037 [C(RESULT_MISS)] = GLM_DEMAND_READ| 2038 GLM_LLC_MISS, 2039 }, 2040 [C(OP_WRITE)] = { 2041 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 2042 GLM_LLC_ACCESS, 2043 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 2044 GLM_LLC_MISS, 2045 }, 2046 [C(OP_PREFETCH)] = { 2047 [C(RESULT_ACCESS)] = 0x0, 2048 [C(RESULT_MISS)] = 0x0, 2049 }, 2050 }, 2051 }; 2052 2053 #define TNT_LOCAL_DRAM BIT_ULL(26) 2054 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD 2055 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO 2056 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE 2057 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \ 2058 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM) 2059 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM) 2060 2061 static __initconst const u64 tnt_hw_cache_extra_regs 2062 [PERF_COUNT_HW_CACHE_MAX] 2063 [PERF_COUNT_HW_CACHE_OP_MAX] 2064 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2065 [C(LL)] = { 2066 [C(OP_READ)] = { 2067 [C(RESULT_ACCESS)] = TNT_DEMAND_READ| 2068 TNT_LLC_ACCESS, 2069 [C(RESULT_MISS)] = TNT_DEMAND_READ| 2070 TNT_LLC_MISS, 2071 }, 2072 [C(OP_WRITE)] = { 2073 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| 2074 TNT_LLC_ACCESS, 2075 [C(RESULT_MISS)] = TNT_DEMAND_WRITE| 2076 TNT_LLC_MISS, 2077 }, 2078 [C(OP_PREFETCH)] = { 2079 [C(RESULT_ACCESS)] = 0x0, 2080 [C(RESULT_MISS)] = 0x0, 2081 }, 2082 }, 2083 }; 2084 2085 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0"); 2086 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0"); 2087 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6"); 2088 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0"); 2089 2090 static struct attribute *tnt_events_attrs[] = { 2091 EVENT_PTR(td_fe_bound_tnt), 2092 EVENT_PTR(td_retiring_tnt), 2093 EVENT_PTR(td_bad_spec_tnt), 2094 EVENT_PTR(td_be_bound_tnt), 2095 NULL, 2096 }; 2097 2098 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { 2099 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2100 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0), 2101 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1), 2102 EVENT_EXTRA_END 2103 }; 2104 2105 EVENT_ATTR_STR(mem-loads, mem_ld_grt, "event=0xd0,umask=0x5,ldlat=3"); 2106 EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6"); 2107 2108 static struct attribute *grt_mem_attrs[] = { 2109 EVENT_PTR(mem_ld_grt), 2110 EVENT_PTR(mem_st_grt), 2111 NULL 2112 }; 2113 2114 static struct extra_reg intel_grt_extra_regs[] __read_mostly = { 2115 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2116 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 2117 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 2118 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2119 EVENT_EXTRA_END 2120 }; 2121 2122 static struct extra_reg intel_cmt_extra_regs[] __read_mostly = { 2123 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2124 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0), 2125 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff3ffffffffffull, RSP_1), 2126 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2127 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0), 2128 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1), 2129 EVENT_EXTRA_END 2130 }; 2131 2132 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 2133 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 2134 #define KNL_MCDRAM_LOCAL BIT_ULL(21) 2135 #define KNL_MCDRAM_FAR BIT_ULL(22) 2136 #define KNL_DDR_LOCAL BIT_ULL(23) 2137 #define KNL_DDR_FAR BIT_ULL(24) 2138 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 2139 KNL_DDR_LOCAL | KNL_DDR_FAR) 2140 #define KNL_L2_READ SLM_DMND_READ 2141 #define KNL_L2_WRITE SLM_DMND_WRITE 2142 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH 2143 #define KNL_L2_ACCESS SLM_LLC_ACCESS 2144 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 2145 KNL_DRAM_ANY | SNB_SNP_ANY | \ 2146 SNB_NON_DRAM) 2147 2148 static __initconst const u64 knl_hw_cache_extra_regs 2149 [PERF_COUNT_HW_CACHE_MAX] 2150 [PERF_COUNT_HW_CACHE_OP_MAX] 2151 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2152 [C(LL)] = { 2153 [C(OP_READ)] = { 2154 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 2155 [C(RESULT_MISS)] = 0, 2156 }, 2157 [C(OP_WRITE)] = { 2158 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 2159 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 2160 }, 2161 [C(OP_PREFETCH)] = { 2162 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 2163 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 2164 }, 2165 }, 2166 }; 2167 2168 /* 2169 * Used from PMIs where the LBRs are already disabled. 2170 * 2171 * This function could be called consecutively. It is required to remain in 2172 * disabled state if called consecutively. 2173 * 2174 * During consecutive calls, the same disable value will be written to related 2175 * registers, so the PMU state remains unchanged. 2176 * 2177 * intel_bts events don't coexist with intel PMU's BTS events because of 2178 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 2179 * disabled around intel PMU's event batching etc, only inside the PMI handler. 2180 * 2181 * Avoid PEBS_ENABLE MSR access in PMIs. 2182 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore. 2183 * It doesn't matter if the PEBS is enabled or not. 2184 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to 2185 * access PEBS_ENABLE MSR in disable_all()/enable_all(). 2186 * However, there are some cases which may change PEBS status, e.g. PMI 2187 * throttle. The PEBS_ENABLE should be updated where the status changes. 2188 */ 2189 static __always_inline void __intel_pmu_disable_all(bool bts) 2190 { 2191 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2192 2193 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2194 2195 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 2196 intel_pmu_disable_bts(); 2197 } 2198 2199 static __always_inline void intel_pmu_disable_all(void) 2200 { 2201 __intel_pmu_disable_all(true); 2202 intel_pmu_pebs_disable_all(); 2203 intel_pmu_lbr_disable_all(); 2204 } 2205 2206 static void __intel_pmu_enable_all(int added, bool pmi) 2207 { 2208 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2209 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 2210 2211 intel_pmu_lbr_enable_all(pmi); 2212 2213 if (cpuc->fixed_ctrl_val != cpuc->active_fixed_ctrl_val) { 2214 wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, cpuc->fixed_ctrl_val); 2215 cpuc->active_fixed_ctrl_val = cpuc->fixed_ctrl_val; 2216 } 2217 2218 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 2219 intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 2220 2221 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 2222 struct perf_event *event = 2223 cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 2224 2225 if (WARN_ON_ONCE(!event)) 2226 return; 2227 2228 intel_pmu_enable_bts(event->hw.config); 2229 } 2230 } 2231 2232 static void intel_pmu_enable_all(int added) 2233 { 2234 intel_pmu_pebs_enable_all(); 2235 __intel_pmu_enable_all(added, false); 2236 } 2237 2238 static noinline int 2239 __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, 2240 unsigned int cnt, unsigned long flags) 2241 { 2242 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2243 2244 intel_pmu_lbr_read(); 2245 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr); 2246 2247 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt); 2248 intel_pmu_enable_all(0); 2249 local_irq_restore(flags); 2250 return cnt; 2251 } 2252 2253 static int 2254 intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2255 { 2256 unsigned long flags; 2257 2258 /* must not have branches... */ 2259 local_irq_save(flags); 2260 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2261 __intel_pmu_lbr_disable(); 2262 /* ... until here */ 2263 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2264 } 2265 2266 static int 2267 intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2268 { 2269 unsigned long flags; 2270 2271 /* must not have branches... */ 2272 local_irq_save(flags); 2273 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2274 __intel_pmu_arch_lbr_disable(); 2275 /* ... until here */ 2276 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2277 } 2278 2279 /* 2280 * Workaround for: 2281 * Intel Errata AAK100 (model 26) 2282 * Intel Errata AAP53 (model 30) 2283 * Intel Errata BD53 (model 44) 2284 * 2285 * The official story: 2286 * These chips need to be 'reset' when adding counters by programming the 2287 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 2288 * in sequence on the same PMC or on different PMCs. 2289 * 2290 * In practice it appears some of these events do in fact count, and 2291 * we need to program all 4 events. 2292 */ 2293 static void intel_pmu_nhm_workaround(void) 2294 { 2295 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2296 static const unsigned long nhm_magic[4] = { 2297 0x4300B5, 2298 0x4300D2, 2299 0x4300B1, 2300 0x4300B1 2301 }; 2302 struct perf_event *event; 2303 int i; 2304 2305 /* 2306 * The Errata requires below steps: 2307 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 2308 * 2) Configure 4 PERFEVTSELx with the magic events and clear 2309 * the corresponding PMCx; 2310 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 2311 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 2312 * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 2313 */ 2314 2315 /* 2316 * The real steps we choose are a little different from above. 2317 * A) To reduce MSR operations, we don't run step 1) as they 2318 * are already cleared before this function is called; 2319 * B) Call x86_perf_event_update to save PMCx before configuring 2320 * PERFEVTSELx with magic number; 2321 * C) With step 5), we do clear only when the PERFEVTSELx is 2322 * not used currently. 2323 * D) Call x86_perf_event_set_period to restore PMCx; 2324 */ 2325 2326 /* We always operate 4 pairs of PERF Counters */ 2327 for (i = 0; i < 4; i++) { 2328 event = cpuc->events[i]; 2329 if (event) 2330 static_call(x86_pmu_update)(event); 2331 } 2332 2333 for (i = 0; i < 4; i++) { 2334 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 2335 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 2336 } 2337 2338 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 2339 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 2340 2341 for (i = 0; i < 4; i++) { 2342 event = cpuc->events[i]; 2343 2344 if (event) { 2345 static_call(x86_pmu_set_period)(event); 2346 __x86_pmu_enable_event(&event->hw, 2347 ARCH_PERFMON_EVENTSEL_ENABLE); 2348 } else 2349 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 2350 } 2351 } 2352 2353 static void intel_pmu_nhm_enable_all(int added) 2354 { 2355 if (added) 2356 intel_pmu_nhm_workaround(); 2357 intel_pmu_enable_all(added); 2358 } 2359 2360 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on) 2361 { 2362 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0; 2363 2364 if (cpuc->tfa_shadow != val) { 2365 cpuc->tfa_shadow = val; 2366 wrmsrl(MSR_TSX_FORCE_ABORT, val); 2367 } 2368 } 2369 2370 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2371 { 2372 /* 2373 * We're going to use PMC3, make sure TFA is set before we touch it. 2374 */ 2375 if (cntr == 3) 2376 intel_set_tfa(cpuc, true); 2377 } 2378 2379 static void intel_tfa_pmu_enable_all(int added) 2380 { 2381 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2382 2383 /* 2384 * If we find PMC3 is no longer used when we enable the PMU, we can 2385 * clear TFA. 2386 */ 2387 if (!test_bit(3, cpuc->active_mask)) 2388 intel_set_tfa(cpuc, false); 2389 2390 intel_pmu_enable_all(added); 2391 } 2392 2393 static inline u64 intel_pmu_get_status(void) 2394 { 2395 u64 status; 2396 2397 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 2398 2399 return status; 2400 } 2401 2402 static inline void intel_pmu_ack_status(u64 ack) 2403 { 2404 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2405 } 2406 2407 static inline bool event_is_checkpointed(struct perf_event *event) 2408 { 2409 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 2410 } 2411 2412 static inline void intel_set_masks(struct perf_event *event, int idx) 2413 { 2414 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2415 2416 if (event->attr.exclude_host) 2417 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2418 if (event->attr.exclude_guest) 2419 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2420 if (event_is_checkpointed(event)) 2421 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2422 } 2423 2424 static inline void intel_clear_masks(struct perf_event *event, int idx) 2425 { 2426 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2427 2428 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2429 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2430 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2431 } 2432 2433 static void intel_pmu_disable_fixed(struct perf_event *event) 2434 { 2435 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2436 struct hw_perf_event *hwc = &event->hw; 2437 int idx = hwc->idx; 2438 u64 mask; 2439 2440 if (is_topdown_idx(idx)) { 2441 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2442 2443 /* 2444 * When there are other active TopDown events, 2445 * don't disable the fixed counter 3. 2446 */ 2447 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2448 return; 2449 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2450 } 2451 2452 intel_clear_masks(event, idx); 2453 2454 mask = 0xfULL << ((idx - INTEL_PMC_IDX_FIXED) * 4); 2455 cpuc->fixed_ctrl_val &= ~mask; 2456 } 2457 2458 static void intel_pmu_disable_event(struct perf_event *event) 2459 { 2460 struct hw_perf_event *hwc = &event->hw; 2461 int idx = hwc->idx; 2462 2463 switch (idx) { 2464 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2465 intel_clear_masks(event, idx); 2466 x86_pmu_disable_event(event); 2467 break; 2468 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2469 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2470 intel_pmu_disable_fixed(event); 2471 break; 2472 case INTEL_PMC_IDX_FIXED_BTS: 2473 intel_pmu_disable_bts(); 2474 intel_pmu_drain_bts_buffer(); 2475 return; 2476 case INTEL_PMC_IDX_FIXED_VLBR: 2477 intel_clear_masks(event, idx); 2478 break; 2479 default: 2480 intel_clear_masks(event, idx); 2481 pr_warn("Failed to disable the event with invalid index %d\n", 2482 idx); 2483 return; 2484 } 2485 2486 /* 2487 * Needs to be called after x86_pmu_disable_event, 2488 * so we don't trigger the event without PEBS bit set. 2489 */ 2490 if (unlikely(event->attr.precise_ip)) 2491 intel_pmu_pebs_disable(event); 2492 } 2493 2494 static void intel_pmu_assign_event(struct perf_event *event, int idx) 2495 { 2496 if (is_pebs_pt(event)) 2497 perf_report_aux_output_id(event, idx); 2498 } 2499 2500 static void intel_pmu_del_event(struct perf_event *event) 2501 { 2502 if (needs_branch_stack(event)) 2503 intel_pmu_lbr_del(event); 2504 if (event->attr.precise_ip) 2505 intel_pmu_pebs_del(event); 2506 } 2507 2508 static int icl_set_topdown_event_period(struct perf_event *event) 2509 { 2510 struct hw_perf_event *hwc = &event->hw; 2511 s64 left = local64_read(&hwc->period_left); 2512 2513 /* 2514 * The values in PERF_METRICS MSR are derived from fixed counter 3. 2515 * Software should start both registers, PERF_METRICS and fixed 2516 * counter 3, from zero. 2517 * Clear PERF_METRICS and Fixed counter 3 in initialization. 2518 * After that, both MSRs will be cleared for each read. 2519 * Don't need to clear them again. 2520 */ 2521 if (left == x86_pmu.max_period) { 2522 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 2523 wrmsrl(MSR_PERF_METRICS, 0); 2524 hwc->saved_slots = 0; 2525 hwc->saved_metric = 0; 2526 } 2527 2528 if ((hwc->saved_slots) && is_slots_event(event)) { 2529 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots); 2530 wrmsrl(MSR_PERF_METRICS, hwc->saved_metric); 2531 } 2532 2533 perf_event_update_userpage(event); 2534 2535 return 0; 2536 } 2537 2538 static int adl_set_topdown_event_period(struct perf_event *event) 2539 { 2540 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 2541 2542 if (pmu->cpu_type != hybrid_big) 2543 return 0; 2544 2545 return icl_set_topdown_event_period(event); 2546 } 2547 2548 DEFINE_STATIC_CALL(intel_pmu_set_topdown_event_period, x86_perf_event_set_period); 2549 2550 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx) 2551 { 2552 u32 val; 2553 2554 /* 2555 * The metric is reported as an 8bit integer fraction 2556 * summing up to 0xff. 2557 * slots-in-metric = (Metric / 0xff) * slots 2558 */ 2559 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff; 2560 return mul_u64_u32_div(slots, val, 0xff); 2561 } 2562 2563 static u64 icl_get_topdown_value(struct perf_event *event, 2564 u64 slots, u64 metrics) 2565 { 2566 int idx = event->hw.idx; 2567 u64 delta; 2568 2569 if (is_metric_idx(idx)) 2570 delta = icl_get_metrics_event_value(metrics, slots, idx); 2571 else 2572 delta = slots; 2573 2574 return delta; 2575 } 2576 2577 static void __icl_update_topdown_event(struct perf_event *event, 2578 u64 slots, u64 metrics, 2579 u64 last_slots, u64 last_metrics) 2580 { 2581 u64 delta, last = 0; 2582 2583 delta = icl_get_topdown_value(event, slots, metrics); 2584 if (last_slots) 2585 last = icl_get_topdown_value(event, last_slots, last_metrics); 2586 2587 /* 2588 * The 8bit integer fraction of metric may be not accurate, 2589 * especially when the changes is very small. 2590 * For example, if only a few bad_spec happens, the fraction 2591 * may be reduced from 1 to 0. If so, the bad_spec event value 2592 * will be 0 which is definitely less than the last value. 2593 * Avoid update event->count for this case. 2594 */ 2595 if (delta > last) { 2596 delta -= last; 2597 local64_add(delta, &event->count); 2598 } 2599 } 2600 2601 static void update_saved_topdown_regs(struct perf_event *event, u64 slots, 2602 u64 metrics, int metric_end) 2603 { 2604 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2605 struct perf_event *other; 2606 int idx; 2607 2608 event->hw.saved_slots = slots; 2609 event->hw.saved_metric = metrics; 2610 2611 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2612 if (!is_topdown_idx(idx)) 2613 continue; 2614 other = cpuc->events[idx]; 2615 other->hw.saved_slots = slots; 2616 other->hw.saved_metric = metrics; 2617 } 2618 } 2619 2620 /* 2621 * Update all active Topdown events. 2622 * 2623 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be 2624 * modify by a NMI. PMU has to be disabled before calling this function. 2625 */ 2626 2627 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end) 2628 { 2629 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2630 struct perf_event *other; 2631 u64 slots, metrics; 2632 bool reset = true; 2633 int idx; 2634 2635 /* read Fixed counter 3 */ 2636 rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots); 2637 if (!slots) 2638 return 0; 2639 2640 /* read PERF_METRICS */ 2641 rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics); 2642 2643 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2644 if (!is_topdown_idx(idx)) 2645 continue; 2646 other = cpuc->events[idx]; 2647 __icl_update_topdown_event(other, slots, metrics, 2648 event ? event->hw.saved_slots : 0, 2649 event ? event->hw.saved_metric : 0); 2650 } 2651 2652 /* 2653 * Check and update this event, which may have been cleared 2654 * in active_mask e.g. x86_pmu_stop() 2655 */ 2656 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) { 2657 __icl_update_topdown_event(event, slots, metrics, 2658 event->hw.saved_slots, 2659 event->hw.saved_metric); 2660 2661 /* 2662 * In x86_pmu_stop(), the event is cleared in active_mask first, 2663 * then drain the delta, which indicates context switch for 2664 * counting. 2665 * Save metric and slots for context switch. 2666 * Don't need to reset the PERF_METRICS and Fixed counter 3. 2667 * Because the values will be restored in next schedule in. 2668 */ 2669 update_saved_topdown_regs(event, slots, metrics, metric_end); 2670 reset = false; 2671 } 2672 2673 if (reset) { 2674 /* The fixed counter 3 has to be written before the PERF_METRICS. */ 2675 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 2676 wrmsrl(MSR_PERF_METRICS, 0); 2677 if (event) 2678 update_saved_topdown_regs(event, 0, 0, metric_end); 2679 } 2680 2681 return slots; 2682 } 2683 2684 static u64 icl_update_topdown_event(struct perf_event *event) 2685 { 2686 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE + 2687 x86_pmu.num_topdown_events - 1); 2688 } 2689 2690 static u64 adl_update_topdown_event(struct perf_event *event) 2691 { 2692 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 2693 2694 if (pmu->cpu_type != hybrid_big) 2695 return 0; 2696 2697 return icl_update_topdown_event(event); 2698 } 2699 2700 DEFINE_STATIC_CALL(intel_pmu_update_topdown_event, x86_perf_event_update); 2701 2702 static void intel_pmu_read_topdown_event(struct perf_event *event) 2703 { 2704 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2705 2706 /* Only need to call update_topdown_event() once for group read. */ 2707 if ((cpuc->txn_flags & PERF_PMU_TXN_READ) && 2708 !is_slots_event(event)) 2709 return; 2710 2711 perf_pmu_disable(event->pmu); 2712 static_call(intel_pmu_update_topdown_event)(event); 2713 perf_pmu_enable(event->pmu); 2714 } 2715 2716 static void intel_pmu_read_event(struct perf_event *event) 2717 { 2718 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 2719 intel_pmu_auto_reload_read(event); 2720 else if (is_topdown_count(event)) 2721 intel_pmu_read_topdown_event(event); 2722 else 2723 x86_perf_event_update(event); 2724 } 2725 2726 static void intel_pmu_enable_fixed(struct perf_event *event) 2727 { 2728 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2729 struct hw_perf_event *hwc = &event->hw; 2730 u64 mask, bits = 0; 2731 int idx = hwc->idx; 2732 2733 if (is_topdown_idx(idx)) { 2734 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2735 /* 2736 * When there are other active TopDown events, 2737 * don't enable the fixed counter 3 again. 2738 */ 2739 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2740 return; 2741 2742 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2743 } 2744 2745 intel_set_masks(event, idx); 2746 2747 /* 2748 * Enable IRQ generation (0x8), if not PEBS, 2749 * and enable ring-3 counting (0x2) and ring-0 counting (0x1) 2750 * if requested: 2751 */ 2752 if (!event->attr.precise_ip) 2753 bits |= 0x8; 2754 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 2755 bits |= 0x2; 2756 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 2757 bits |= 0x1; 2758 2759 /* 2760 * ANY bit is supported in v3 and up 2761 */ 2762 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 2763 bits |= 0x4; 2764 2765 idx -= INTEL_PMC_IDX_FIXED; 2766 bits <<= (idx * 4); 2767 mask = 0xfULL << (idx * 4); 2768 2769 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) { 2770 bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2771 mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2772 } 2773 2774 cpuc->fixed_ctrl_val &= ~mask; 2775 cpuc->fixed_ctrl_val |= bits; 2776 } 2777 2778 static void intel_pmu_enable_event(struct perf_event *event) 2779 { 2780 struct hw_perf_event *hwc = &event->hw; 2781 int idx = hwc->idx; 2782 2783 if (unlikely(event->attr.precise_ip)) 2784 intel_pmu_pebs_enable(event); 2785 2786 switch (idx) { 2787 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2788 intel_set_masks(event, idx); 2789 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 2790 break; 2791 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2792 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2793 intel_pmu_enable_fixed(event); 2794 break; 2795 case INTEL_PMC_IDX_FIXED_BTS: 2796 if (!__this_cpu_read(cpu_hw_events.enabled)) 2797 return; 2798 intel_pmu_enable_bts(hwc->config); 2799 break; 2800 case INTEL_PMC_IDX_FIXED_VLBR: 2801 intel_set_masks(event, idx); 2802 break; 2803 default: 2804 pr_warn("Failed to enable the event with invalid index %d\n", 2805 idx); 2806 } 2807 } 2808 2809 static void intel_pmu_add_event(struct perf_event *event) 2810 { 2811 if (event->attr.precise_ip) 2812 intel_pmu_pebs_add(event); 2813 if (needs_branch_stack(event)) 2814 intel_pmu_lbr_add(event); 2815 } 2816 2817 /* 2818 * Save and restart an expired event. Called by NMI contexts, 2819 * so it has to be careful about preempting normal event ops: 2820 */ 2821 int intel_pmu_save_and_restart(struct perf_event *event) 2822 { 2823 static_call(x86_pmu_update)(event); 2824 /* 2825 * For a checkpointed counter always reset back to 0. This 2826 * avoids a situation where the counter overflows, aborts the 2827 * transaction and is then set back to shortly before the 2828 * overflow, and overflows and aborts again. 2829 */ 2830 if (unlikely(event_is_checkpointed(event))) { 2831 /* No race with NMIs because the counter should not be armed */ 2832 wrmsrl(event->hw.event_base, 0); 2833 local64_set(&event->hw.prev_count, 0); 2834 } 2835 return static_call(x86_pmu_set_period)(event); 2836 } 2837 2838 static int intel_pmu_set_period(struct perf_event *event) 2839 { 2840 if (unlikely(is_topdown_count(event))) 2841 return static_call(intel_pmu_set_topdown_event_period)(event); 2842 2843 return x86_perf_event_set_period(event); 2844 } 2845 2846 static u64 intel_pmu_update(struct perf_event *event) 2847 { 2848 if (unlikely(is_topdown_count(event))) 2849 return static_call(intel_pmu_update_topdown_event)(event); 2850 2851 return x86_perf_event_update(event); 2852 } 2853 2854 static void intel_pmu_reset(void) 2855 { 2856 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 2857 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2858 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed); 2859 int num_counters = hybrid(cpuc->pmu, num_counters); 2860 unsigned long flags; 2861 int idx; 2862 2863 if (!num_counters) 2864 return; 2865 2866 local_irq_save(flags); 2867 2868 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 2869 2870 for (idx = 0; idx < num_counters; idx++) { 2871 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); 2872 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); 2873 } 2874 for (idx = 0; idx < num_counters_fixed; idx++) { 2875 if (fixed_counter_disabled(idx, cpuc->pmu)) 2876 continue; 2877 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); 2878 } 2879 2880 if (ds) 2881 ds->bts_index = ds->bts_buffer_base; 2882 2883 /* Ack all overflows and disable fixed counters */ 2884 if (x86_pmu.version >= 2) { 2885 intel_pmu_ack_status(intel_pmu_get_status()); 2886 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2887 } 2888 2889 /* Reset LBRs and LBR freezing */ 2890 if (x86_pmu.lbr_nr) { 2891 update_debugctlmsr(get_debugctlmsr() & 2892 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 2893 } 2894 2895 local_irq_restore(flags); 2896 } 2897 2898 /* 2899 * We may be running with guest PEBS events created by KVM, and the 2900 * PEBS records are logged into the guest's DS and invisible to host. 2901 * 2902 * In the case of guest PEBS overflow, we only trigger a fake event 2903 * to emulate the PEBS overflow PMI for guest PEBS counters in KVM. 2904 * The guest will then vm-entry and check the guest DS area to read 2905 * the guest PEBS records. 2906 * 2907 * The contents and other behavior of the guest event do not matter. 2908 */ 2909 static void x86_pmu_handle_guest_pebs(struct pt_regs *regs, 2910 struct perf_sample_data *data) 2911 { 2912 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2913 u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask; 2914 struct perf_event *event = NULL; 2915 int bit; 2916 2917 if (!unlikely(perf_guest_state())) 2918 return; 2919 2920 if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active || 2921 !guest_pebs_idxs) 2922 return; 2923 2924 for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs, 2925 INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed) { 2926 event = cpuc->events[bit]; 2927 if (!event->attr.precise_ip) 2928 continue; 2929 2930 perf_sample_data_init(data, 0, event->hw.last_period); 2931 if (perf_event_overflow(event, data, regs)) 2932 x86_pmu_stop(event, 0); 2933 2934 /* Inject one fake event is enough. */ 2935 break; 2936 } 2937 } 2938 2939 static int handle_pmi_common(struct pt_regs *regs, u64 status) 2940 { 2941 struct perf_sample_data data; 2942 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2943 int bit; 2944 int handled = 0; 2945 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 2946 2947 inc_irq_stat(apic_perf_irqs); 2948 2949 /* 2950 * Ignore a range of extra bits in status that do not indicate 2951 * overflow by themselves. 2952 */ 2953 status &= ~(GLOBAL_STATUS_COND_CHG | 2954 GLOBAL_STATUS_ASIF | 2955 GLOBAL_STATUS_LBRS_FROZEN); 2956 if (!status) 2957 return 0; 2958 /* 2959 * In case multiple PEBS events are sampled at the same time, 2960 * it is possible to have GLOBAL_STATUS bit 62 set indicating 2961 * PEBS buffer overflow and also seeing at most 3 PEBS counters 2962 * having their bits set in the status register. This is a sign 2963 * that there was at least one PEBS record pending at the time 2964 * of the PMU interrupt. PEBS counters must only be processed 2965 * via the drain_pebs() calls and not via the regular sample 2966 * processing loop coming after that the function, otherwise 2967 * phony regular samples may be generated in the sampling buffer 2968 * not marked with the EXACT tag. Another possibility is to have 2969 * one PEBS event and at least one non-PEBS event which overflows 2970 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 2971 * not be set, yet the overflow status bit for the PEBS counter will 2972 * be on Skylake. 2973 * 2974 * To avoid this problem, we systematically ignore the PEBS-enabled 2975 * counters from the GLOBAL_STATUS mask and we always process PEBS 2976 * events via drain_pebs(). 2977 */ 2978 status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable); 2979 2980 /* 2981 * PEBS overflow sets bit 62 in the global status register 2982 */ 2983 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) { 2984 u64 pebs_enabled = cpuc->pebs_enabled; 2985 2986 handled++; 2987 x86_pmu_handle_guest_pebs(regs, &data); 2988 x86_pmu.drain_pebs(regs, &data); 2989 status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; 2990 2991 /* 2992 * PMI throttle may be triggered, which stops the PEBS event. 2993 * Although cpuc->pebs_enabled is updated accordingly, the 2994 * MSR_IA32_PEBS_ENABLE is not updated. Because the 2995 * cpuc->enabled has been forced to 0 in PMI. 2996 * Update the MSR if pebs_enabled is changed. 2997 */ 2998 if (pebs_enabled != cpuc->pebs_enabled) 2999 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 3000 } 3001 3002 /* 3003 * Intel PT 3004 */ 3005 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) { 3006 handled++; 3007 if (!perf_guest_handle_intel_pt_intr()) 3008 intel_pt_interrupt(); 3009 } 3010 3011 /* 3012 * Intel Perf metrics 3013 */ 3014 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) { 3015 handled++; 3016 static_call(intel_pmu_update_topdown_event)(NULL); 3017 } 3018 3019 /* 3020 * Checkpointed counters can lead to 'spurious' PMIs because the 3021 * rollback caused by the PMI will have cleared the overflow status 3022 * bit. Therefore always force probe these counters. 3023 */ 3024 status |= cpuc->intel_cp_status; 3025 3026 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 3027 struct perf_event *event = cpuc->events[bit]; 3028 3029 handled++; 3030 3031 if (!test_bit(bit, cpuc->active_mask)) 3032 continue; 3033 3034 if (!intel_pmu_save_and_restart(event)) 3035 continue; 3036 3037 perf_sample_data_init(&data, 0, event->hw.last_period); 3038 3039 if (has_branch_stack(event)) 3040 perf_sample_save_brstack(&data, event, &cpuc->lbr_stack); 3041 3042 if (perf_event_overflow(event, &data, regs)) 3043 x86_pmu_stop(event, 0); 3044 } 3045 3046 return handled; 3047 } 3048 3049 /* 3050 * This handler is triggered by the local APIC, so the APIC IRQ handling 3051 * rules apply: 3052 */ 3053 static int intel_pmu_handle_irq(struct pt_regs *regs) 3054 { 3055 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3056 bool late_ack = hybrid_bit(cpuc->pmu, late_ack); 3057 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack); 3058 int loops; 3059 u64 status; 3060 int handled; 3061 int pmu_enabled; 3062 3063 /* 3064 * Save the PMU state. 3065 * It needs to be restored when leaving the handler. 3066 */ 3067 pmu_enabled = cpuc->enabled; 3068 /* 3069 * In general, the early ACK is only applied for old platforms. 3070 * For the big core starts from Haswell, the late ACK should be 3071 * applied. 3072 * For the small core after Tremont, we have to do the ACK right 3073 * before re-enabling counters, which is in the middle of the 3074 * NMI handler. 3075 */ 3076 if (!late_ack && !mid_ack) 3077 apic_write(APIC_LVTPC, APIC_DM_NMI); 3078 intel_bts_disable_local(); 3079 cpuc->enabled = 0; 3080 __intel_pmu_disable_all(true); 3081 handled = intel_pmu_drain_bts_buffer(); 3082 handled += intel_bts_interrupt(); 3083 status = intel_pmu_get_status(); 3084 if (!status) 3085 goto done; 3086 3087 loops = 0; 3088 again: 3089 intel_pmu_lbr_read(); 3090 intel_pmu_ack_status(status); 3091 if (++loops > 100) { 3092 static bool warned; 3093 3094 if (!warned) { 3095 WARN(1, "perfevents: irq loop stuck!\n"); 3096 perf_event_print_debug(); 3097 warned = true; 3098 } 3099 intel_pmu_reset(); 3100 goto done; 3101 } 3102 3103 handled += handle_pmi_common(regs, status); 3104 3105 /* 3106 * Repeat if there is more work to be done: 3107 */ 3108 status = intel_pmu_get_status(); 3109 if (status) 3110 goto again; 3111 3112 done: 3113 if (mid_ack) 3114 apic_write(APIC_LVTPC, APIC_DM_NMI); 3115 /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 3116 cpuc->enabled = pmu_enabled; 3117 if (pmu_enabled) 3118 __intel_pmu_enable_all(0, true); 3119 intel_bts_enable_local(); 3120 3121 /* 3122 * Only unmask the NMI after the overflow counters 3123 * have been reset. This avoids spurious NMIs on 3124 * Haswell CPUs. 3125 */ 3126 if (late_ack) 3127 apic_write(APIC_LVTPC, APIC_DM_NMI); 3128 return handled; 3129 } 3130 3131 static struct event_constraint * 3132 intel_bts_constraints(struct perf_event *event) 3133 { 3134 if (unlikely(intel_pmu_has_bts(event))) 3135 return &bts_constraint; 3136 3137 return NULL; 3138 } 3139 3140 /* 3141 * Note: matches a fake event, like Fixed2. 3142 */ 3143 static struct event_constraint * 3144 intel_vlbr_constraints(struct perf_event *event) 3145 { 3146 struct event_constraint *c = &vlbr_constraint; 3147 3148 if (unlikely(constraint_match(c, event->hw.config))) { 3149 event->hw.flags |= c->flags; 3150 return c; 3151 } 3152 3153 return NULL; 3154 } 3155 3156 static int intel_alt_er(struct cpu_hw_events *cpuc, 3157 int idx, u64 config) 3158 { 3159 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs); 3160 int alt_idx = idx; 3161 3162 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 3163 return idx; 3164 3165 if (idx == EXTRA_REG_RSP_0) 3166 alt_idx = EXTRA_REG_RSP_1; 3167 3168 if (idx == EXTRA_REG_RSP_1) 3169 alt_idx = EXTRA_REG_RSP_0; 3170 3171 if (config & ~extra_regs[alt_idx].valid_mask) 3172 return idx; 3173 3174 return alt_idx; 3175 } 3176 3177 static void intel_fixup_er(struct perf_event *event, int idx) 3178 { 3179 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs); 3180 event->hw.extra_reg.idx = idx; 3181 3182 if (idx == EXTRA_REG_RSP_0) { 3183 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3184 event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event; 3185 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; 3186 } else if (idx == EXTRA_REG_RSP_1) { 3187 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3188 event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event; 3189 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; 3190 } 3191 } 3192 3193 /* 3194 * manage allocation of shared extra msr for certain events 3195 * 3196 * sharing can be: 3197 * per-cpu: to be shared between the various events on a single PMU 3198 * per-core: per-cpu + shared by HT threads 3199 */ 3200 static struct event_constraint * 3201 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 3202 struct perf_event *event, 3203 struct hw_perf_event_extra *reg) 3204 { 3205 struct event_constraint *c = &emptyconstraint; 3206 struct er_account *era; 3207 unsigned long flags; 3208 int idx = reg->idx; 3209 3210 /* 3211 * reg->alloc can be set due to existing state, so for fake cpuc we 3212 * need to ignore this, otherwise we might fail to allocate proper fake 3213 * state for this extra reg constraint. Also see the comment below. 3214 */ 3215 if (reg->alloc && !cpuc->is_fake) 3216 return NULL; /* call x86_get_event_constraint() */ 3217 3218 again: 3219 era = &cpuc->shared_regs->regs[idx]; 3220 /* 3221 * we use spin_lock_irqsave() to avoid lockdep issues when 3222 * passing a fake cpuc 3223 */ 3224 raw_spin_lock_irqsave(&era->lock, flags); 3225 3226 if (!atomic_read(&era->ref) || era->config == reg->config) { 3227 3228 /* 3229 * If its a fake cpuc -- as per validate_{group,event}() we 3230 * shouldn't touch event state and we can avoid doing so 3231 * since both will only call get_event_constraints() once 3232 * on each event, this avoids the need for reg->alloc. 3233 * 3234 * Not doing the ER fixup will only result in era->reg being 3235 * wrong, but since we won't actually try and program hardware 3236 * this isn't a problem either. 3237 */ 3238 if (!cpuc->is_fake) { 3239 if (idx != reg->idx) 3240 intel_fixup_er(event, idx); 3241 3242 /* 3243 * x86_schedule_events() can call get_event_constraints() 3244 * multiple times on events in the case of incremental 3245 * scheduling(). reg->alloc ensures we only do the ER 3246 * allocation once. 3247 */ 3248 reg->alloc = 1; 3249 } 3250 3251 /* lock in msr value */ 3252 era->config = reg->config; 3253 era->reg = reg->reg; 3254 3255 /* one more user */ 3256 atomic_inc(&era->ref); 3257 3258 /* 3259 * need to call x86_get_event_constraint() 3260 * to check if associated event has constraints 3261 */ 3262 c = NULL; 3263 } else { 3264 idx = intel_alt_er(cpuc, idx, reg->config); 3265 if (idx != reg->idx) { 3266 raw_spin_unlock_irqrestore(&era->lock, flags); 3267 goto again; 3268 } 3269 } 3270 raw_spin_unlock_irqrestore(&era->lock, flags); 3271 3272 return c; 3273 } 3274 3275 static void 3276 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 3277 struct hw_perf_event_extra *reg) 3278 { 3279 struct er_account *era; 3280 3281 /* 3282 * Only put constraint if extra reg was actually allocated. Also takes 3283 * care of event which do not use an extra shared reg. 3284 * 3285 * Also, if this is a fake cpuc we shouldn't touch any event state 3286 * (reg->alloc) and we don't care about leaving inconsistent cpuc state 3287 * either since it'll be thrown out. 3288 */ 3289 if (!reg->alloc || cpuc->is_fake) 3290 return; 3291 3292 era = &cpuc->shared_regs->regs[reg->idx]; 3293 3294 /* one fewer user */ 3295 atomic_dec(&era->ref); 3296 3297 /* allocate again next time */ 3298 reg->alloc = 0; 3299 } 3300 3301 static struct event_constraint * 3302 intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 3303 struct perf_event *event) 3304 { 3305 struct event_constraint *c = NULL, *d; 3306 struct hw_perf_event_extra *xreg, *breg; 3307 3308 xreg = &event->hw.extra_reg; 3309 if (xreg->idx != EXTRA_REG_NONE) { 3310 c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 3311 if (c == &emptyconstraint) 3312 return c; 3313 } 3314 breg = &event->hw.branch_reg; 3315 if (breg->idx != EXTRA_REG_NONE) { 3316 d = __intel_shared_reg_get_constraints(cpuc, event, breg); 3317 if (d == &emptyconstraint) { 3318 __intel_shared_reg_put_constraints(cpuc, xreg); 3319 c = d; 3320 } 3321 } 3322 return c; 3323 } 3324 3325 struct event_constraint * 3326 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3327 struct perf_event *event) 3328 { 3329 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints); 3330 struct event_constraint *c; 3331 3332 if (event_constraints) { 3333 for_each_event_constraint(c, event_constraints) { 3334 if (constraint_match(c, event->hw.config)) { 3335 event->hw.flags |= c->flags; 3336 return c; 3337 } 3338 } 3339 } 3340 3341 return &hybrid_var(cpuc->pmu, unconstrained); 3342 } 3343 3344 static struct event_constraint * 3345 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3346 struct perf_event *event) 3347 { 3348 struct event_constraint *c; 3349 3350 c = intel_vlbr_constraints(event); 3351 if (c) 3352 return c; 3353 3354 c = intel_bts_constraints(event); 3355 if (c) 3356 return c; 3357 3358 c = intel_shared_regs_constraints(cpuc, event); 3359 if (c) 3360 return c; 3361 3362 c = intel_pebs_constraints(event); 3363 if (c) 3364 return c; 3365 3366 return x86_get_event_constraints(cpuc, idx, event); 3367 } 3368 3369 static void 3370 intel_start_scheduling(struct cpu_hw_events *cpuc) 3371 { 3372 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3373 struct intel_excl_states *xl; 3374 int tid = cpuc->excl_thread_id; 3375 3376 /* 3377 * nothing needed if in group validation mode 3378 */ 3379 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3380 return; 3381 3382 /* 3383 * no exclusion needed 3384 */ 3385 if (WARN_ON_ONCE(!excl_cntrs)) 3386 return; 3387 3388 xl = &excl_cntrs->states[tid]; 3389 3390 xl->sched_started = true; 3391 /* 3392 * lock shared state until we are done scheduling 3393 * in stop_event_scheduling() 3394 * makes scheduling appear as a transaction 3395 */ 3396 raw_spin_lock(&excl_cntrs->lock); 3397 } 3398 3399 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 3400 { 3401 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3402 struct event_constraint *c = cpuc->event_constraint[idx]; 3403 struct intel_excl_states *xl; 3404 int tid = cpuc->excl_thread_id; 3405 3406 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3407 return; 3408 3409 if (WARN_ON_ONCE(!excl_cntrs)) 3410 return; 3411 3412 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 3413 return; 3414 3415 xl = &excl_cntrs->states[tid]; 3416 3417 lockdep_assert_held(&excl_cntrs->lock); 3418 3419 if (c->flags & PERF_X86_EVENT_EXCL) 3420 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 3421 else 3422 xl->state[cntr] = INTEL_EXCL_SHARED; 3423 } 3424 3425 static void 3426 intel_stop_scheduling(struct cpu_hw_events *cpuc) 3427 { 3428 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3429 struct intel_excl_states *xl; 3430 int tid = cpuc->excl_thread_id; 3431 3432 /* 3433 * nothing needed if in group validation mode 3434 */ 3435 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3436 return; 3437 /* 3438 * no exclusion needed 3439 */ 3440 if (WARN_ON_ONCE(!excl_cntrs)) 3441 return; 3442 3443 xl = &excl_cntrs->states[tid]; 3444 3445 xl->sched_started = false; 3446 /* 3447 * release shared state lock (acquired in intel_start_scheduling()) 3448 */ 3449 raw_spin_unlock(&excl_cntrs->lock); 3450 } 3451 3452 static struct event_constraint * 3453 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx) 3454 { 3455 WARN_ON_ONCE(!cpuc->constraint_list); 3456 3457 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 3458 struct event_constraint *cx; 3459 3460 /* 3461 * grab pre-allocated constraint entry 3462 */ 3463 cx = &cpuc->constraint_list[idx]; 3464 3465 /* 3466 * initialize dynamic constraint 3467 * with static constraint 3468 */ 3469 *cx = *c; 3470 3471 /* 3472 * mark constraint as dynamic 3473 */ 3474 cx->flags |= PERF_X86_EVENT_DYNAMIC; 3475 c = cx; 3476 } 3477 3478 return c; 3479 } 3480 3481 static struct event_constraint * 3482 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 3483 int idx, struct event_constraint *c) 3484 { 3485 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3486 struct intel_excl_states *xlo; 3487 int tid = cpuc->excl_thread_id; 3488 int is_excl, i, w; 3489 3490 /* 3491 * validating a group does not require 3492 * enforcing cross-thread exclusion 3493 */ 3494 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3495 return c; 3496 3497 /* 3498 * no exclusion needed 3499 */ 3500 if (WARN_ON_ONCE(!excl_cntrs)) 3501 return c; 3502 3503 /* 3504 * because we modify the constraint, we need 3505 * to make a copy. Static constraints come 3506 * from static const tables. 3507 * 3508 * only needed when constraint has not yet 3509 * been cloned (marked dynamic) 3510 */ 3511 c = dyn_constraint(cpuc, c, idx); 3512 3513 /* 3514 * From here on, the constraint is dynamic. 3515 * Either it was just allocated above, or it 3516 * was allocated during a earlier invocation 3517 * of this function 3518 */ 3519 3520 /* 3521 * state of sibling HT 3522 */ 3523 xlo = &excl_cntrs->states[tid ^ 1]; 3524 3525 /* 3526 * event requires exclusive counter access 3527 * across HT threads 3528 */ 3529 is_excl = c->flags & PERF_X86_EVENT_EXCL; 3530 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 3531 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 3532 if (!cpuc->n_excl++) 3533 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 3534 } 3535 3536 /* 3537 * Modify static constraint with current dynamic 3538 * state of thread 3539 * 3540 * EXCLUSIVE: sibling counter measuring exclusive event 3541 * SHARED : sibling counter measuring non-exclusive event 3542 * UNUSED : sibling counter unused 3543 */ 3544 w = c->weight; 3545 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 3546 /* 3547 * exclusive event in sibling counter 3548 * our corresponding counter cannot be used 3549 * regardless of our event 3550 */ 3551 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) { 3552 __clear_bit(i, c->idxmsk); 3553 w--; 3554 continue; 3555 } 3556 /* 3557 * if measuring an exclusive event, sibling 3558 * measuring non-exclusive, then counter cannot 3559 * be used 3560 */ 3561 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) { 3562 __clear_bit(i, c->idxmsk); 3563 w--; 3564 continue; 3565 } 3566 } 3567 3568 /* 3569 * if we return an empty mask, then switch 3570 * back to static empty constraint to avoid 3571 * the cost of freeing later on 3572 */ 3573 if (!w) 3574 c = &emptyconstraint; 3575 3576 c->weight = w; 3577 3578 return c; 3579 } 3580 3581 static struct event_constraint * 3582 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3583 struct perf_event *event) 3584 { 3585 struct event_constraint *c1, *c2; 3586 3587 c1 = cpuc->event_constraint[idx]; 3588 3589 /* 3590 * first time only 3591 * - static constraint: no change across incremental scheduling calls 3592 * - dynamic constraint: handled by intel_get_excl_constraints() 3593 */ 3594 c2 = __intel_get_event_constraints(cpuc, idx, event); 3595 if (c1) { 3596 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC)); 3597 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 3598 c1->weight = c2->weight; 3599 c2 = c1; 3600 } 3601 3602 if (cpuc->excl_cntrs) 3603 return intel_get_excl_constraints(cpuc, event, idx, c2); 3604 3605 return c2; 3606 } 3607 3608 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 3609 struct perf_event *event) 3610 { 3611 struct hw_perf_event *hwc = &event->hw; 3612 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3613 int tid = cpuc->excl_thread_id; 3614 struct intel_excl_states *xl; 3615 3616 /* 3617 * nothing needed if in group validation mode 3618 */ 3619 if (cpuc->is_fake) 3620 return; 3621 3622 if (WARN_ON_ONCE(!excl_cntrs)) 3623 return; 3624 3625 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 3626 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 3627 if (!--cpuc->n_excl) 3628 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 3629 } 3630 3631 /* 3632 * If event was actually assigned, then mark the counter state as 3633 * unused now. 3634 */ 3635 if (hwc->idx >= 0) { 3636 xl = &excl_cntrs->states[tid]; 3637 3638 /* 3639 * put_constraint may be called from x86_schedule_events() 3640 * which already has the lock held so here make locking 3641 * conditional. 3642 */ 3643 if (!xl->sched_started) 3644 raw_spin_lock(&excl_cntrs->lock); 3645 3646 xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 3647 3648 if (!xl->sched_started) 3649 raw_spin_unlock(&excl_cntrs->lock); 3650 } 3651 } 3652 3653 static void 3654 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 3655 struct perf_event *event) 3656 { 3657 struct hw_perf_event_extra *reg; 3658 3659 reg = &event->hw.extra_reg; 3660 if (reg->idx != EXTRA_REG_NONE) 3661 __intel_shared_reg_put_constraints(cpuc, reg); 3662 3663 reg = &event->hw.branch_reg; 3664 if (reg->idx != EXTRA_REG_NONE) 3665 __intel_shared_reg_put_constraints(cpuc, reg); 3666 } 3667 3668 static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 3669 struct perf_event *event) 3670 { 3671 intel_put_shared_regs_event_constraints(cpuc, event); 3672 3673 /* 3674 * is PMU has exclusive counter restrictions, then 3675 * all events are subject to and must call the 3676 * put_excl_constraints() routine 3677 */ 3678 if (cpuc->excl_cntrs) 3679 intel_put_excl_constraints(cpuc, event); 3680 } 3681 3682 static void intel_pebs_aliases_core2(struct perf_event *event) 3683 { 3684 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3685 /* 3686 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3687 * (0x003c) so that we can use it with PEBS. 3688 * 3689 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3690 * PEBS capable. However we can use INST_RETIRED.ANY_P 3691 * (0x00c0), which is a PEBS capable event, to get the same 3692 * count. 3693 * 3694 * INST_RETIRED.ANY_P counts the number of cycles that retires 3695 * CNTMASK instructions. By setting CNTMASK to a value (16) 3696 * larger than the maximum number of instructions that can be 3697 * retired per cycle (4) and then inverting the condition, we 3698 * count all cycles that retire 16 or less instructions, which 3699 * is every cycle. 3700 * 3701 * Thereby we gain a PEBS capable cycle counter. 3702 */ 3703 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 3704 3705 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3706 event->hw.config = alt_config; 3707 } 3708 } 3709 3710 static void intel_pebs_aliases_snb(struct perf_event *event) 3711 { 3712 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3713 /* 3714 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3715 * (0x003c) so that we can use it with PEBS. 3716 * 3717 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3718 * PEBS capable. However we can use UOPS_RETIRED.ALL 3719 * (0x01c2), which is a PEBS capable event, to get the same 3720 * count. 3721 * 3722 * UOPS_RETIRED.ALL counts the number of cycles that retires 3723 * CNTMASK micro-ops. By setting CNTMASK to a value (16) 3724 * larger than the maximum number of micro-ops that can be 3725 * retired per cycle (4) and then inverting the condition, we 3726 * count all cycles that retire 16 or less micro-ops, which 3727 * is every cycle. 3728 * 3729 * Thereby we gain a PEBS capable cycle counter. 3730 */ 3731 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 3732 3733 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3734 event->hw.config = alt_config; 3735 } 3736 } 3737 3738 static void intel_pebs_aliases_precdist(struct perf_event *event) 3739 { 3740 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3741 /* 3742 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3743 * (0x003c) so that we can use it with PEBS. 3744 * 3745 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3746 * PEBS capable. However we can use INST_RETIRED.PREC_DIST 3747 * (0x01c0), which is a PEBS capable event, to get the same 3748 * count. 3749 * 3750 * The PREC_DIST event has special support to minimize sample 3751 * shadowing effects. One drawback is that it can be 3752 * only programmed on counter 1, but that seems like an 3753 * acceptable trade off. 3754 */ 3755 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 3756 3757 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3758 event->hw.config = alt_config; 3759 } 3760 } 3761 3762 static void intel_pebs_aliases_ivb(struct perf_event *event) 3763 { 3764 if (event->attr.precise_ip < 3) 3765 return intel_pebs_aliases_snb(event); 3766 return intel_pebs_aliases_precdist(event); 3767 } 3768 3769 static void intel_pebs_aliases_skl(struct perf_event *event) 3770 { 3771 if (event->attr.precise_ip < 3) 3772 return intel_pebs_aliases_core2(event); 3773 return intel_pebs_aliases_precdist(event); 3774 } 3775 3776 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 3777 { 3778 unsigned long flags = x86_pmu.large_pebs_flags; 3779 3780 if (event->attr.use_clockid) 3781 flags &= ~PERF_SAMPLE_TIME; 3782 if (!event->attr.exclude_kernel) 3783 flags &= ~PERF_SAMPLE_REGS_USER; 3784 if (event->attr.sample_regs_user & ~PEBS_GP_REGS) 3785 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); 3786 return flags; 3787 } 3788 3789 static int intel_pmu_bts_config(struct perf_event *event) 3790 { 3791 struct perf_event_attr *attr = &event->attr; 3792 3793 if (unlikely(intel_pmu_has_bts(event))) { 3794 /* BTS is not supported by this architecture. */ 3795 if (!x86_pmu.bts_active) 3796 return -EOPNOTSUPP; 3797 3798 /* BTS is currently only allowed for user-mode. */ 3799 if (!attr->exclude_kernel) 3800 return -EOPNOTSUPP; 3801 3802 /* BTS is not allowed for precise events. */ 3803 if (attr->precise_ip) 3804 return -EOPNOTSUPP; 3805 3806 /* disallow bts if conflicting events are present */ 3807 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3808 return -EBUSY; 3809 3810 event->destroy = hw_perf_lbr_event_destroy; 3811 } 3812 3813 return 0; 3814 } 3815 3816 static int core_pmu_hw_config(struct perf_event *event) 3817 { 3818 int ret = x86_pmu_hw_config(event); 3819 3820 if (ret) 3821 return ret; 3822 3823 return intel_pmu_bts_config(event); 3824 } 3825 3826 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \ 3827 ((x86_pmu.num_topdown_events - 1) << 8)) 3828 3829 static bool is_available_metric_event(struct perf_event *event) 3830 { 3831 return is_metric_event(event) && 3832 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX; 3833 } 3834 3835 static inline bool is_mem_loads_event(struct perf_event *event) 3836 { 3837 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01); 3838 } 3839 3840 static inline bool is_mem_loads_aux_event(struct perf_event *event) 3841 { 3842 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82); 3843 } 3844 3845 static inline bool require_mem_loads_aux_event(struct perf_event *event) 3846 { 3847 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX)) 3848 return false; 3849 3850 if (is_hybrid()) 3851 return hybrid_pmu(event->pmu)->cpu_type == hybrid_big; 3852 3853 return true; 3854 } 3855 3856 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx) 3857 { 3858 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap); 3859 3860 return test_bit(idx, (unsigned long *)&intel_cap->capabilities); 3861 } 3862 3863 static int intel_pmu_hw_config(struct perf_event *event) 3864 { 3865 int ret = x86_pmu_hw_config(event); 3866 3867 if (ret) 3868 return ret; 3869 3870 ret = intel_pmu_bts_config(event); 3871 if (ret) 3872 return ret; 3873 3874 if (event->attr.precise_ip) { 3875 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT) 3876 return -EINVAL; 3877 3878 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) { 3879 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 3880 if (!(event->attr.sample_type & 3881 ~intel_pmu_large_pebs_flags(event))) { 3882 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; 3883 event->attach_state |= PERF_ATTACH_SCHED_CB; 3884 } 3885 } 3886 if (x86_pmu.pebs_aliases) 3887 x86_pmu.pebs_aliases(event); 3888 } 3889 3890 if (needs_branch_stack(event)) { 3891 ret = intel_pmu_setup_lbr_filter(event); 3892 if (ret) 3893 return ret; 3894 event->attach_state |= PERF_ATTACH_SCHED_CB; 3895 3896 /* 3897 * BTS is set up earlier in this path, so don't account twice 3898 */ 3899 if (!unlikely(intel_pmu_has_bts(event))) { 3900 /* disallow lbr if conflicting events are present */ 3901 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3902 return -EBUSY; 3903 3904 event->destroy = hw_perf_lbr_event_destroy; 3905 } 3906 } 3907 3908 if (event->attr.aux_output) { 3909 if (!event->attr.precise_ip) 3910 return -EINVAL; 3911 3912 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT; 3913 } 3914 3915 if ((event->attr.type == PERF_TYPE_HARDWARE) || 3916 (event->attr.type == PERF_TYPE_HW_CACHE)) 3917 return 0; 3918 3919 /* 3920 * Config Topdown slots and metric events 3921 * 3922 * The slots event on Fixed Counter 3 can support sampling, 3923 * which will be handled normally in x86_perf_event_update(). 3924 * 3925 * Metric events don't support sampling and require being paired 3926 * with a slots event as group leader. When the slots event 3927 * is used in a metrics group, it too cannot support sampling. 3928 */ 3929 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) { 3930 if (event->attr.config1 || event->attr.config2) 3931 return -EINVAL; 3932 3933 /* 3934 * The TopDown metrics events and slots event don't 3935 * support any filters. 3936 */ 3937 if (event->attr.config & X86_ALL_EVENT_FLAGS) 3938 return -EINVAL; 3939 3940 if (is_available_metric_event(event)) { 3941 struct perf_event *leader = event->group_leader; 3942 3943 /* The metric events don't support sampling. */ 3944 if (is_sampling_event(event)) 3945 return -EINVAL; 3946 3947 /* The metric events require a slots group leader. */ 3948 if (!is_slots_event(leader)) 3949 return -EINVAL; 3950 3951 /* 3952 * The leader/SLOTS must not be a sampling event for 3953 * metric use; hardware requires it starts at 0 when used 3954 * in conjunction with MSR_PERF_METRICS. 3955 */ 3956 if (is_sampling_event(leader)) 3957 return -EINVAL; 3958 3959 event->event_caps |= PERF_EV_CAP_SIBLING; 3960 /* 3961 * Only once we have a METRICs sibling do we 3962 * need TopDown magic. 3963 */ 3964 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN; 3965 event->hw.flags |= PERF_X86_EVENT_TOPDOWN; 3966 } 3967 } 3968 3969 /* 3970 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR 3971 * doesn't function quite right. As a work-around it needs to always be 3972 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82). 3973 * The actual count of this second event is irrelevant it just needs 3974 * to be active to make the first event function correctly. 3975 * 3976 * In a group, the auxiliary event must be in front of the load latency 3977 * event. The rule is to simplify the implementation of the check. 3978 * That's because perf cannot have a complete group at the moment. 3979 */ 3980 if (require_mem_loads_aux_event(event) && 3981 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) && 3982 is_mem_loads_event(event)) { 3983 struct perf_event *leader = event->group_leader; 3984 struct perf_event *sibling = NULL; 3985 3986 if (!is_mem_loads_aux_event(leader)) { 3987 for_each_sibling_event(sibling, leader) { 3988 if (is_mem_loads_aux_event(sibling)) 3989 break; 3990 } 3991 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list)) 3992 return -ENODATA; 3993 } 3994 } 3995 3996 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 3997 return 0; 3998 3999 if (x86_pmu.version < 3) 4000 return -EINVAL; 4001 4002 ret = perf_allow_cpu(&event->attr); 4003 if (ret) 4004 return ret; 4005 4006 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 4007 4008 return 0; 4009 } 4010 4011 /* 4012 * Currently, the only caller of this function is the atomic_switch_perf_msrs(). 4013 * The host perf conext helps to prepare the values of the real hardware for 4014 * a set of msrs that need to be switched atomically in a vmx transaction. 4015 * 4016 * For example, the pseudocode needed to add a new msr should look like: 4017 * 4018 * arr[(*nr)++] = (struct perf_guest_switch_msr){ 4019 * .msr = the hardware msr address, 4020 * .host = the value the hardware has when it doesn't run a guest, 4021 * .guest = the value the hardware has when it runs a guest, 4022 * }; 4023 * 4024 * These values have nothing to do with the emulated values the guest sees 4025 * when it uses {RD,WR}MSR, which should be handled by the KVM context, 4026 * specifically in the intel_pmu_{get,set}_msr(). 4027 */ 4028 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) 4029 { 4030 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4031 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 4032 struct kvm_pmu *kvm_pmu = (struct kvm_pmu *)data; 4033 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 4034 u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable; 4035 int global_ctrl, pebs_enable; 4036 4037 *nr = 0; 4038 global_ctrl = (*nr)++; 4039 arr[global_ctrl] = (struct perf_guest_switch_msr){ 4040 .msr = MSR_CORE_PERF_GLOBAL_CTRL, 4041 .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask, 4042 .guest = intel_ctrl & (~cpuc->intel_ctrl_host_mask | ~pebs_mask), 4043 }; 4044 4045 if (!x86_pmu.pebs) 4046 return arr; 4047 4048 /* 4049 * If PMU counter has PEBS enabled it is not enough to 4050 * disable counter on a guest entry since PEBS memory 4051 * write can overshoot guest entry and corrupt guest 4052 * memory. Disabling PEBS solves the problem. 4053 * 4054 * Don't do this if the CPU already enforces it. 4055 */ 4056 if (x86_pmu.pebs_no_isolation) { 4057 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4058 .msr = MSR_IA32_PEBS_ENABLE, 4059 .host = cpuc->pebs_enabled, 4060 .guest = 0, 4061 }; 4062 return arr; 4063 } 4064 4065 if (!kvm_pmu || !x86_pmu.pebs_ept) 4066 return arr; 4067 4068 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4069 .msr = MSR_IA32_DS_AREA, 4070 .host = (unsigned long)cpuc->ds, 4071 .guest = kvm_pmu->ds_area, 4072 }; 4073 4074 if (x86_pmu.intel_cap.pebs_baseline) { 4075 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4076 .msr = MSR_PEBS_DATA_CFG, 4077 .host = cpuc->pebs_data_cfg, 4078 .guest = kvm_pmu->pebs_data_cfg, 4079 }; 4080 } 4081 4082 pebs_enable = (*nr)++; 4083 arr[pebs_enable] = (struct perf_guest_switch_msr){ 4084 .msr = MSR_IA32_PEBS_ENABLE, 4085 .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask, 4086 .guest = pebs_mask & ~cpuc->intel_ctrl_host_mask, 4087 }; 4088 4089 if (arr[pebs_enable].host) { 4090 /* Disable guest PEBS if host PEBS is enabled. */ 4091 arr[pebs_enable].guest = 0; 4092 } else { 4093 /* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */ 4094 arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask; 4095 arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask; 4096 /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */ 4097 arr[global_ctrl].guest |= arr[pebs_enable].guest; 4098 } 4099 4100 return arr; 4101 } 4102 4103 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr, void *data) 4104 { 4105 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4106 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 4107 int idx; 4108 4109 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 4110 struct perf_event *event = cpuc->events[idx]; 4111 4112 arr[idx].msr = x86_pmu_config_addr(idx); 4113 arr[idx].host = arr[idx].guest = 0; 4114 4115 if (!test_bit(idx, cpuc->active_mask)) 4116 continue; 4117 4118 arr[idx].host = arr[idx].guest = 4119 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 4120 4121 if (event->attr.exclude_host) 4122 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 4123 else if (event->attr.exclude_guest) 4124 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 4125 } 4126 4127 *nr = x86_pmu.num_counters; 4128 return arr; 4129 } 4130 4131 static void core_pmu_enable_event(struct perf_event *event) 4132 { 4133 if (!event->attr.exclude_host) 4134 x86_pmu_enable_event(event); 4135 } 4136 4137 static void core_pmu_enable_all(int added) 4138 { 4139 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4140 int idx; 4141 4142 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 4143 struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 4144 4145 if (!test_bit(idx, cpuc->active_mask) || 4146 cpuc->events[idx]->attr.exclude_host) 4147 continue; 4148 4149 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 4150 } 4151 } 4152 4153 static int hsw_hw_config(struct perf_event *event) 4154 { 4155 int ret = intel_pmu_hw_config(event); 4156 4157 if (ret) 4158 return ret; 4159 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 4160 return 0; 4161 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 4162 4163 /* 4164 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 4165 * PEBS or in ANY thread mode. Since the results are non-sensical forbid 4166 * this combination. 4167 */ 4168 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 4169 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 4170 event->attr.precise_ip > 0)) 4171 return -EOPNOTSUPP; 4172 4173 if (event_is_checkpointed(event)) { 4174 /* 4175 * Sampling of checkpointed events can cause situations where 4176 * the CPU constantly aborts because of a overflow, which is 4177 * then checkpointed back and ignored. Forbid checkpointing 4178 * for sampling. 4179 * 4180 * But still allow a long sampling period, so that perf stat 4181 * from KVM works. 4182 */ 4183 if (event->attr.sample_period > 0 && 4184 event->attr.sample_period < 0x7fffffff) 4185 return -EOPNOTSUPP; 4186 } 4187 return 0; 4188 } 4189 4190 static struct event_constraint counter0_constraint = 4191 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 4192 4193 static struct event_constraint counter1_constraint = 4194 INTEL_ALL_EVENT_CONSTRAINT(0, 0x2); 4195 4196 static struct event_constraint counter0_1_constraint = 4197 INTEL_ALL_EVENT_CONSTRAINT(0, 0x3); 4198 4199 static struct event_constraint counter2_constraint = 4200 EVENT_CONSTRAINT(0, 0x4, 0); 4201 4202 static struct event_constraint fixed0_constraint = 4203 FIXED_EVENT_CONSTRAINT(0x00c0, 0); 4204 4205 static struct event_constraint fixed0_counter0_constraint = 4206 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); 4207 4208 static struct event_constraint fixed0_counter0_1_constraint = 4209 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000003ULL); 4210 4211 static struct event_constraint counters_1_7_constraint = 4212 INTEL_ALL_EVENT_CONSTRAINT(0, 0xfeULL); 4213 4214 static struct event_constraint * 4215 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4216 struct perf_event *event) 4217 { 4218 struct event_constraint *c; 4219 4220 c = intel_get_event_constraints(cpuc, idx, event); 4221 4222 /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 4223 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 4224 if (c->idxmsk64 & (1U << 2)) 4225 return &counter2_constraint; 4226 return &emptyconstraint; 4227 } 4228 4229 return c; 4230 } 4231 4232 static struct event_constraint * 4233 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4234 struct perf_event *event) 4235 { 4236 /* 4237 * Fixed counter 0 has less skid. 4238 * Force instruction:ppp in Fixed counter 0 4239 */ 4240 if ((event->attr.precise_ip == 3) && 4241 constraint_match(&fixed0_constraint, event->hw.config)) 4242 return &fixed0_constraint; 4243 4244 return hsw_get_event_constraints(cpuc, idx, event); 4245 } 4246 4247 static struct event_constraint * 4248 spr_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4249 struct perf_event *event) 4250 { 4251 struct event_constraint *c; 4252 4253 c = icl_get_event_constraints(cpuc, idx, event); 4254 4255 /* 4256 * The :ppp indicates the Precise Distribution (PDist) facility, which 4257 * is only supported on the GP counter 0. If a :ppp event which is not 4258 * available on the GP counter 0, error out. 4259 * Exception: Instruction PDIR is only available on the fixed counter 0. 4260 */ 4261 if ((event->attr.precise_ip == 3) && 4262 !constraint_match(&fixed0_constraint, event->hw.config)) { 4263 if (c->idxmsk64 & BIT_ULL(0)) 4264 return &counter0_constraint; 4265 4266 return &emptyconstraint; 4267 } 4268 4269 return c; 4270 } 4271 4272 static struct event_constraint * 4273 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4274 struct perf_event *event) 4275 { 4276 struct event_constraint *c; 4277 4278 /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 4279 if (event->attr.precise_ip == 3) 4280 return &counter0_constraint; 4281 4282 c = intel_get_event_constraints(cpuc, idx, event); 4283 4284 return c; 4285 } 4286 4287 static struct event_constraint * 4288 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4289 struct perf_event *event) 4290 { 4291 struct event_constraint *c; 4292 4293 c = intel_get_event_constraints(cpuc, idx, event); 4294 4295 /* 4296 * :ppp means to do reduced skid PEBS, 4297 * which is available on PMC0 and fixed counter 0. 4298 */ 4299 if (event->attr.precise_ip == 3) { 4300 /* Force instruction:ppp on PMC0 and Fixed counter 0 */ 4301 if (constraint_match(&fixed0_constraint, event->hw.config)) 4302 return &fixed0_counter0_constraint; 4303 4304 return &counter0_constraint; 4305 } 4306 4307 return c; 4308 } 4309 4310 static bool allow_tsx_force_abort = true; 4311 4312 static struct event_constraint * 4313 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4314 struct perf_event *event) 4315 { 4316 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event); 4317 4318 /* 4319 * Without TFA we must not use PMC3. 4320 */ 4321 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) { 4322 c = dyn_constraint(cpuc, c, idx); 4323 c->idxmsk64 &= ~(1ULL << 3); 4324 c->weight--; 4325 } 4326 4327 return c; 4328 } 4329 4330 static struct event_constraint * 4331 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4332 struct perf_event *event) 4333 { 4334 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4335 4336 if (pmu->cpu_type == hybrid_big) 4337 return spr_get_event_constraints(cpuc, idx, event); 4338 else if (pmu->cpu_type == hybrid_small) 4339 return tnt_get_event_constraints(cpuc, idx, event); 4340 4341 WARN_ON(1); 4342 return &emptyconstraint; 4343 } 4344 4345 static struct event_constraint * 4346 cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4347 struct perf_event *event) 4348 { 4349 struct event_constraint *c; 4350 4351 c = intel_get_event_constraints(cpuc, idx, event); 4352 4353 /* 4354 * The :ppp indicates the Precise Distribution (PDist) facility, which 4355 * is only supported on the GP counter 0 & 1 and Fixed counter 0. 4356 * If a :ppp event which is not available on the above eligible counters, 4357 * error out. 4358 */ 4359 if (event->attr.precise_ip == 3) { 4360 /* Force instruction:ppp on PMC0, 1 and Fixed counter 0 */ 4361 if (constraint_match(&fixed0_constraint, event->hw.config)) 4362 return &fixed0_counter0_1_constraint; 4363 4364 switch (c->idxmsk64 & 0x3ull) { 4365 case 0x1: 4366 return &counter0_constraint; 4367 case 0x2: 4368 return &counter1_constraint; 4369 case 0x3: 4370 return &counter0_1_constraint; 4371 } 4372 return &emptyconstraint; 4373 } 4374 4375 return c; 4376 } 4377 4378 static struct event_constraint * 4379 rwc_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4380 struct perf_event *event) 4381 { 4382 struct event_constraint *c; 4383 4384 c = spr_get_event_constraints(cpuc, idx, event); 4385 4386 /* The Retire Latency is not supported by the fixed counter 0. */ 4387 if (event->attr.precise_ip && 4388 (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE) && 4389 constraint_match(&fixed0_constraint, event->hw.config)) { 4390 /* 4391 * The Instruction PDIR is only available 4392 * on the fixed counter 0. Error out for this case. 4393 */ 4394 if (event->attr.precise_ip == 3) 4395 return &emptyconstraint; 4396 return &counters_1_7_constraint; 4397 } 4398 4399 return c; 4400 } 4401 4402 static struct event_constraint * 4403 mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4404 struct perf_event *event) 4405 { 4406 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4407 4408 if (pmu->cpu_type == hybrid_big) 4409 return rwc_get_event_constraints(cpuc, idx, event); 4410 if (pmu->cpu_type == hybrid_small) 4411 return cmt_get_event_constraints(cpuc, idx, event); 4412 4413 WARN_ON(1); 4414 return &emptyconstraint; 4415 } 4416 4417 static int adl_hw_config(struct perf_event *event) 4418 { 4419 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4420 4421 if (pmu->cpu_type == hybrid_big) 4422 return hsw_hw_config(event); 4423 else if (pmu->cpu_type == hybrid_small) 4424 return intel_pmu_hw_config(event); 4425 4426 WARN_ON(1); 4427 return -EOPNOTSUPP; 4428 } 4429 4430 static u8 adl_get_hybrid_cpu_type(void) 4431 { 4432 return hybrid_big; 4433 } 4434 4435 /* 4436 * Broadwell: 4437 * 4438 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 4439 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 4440 * the two to enforce a minimum period of 128 (the smallest value that has bits 4441 * 0-5 cleared and >= 100). 4442 * 4443 * Because of how the code in x86_perf_event_set_period() works, the truncation 4444 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 4445 * to make up for the 'lost' events due to carrying the 'error' in period_left. 4446 * 4447 * Therefore the effective (average) period matches the requested period, 4448 * despite coarser hardware granularity. 4449 */ 4450 static void bdw_limit_period(struct perf_event *event, s64 *left) 4451 { 4452 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) == 4453 X86_CONFIG(.event=0xc0, .umask=0x01)) { 4454 if (*left < 128) 4455 *left = 128; 4456 *left &= ~0x3fULL; 4457 } 4458 } 4459 4460 static void nhm_limit_period(struct perf_event *event, s64 *left) 4461 { 4462 *left = max(*left, 32LL); 4463 } 4464 4465 static void spr_limit_period(struct perf_event *event, s64 *left) 4466 { 4467 if (event->attr.precise_ip == 3) 4468 *left = max(*left, 128LL); 4469 } 4470 4471 PMU_FORMAT_ATTR(event, "config:0-7" ); 4472 PMU_FORMAT_ATTR(umask, "config:8-15" ); 4473 PMU_FORMAT_ATTR(edge, "config:18" ); 4474 PMU_FORMAT_ATTR(pc, "config:19" ); 4475 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 4476 PMU_FORMAT_ATTR(inv, "config:23" ); 4477 PMU_FORMAT_ATTR(cmask, "config:24-31" ); 4478 PMU_FORMAT_ATTR(in_tx, "config:32"); 4479 PMU_FORMAT_ATTR(in_tx_cp, "config:33"); 4480 4481 static struct attribute *intel_arch_formats_attr[] = { 4482 &format_attr_event.attr, 4483 &format_attr_umask.attr, 4484 &format_attr_edge.attr, 4485 &format_attr_pc.attr, 4486 &format_attr_inv.attr, 4487 &format_attr_cmask.attr, 4488 NULL, 4489 }; 4490 4491 ssize_t intel_event_sysfs_show(char *page, u64 config) 4492 { 4493 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 4494 4495 return x86_event_sysfs_show(page, config, event); 4496 } 4497 4498 static struct intel_shared_regs *allocate_shared_regs(int cpu) 4499 { 4500 struct intel_shared_regs *regs; 4501 int i; 4502 4503 regs = kzalloc_node(sizeof(struct intel_shared_regs), 4504 GFP_KERNEL, cpu_to_node(cpu)); 4505 if (regs) { 4506 /* 4507 * initialize the locks to keep lockdep happy 4508 */ 4509 for (i = 0; i < EXTRA_REG_MAX; i++) 4510 raw_spin_lock_init(®s->regs[i].lock); 4511 4512 regs->core_id = -1; 4513 } 4514 return regs; 4515 } 4516 4517 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 4518 { 4519 struct intel_excl_cntrs *c; 4520 4521 c = kzalloc_node(sizeof(struct intel_excl_cntrs), 4522 GFP_KERNEL, cpu_to_node(cpu)); 4523 if (c) { 4524 raw_spin_lock_init(&c->lock); 4525 c->core_id = -1; 4526 } 4527 return c; 4528 } 4529 4530 4531 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 4532 { 4533 cpuc->pebs_record_size = x86_pmu.pebs_record_size; 4534 4535 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 4536 cpuc->shared_regs = allocate_shared_regs(cpu); 4537 if (!cpuc->shared_regs) 4538 goto err; 4539 } 4540 4541 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) { 4542 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 4543 4544 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu)); 4545 if (!cpuc->constraint_list) 4546 goto err_shared_regs; 4547 } 4548 4549 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4550 cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 4551 if (!cpuc->excl_cntrs) 4552 goto err_constraint_list; 4553 4554 cpuc->excl_thread_id = 0; 4555 } 4556 4557 return 0; 4558 4559 err_constraint_list: 4560 kfree(cpuc->constraint_list); 4561 cpuc->constraint_list = NULL; 4562 4563 err_shared_regs: 4564 kfree(cpuc->shared_regs); 4565 cpuc->shared_regs = NULL; 4566 4567 err: 4568 return -ENOMEM; 4569 } 4570 4571 static int intel_pmu_cpu_prepare(int cpu) 4572 { 4573 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu); 4574 } 4575 4576 static void flip_smm_bit(void *data) 4577 { 4578 unsigned long set = *(unsigned long *)data; 4579 4580 if (set > 0) { 4581 msr_set_bit(MSR_IA32_DEBUGCTLMSR, 4582 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 4583 } else { 4584 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 4585 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 4586 } 4587 } 4588 4589 static void intel_pmu_check_num_counters(int *num_counters, 4590 int *num_counters_fixed, 4591 u64 *intel_ctrl, u64 fixed_mask); 4592 4593 static void update_pmu_cap(struct x86_hybrid_pmu *pmu) 4594 { 4595 unsigned int sub_bitmaps = cpuid_eax(ARCH_PERFMON_EXT_LEAF); 4596 unsigned int eax, ebx, ecx, edx; 4597 4598 if (sub_bitmaps & ARCH_PERFMON_NUM_COUNTER_LEAF_BIT) { 4599 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF, 4600 &eax, &ebx, &ecx, &edx); 4601 pmu->num_counters = fls(eax); 4602 pmu->num_counters_fixed = fls(ebx); 4603 intel_pmu_check_num_counters(&pmu->num_counters, &pmu->num_counters_fixed, 4604 &pmu->intel_ctrl, ebx); 4605 } 4606 } 4607 4608 static bool init_hybrid_pmu(int cpu) 4609 { 4610 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4611 u8 cpu_type = get_this_hybrid_cpu_type(); 4612 struct x86_hybrid_pmu *pmu = NULL; 4613 int i; 4614 4615 if (!cpu_type && x86_pmu.get_hybrid_cpu_type) 4616 cpu_type = x86_pmu.get_hybrid_cpu_type(); 4617 4618 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { 4619 if (x86_pmu.hybrid_pmu[i].cpu_type == cpu_type) { 4620 pmu = &x86_pmu.hybrid_pmu[i]; 4621 break; 4622 } 4623 } 4624 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) { 4625 cpuc->pmu = NULL; 4626 return false; 4627 } 4628 4629 /* Only check and dump the PMU information for the first CPU */ 4630 if (!cpumask_empty(&pmu->supported_cpus)) 4631 goto end; 4632 4633 if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT)) 4634 update_pmu_cap(pmu); 4635 4636 if (!check_hw_exists(&pmu->pmu, pmu->num_counters, pmu->num_counters_fixed)) 4637 return false; 4638 4639 pr_info("%s PMU driver: ", pmu->name); 4640 4641 if (pmu->intel_cap.pebs_output_pt_available) 4642 pr_cont("PEBS-via-PT "); 4643 4644 pr_cont("\n"); 4645 4646 x86_pmu_show_pmu_cap(pmu->num_counters, pmu->num_counters_fixed, 4647 pmu->intel_ctrl); 4648 4649 end: 4650 cpumask_set_cpu(cpu, &pmu->supported_cpus); 4651 cpuc->pmu = &pmu->pmu; 4652 4653 return true; 4654 } 4655 4656 static void intel_pmu_cpu_starting(int cpu) 4657 { 4658 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4659 int core_id = topology_core_id(cpu); 4660 int i; 4661 4662 if (is_hybrid() && !init_hybrid_pmu(cpu)) 4663 return; 4664 4665 init_debug_store_on_cpu(cpu); 4666 /* 4667 * Deal with CPUs that don't clear their LBRs on power-up. 4668 */ 4669 intel_pmu_lbr_reset(); 4670 4671 cpuc->lbr_sel = NULL; 4672 4673 if (x86_pmu.flags & PMU_FL_TFA) { 4674 WARN_ON_ONCE(cpuc->tfa_shadow); 4675 cpuc->tfa_shadow = ~0ULL; 4676 intel_set_tfa(cpuc, false); 4677 } 4678 4679 if (x86_pmu.version > 1) 4680 flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 4681 4682 /* 4683 * Disable perf metrics if any added CPU doesn't support it. 4684 * 4685 * Turn off the check for a hybrid architecture, because the 4686 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate 4687 * the architecture features. The perf metrics is a model-specific 4688 * feature for now. The corresponding bit should always be 0 on 4689 * a hybrid platform, e.g., Alder Lake. 4690 */ 4691 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) { 4692 union perf_capabilities perf_cap; 4693 4694 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); 4695 if (!perf_cap.perf_metrics) { 4696 x86_pmu.intel_cap.perf_metrics = 0; 4697 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); 4698 } 4699 } 4700 4701 if (!cpuc->shared_regs) 4702 return; 4703 4704 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 4705 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 4706 struct intel_shared_regs *pc; 4707 4708 pc = per_cpu(cpu_hw_events, i).shared_regs; 4709 if (pc && pc->core_id == core_id) { 4710 cpuc->kfree_on_online[0] = cpuc->shared_regs; 4711 cpuc->shared_regs = pc; 4712 break; 4713 } 4714 } 4715 cpuc->shared_regs->core_id = core_id; 4716 cpuc->shared_regs->refcnt++; 4717 } 4718 4719 if (x86_pmu.lbr_sel_map) 4720 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 4721 4722 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4723 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 4724 struct cpu_hw_events *sibling; 4725 struct intel_excl_cntrs *c; 4726 4727 sibling = &per_cpu(cpu_hw_events, i); 4728 c = sibling->excl_cntrs; 4729 if (c && c->core_id == core_id) { 4730 cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 4731 cpuc->excl_cntrs = c; 4732 if (!sibling->excl_thread_id) 4733 cpuc->excl_thread_id = 1; 4734 break; 4735 } 4736 } 4737 cpuc->excl_cntrs->core_id = core_id; 4738 cpuc->excl_cntrs->refcnt++; 4739 } 4740 } 4741 4742 static void free_excl_cntrs(struct cpu_hw_events *cpuc) 4743 { 4744 struct intel_excl_cntrs *c; 4745 4746 c = cpuc->excl_cntrs; 4747 if (c) { 4748 if (c->core_id == -1 || --c->refcnt == 0) 4749 kfree(c); 4750 cpuc->excl_cntrs = NULL; 4751 } 4752 4753 kfree(cpuc->constraint_list); 4754 cpuc->constraint_list = NULL; 4755 } 4756 4757 static void intel_pmu_cpu_dying(int cpu) 4758 { 4759 fini_debug_store_on_cpu(cpu); 4760 } 4761 4762 void intel_cpuc_finish(struct cpu_hw_events *cpuc) 4763 { 4764 struct intel_shared_regs *pc; 4765 4766 pc = cpuc->shared_regs; 4767 if (pc) { 4768 if (pc->core_id == -1 || --pc->refcnt == 0) 4769 kfree(pc); 4770 cpuc->shared_regs = NULL; 4771 } 4772 4773 free_excl_cntrs(cpuc); 4774 } 4775 4776 static void intel_pmu_cpu_dead(int cpu) 4777 { 4778 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4779 4780 intel_cpuc_finish(cpuc); 4781 4782 if (is_hybrid() && cpuc->pmu) 4783 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus); 4784 } 4785 4786 static void intel_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx, 4787 bool sched_in) 4788 { 4789 intel_pmu_pebs_sched_task(pmu_ctx, sched_in); 4790 intel_pmu_lbr_sched_task(pmu_ctx, sched_in); 4791 } 4792 4793 static void intel_pmu_swap_task_ctx(struct perf_event_pmu_context *prev_epc, 4794 struct perf_event_pmu_context *next_epc) 4795 { 4796 intel_pmu_lbr_swap_task_ctx(prev_epc, next_epc); 4797 } 4798 4799 static int intel_pmu_check_period(struct perf_event *event, u64 value) 4800 { 4801 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0; 4802 } 4803 4804 static void intel_aux_output_init(void) 4805 { 4806 /* Refer also intel_pmu_aux_output_match() */ 4807 if (x86_pmu.intel_cap.pebs_output_pt_available) 4808 x86_pmu.assign = intel_pmu_assign_event; 4809 } 4810 4811 static int intel_pmu_aux_output_match(struct perf_event *event) 4812 { 4813 /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */ 4814 if (!x86_pmu.intel_cap.pebs_output_pt_available) 4815 return 0; 4816 4817 return is_intel_pt_event(event); 4818 } 4819 4820 static void intel_pmu_filter(struct pmu *pmu, int cpu, bool *ret) 4821 { 4822 struct x86_hybrid_pmu *hpmu = hybrid_pmu(pmu); 4823 4824 *ret = !cpumask_test_cpu(cpu, &hpmu->supported_cpus); 4825 } 4826 4827 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 4828 4829 PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 4830 4831 PMU_FORMAT_ATTR(frontend, "config1:0-23"); 4832 4833 static struct attribute *intel_arch3_formats_attr[] = { 4834 &format_attr_event.attr, 4835 &format_attr_umask.attr, 4836 &format_attr_edge.attr, 4837 &format_attr_pc.attr, 4838 &format_attr_any.attr, 4839 &format_attr_inv.attr, 4840 &format_attr_cmask.attr, 4841 NULL, 4842 }; 4843 4844 static struct attribute *hsw_format_attr[] = { 4845 &format_attr_in_tx.attr, 4846 &format_attr_in_tx_cp.attr, 4847 &format_attr_offcore_rsp.attr, 4848 &format_attr_ldlat.attr, 4849 NULL 4850 }; 4851 4852 static struct attribute *nhm_format_attr[] = { 4853 &format_attr_offcore_rsp.attr, 4854 &format_attr_ldlat.attr, 4855 NULL 4856 }; 4857 4858 static struct attribute *slm_format_attr[] = { 4859 &format_attr_offcore_rsp.attr, 4860 NULL 4861 }; 4862 4863 static struct attribute *skl_format_attr[] = { 4864 &format_attr_frontend.attr, 4865 NULL, 4866 }; 4867 4868 static __initconst const struct x86_pmu core_pmu = { 4869 .name = "core", 4870 .handle_irq = x86_pmu_handle_irq, 4871 .disable_all = x86_pmu_disable_all, 4872 .enable_all = core_pmu_enable_all, 4873 .enable = core_pmu_enable_event, 4874 .disable = x86_pmu_disable_event, 4875 .hw_config = core_pmu_hw_config, 4876 .schedule_events = x86_schedule_events, 4877 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 4878 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 4879 .event_map = intel_pmu_event_map, 4880 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 4881 .apic = 1, 4882 .large_pebs_flags = LARGE_PEBS_FLAGS, 4883 4884 /* 4885 * Intel PMCs cannot be accessed sanely above 32-bit width, 4886 * so we install an artificial 1<<31 period regardless of 4887 * the generic event period: 4888 */ 4889 .max_period = (1ULL<<31) - 1, 4890 .get_event_constraints = intel_get_event_constraints, 4891 .put_event_constraints = intel_put_event_constraints, 4892 .event_constraints = intel_core_event_constraints, 4893 .guest_get_msrs = core_guest_get_msrs, 4894 .format_attrs = intel_arch_formats_attr, 4895 .events_sysfs_show = intel_event_sysfs_show, 4896 4897 /* 4898 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 4899 * together with PMU version 1 and thus be using core_pmu with 4900 * shared_regs. We need following callbacks here to allocate 4901 * it properly. 4902 */ 4903 .cpu_prepare = intel_pmu_cpu_prepare, 4904 .cpu_starting = intel_pmu_cpu_starting, 4905 .cpu_dying = intel_pmu_cpu_dying, 4906 .cpu_dead = intel_pmu_cpu_dead, 4907 4908 .check_period = intel_pmu_check_period, 4909 4910 .lbr_reset = intel_pmu_lbr_reset_64, 4911 .lbr_read = intel_pmu_lbr_read_64, 4912 .lbr_save = intel_pmu_lbr_save, 4913 .lbr_restore = intel_pmu_lbr_restore, 4914 }; 4915 4916 static __initconst const struct x86_pmu intel_pmu = { 4917 .name = "Intel", 4918 .handle_irq = intel_pmu_handle_irq, 4919 .disable_all = intel_pmu_disable_all, 4920 .enable_all = intel_pmu_enable_all, 4921 .enable = intel_pmu_enable_event, 4922 .disable = intel_pmu_disable_event, 4923 .add = intel_pmu_add_event, 4924 .del = intel_pmu_del_event, 4925 .read = intel_pmu_read_event, 4926 .set_period = intel_pmu_set_period, 4927 .update = intel_pmu_update, 4928 .hw_config = intel_pmu_hw_config, 4929 .schedule_events = x86_schedule_events, 4930 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 4931 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 4932 .event_map = intel_pmu_event_map, 4933 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 4934 .apic = 1, 4935 .large_pebs_flags = LARGE_PEBS_FLAGS, 4936 /* 4937 * Intel PMCs cannot be accessed sanely above 32 bit width, 4938 * so we install an artificial 1<<31 period regardless of 4939 * the generic event period: 4940 */ 4941 .max_period = (1ULL << 31) - 1, 4942 .get_event_constraints = intel_get_event_constraints, 4943 .put_event_constraints = intel_put_event_constraints, 4944 .pebs_aliases = intel_pebs_aliases_core2, 4945 4946 .format_attrs = intel_arch3_formats_attr, 4947 .events_sysfs_show = intel_event_sysfs_show, 4948 4949 .cpu_prepare = intel_pmu_cpu_prepare, 4950 .cpu_starting = intel_pmu_cpu_starting, 4951 .cpu_dying = intel_pmu_cpu_dying, 4952 .cpu_dead = intel_pmu_cpu_dead, 4953 4954 .guest_get_msrs = intel_guest_get_msrs, 4955 .sched_task = intel_pmu_sched_task, 4956 .swap_task_ctx = intel_pmu_swap_task_ctx, 4957 4958 .check_period = intel_pmu_check_period, 4959 4960 .aux_output_match = intel_pmu_aux_output_match, 4961 4962 .lbr_reset = intel_pmu_lbr_reset_64, 4963 .lbr_read = intel_pmu_lbr_read_64, 4964 .lbr_save = intel_pmu_lbr_save, 4965 .lbr_restore = intel_pmu_lbr_restore, 4966 4967 /* 4968 * SMM has access to all 4 rings and while traditionally SMM code only 4969 * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM. 4970 * 4971 * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction 4972 * between SMM or not, this results in what should be pure userspace 4973 * counters including SMM data. 4974 * 4975 * This is a clear privilege issue, therefore globally disable 4976 * counting SMM by default. 4977 */ 4978 .attr_freeze_on_smi = 1, 4979 }; 4980 4981 static __init void intel_clovertown_quirk(void) 4982 { 4983 /* 4984 * PEBS is unreliable due to: 4985 * 4986 * AJ67 - PEBS may experience CPL leaks 4987 * AJ68 - PEBS PMI may be delayed by one event 4988 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 4989 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 4990 * 4991 * AJ67 could be worked around by restricting the OS/USR flags. 4992 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 4993 * 4994 * AJ106 could possibly be worked around by not allowing LBR 4995 * usage from PEBS, including the fixup. 4996 * AJ68 could possibly be worked around by always programming 4997 * a pebs_event_reset[0] value and coping with the lost events. 4998 * 4999 * But taken together it might just make sense to not enable PEBS on 5000 * these chips. 5001 */ 5002 pr_warn("PEBS disabled due to CPU errata\n"); 5003 x86_pmu.pebs = 0; 5004 x86_pmu.pebs_constraints = NULL; 5005 } 5006 5007 static const struct x86_cpu_desc isolation_ucodes[] = { 5008 INTEL_CPU_DESC(INTEL_FAM6_HASWELL, 3, 0x0000001f), 5009 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e), 5010 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015), 5011 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037), 5012 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a), 5013 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL, 4, 0x00000023), 5014 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014), 5015 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 2, 0x00000010), 5016 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 3, 0x07000009), 5017 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 4, 0x0f000009), 5018 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 5, 0x0e000002), 5019 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 1, 0x0b000014), 5020 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021), 5021 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000), 5022 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 5, 0x00000000), 5023 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 6, 0x00000000), 5024 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 7, 0x00000000), 5025 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 11, 0x00000000), 5026 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L, 3, 0x0000007c), 5027 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE, 3, 0x0000007c), 5028 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 9, 0x0000004e), 5029 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 9, 0x0000004e), 5030 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 10, 0x0000004e), 5031 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 11, 0x0000004e), 5032 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 12, 0x0000004e), 5033 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 10, 0x0000004e), 5034 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 11, 0x0000004e), 5035 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 12, 0x0000004e), 5036 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 13, 0x0000004e), 5037 {} 5038 }; 5039 5040 static void intel_check_pebs_isolation(void) 5041 { 5042 x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes); 5043 } 5044 5045 static __init void intel_pebs_isolation_quirk(void) 5046 { 5047 WARN_ON_ONCE(x86_pmu.check_microcode); 5048 x86_pmu.check_microcode = intel_check_pebs_isolation; 5049 intel_check_pebs_isolation(); 5050 } 5051 5052 static const struct x86_cpu_desc pebs_ucodes[] = { 5053 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028), 5054 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618), 5055 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c), 5056 {} 5057 }; 5058 5059 static bool intel_snb_pebs_broken(void) 5060 { 5061 return !x86_cpu_has_min_microcode_rev(pebs_ucodes); 5062 } 5063 5064 static void intel_snb_check_microcode(void) 5065 { 5066 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken) 5067 return; 5068 5069 /* 5070 * Serialized by the microcode lock.. 5071 */ 5072 if (x86_pmu.pebs_broken) { 5073 pr_info("PEBS enabled due to microcode update\n"); 5074 x86_pmu.pebs_broken = 0; 5075 } else { 5076 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 5077 x86_pmu.pebs_broken = 1; 5078 } 5079 } 5080 5081 static bool is_lbr_from(unsigned long msr) 5082 { 5083 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 5084 5085 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 5086 } 5087 5088 /* 5089 * Under certain circumstances, access certain MSR may cause #GP. 5090 * The function tests if the input MSR can be safely accessed. 5091 */ 5092 static bool check_msr(unsigned long msr, u64 mask) 5093 { 5094 u64 val_old, val_new, val_tmp; 5095 5096 /* 5097 * Disable the check for real HW, so we don't 5098 * mess with potentially enabled registers: 5099 */ 5100 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 5101 return true; 5102 5103 /* 5104 * Read the current value, change it and read it back to see if it 5105 * matches, this is needed to detect certain hardware emulators 5106 * (qemu/kvm) that don't trap on the MSR access and always return 0s. 5107 */ 5108 if (rdmsrl_safe(msr, &val_old)) 5109 return false; 5110 5111 /* 5112 * Only change the bits which can be updated by wrmsrl. 5113 */ 5114 val_tmp = val_old ^ mask; 5115 5116 if (is_lbr_from(msr)) 5117 val_tmp = lbr_from_signext_quirk_wr(val_tmp); 5118 5119 if (wrmsrl_safe(msr, val_tmp) || 5120 rdmsrl_safe(msr, &val_new)) 5121 return false; 5122 5123 /* 5124 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value 5125 * should equal rdmsrl()'s even with the quirk. 5126 */ 5127 if (val_new != val_tmp) 5128 return false; 5129 5130 if (is_lbr_from(msr)) 5131 val_old = lbr_from_signext_quirk_wr(val_old); 5132 5133 /* Here it's sure that the MSR can be safely accessed. 5134 * Restore the old value and return. 5135 */ 5136 wrmsrl(msr, val_old); 5137 5138 return true; 5139 } 5140 5141 static __init void intel_sandybridge_quirk(void) 5142 { 5143 x86_pmu.check_microcode = intel_snb_check_microcode; 5144 cpus_read_lock(); 5145 intel_snb_check_microcode(); 5146 cpus_read_unlock(); 5147 } 5148 5149 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 5150 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 5151 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 5152 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 5153 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 5154 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 5155 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 5156 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 5157 }; 5158 5159 static __init void intel_arch_events_quirk(void) 5160 { 5161 int bit; 5162 5163 /* disable event that reported as not present by cpuid */ 5164 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 5165 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 5166 pr_warn("CPUID marked event: \'%s\' unavailable\n", 5167 intel_arch_events_map[bit].name); 5168 } 5169 } 5170 5171 static __init void intel_nehalem_quirk(void) 5172 { 5173 union cpuid10_ebx ebx; 5174 5175 ebx.full = x86_pmu.events_maskl; 5176 if (ebx.split.no_branch_misses_retired) { 5177 /* 5178 * Erratum AAJ80 detected, we work it around by using 5179 * the BR_MISP_EXEC.ANY event. This will over-count 5180 * branch-misses, but it's still much better than the 5181 * architectural event which is often completely bogus: 5182 */ 5183 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 5184 ebx.split.no_branch_misses_retired = 0; 5185 x86_pmu.events_maskl = ebx.full; 5186 pr_info("CPU erratum AAJ80 worked around\n"); 5187 } 5188 } 5189 5190 /* 5191 * enable software workaround for errata: 5192 * SNB: BJ122 5193 * IVB: BV98 5194 * HSW: HSD29 5195 * 5196 * Only needed when HT is enabled. However detecting 5197 * if HT is enabled is difficult (model specific). So instead, 5198 * we enable the workaround in the early boot, and verify if 5199 * it is needed in a later initcall phase once we have valid 5200 * topology information to check if HT is actually enabled 5201 */ 5202 static __init void intel_ht_bug(void) 5203 { 5204 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 5205 5206 x86_pmu.start_scheduling = intel_start_scheduling; 5207 x86_pmu.commit_scheduling = intel_commit_scheduling; 5208 x86_pmu.stop_scheduling = intel_stop_scheduling; 5209 } 5210 5211 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 5212 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 5213 5214 /* Haswell special events */ 5215 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 5216 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 5217 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 5218 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 5219 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 5220 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 5221 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 5222 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 5223 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 5224 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 5225 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 5226 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 5227 5228 static struct attribute *hsw_events_attrs[] = { 5229 EVENT_PTR(td_slots_issued), 5230 EVENT_PTR(td_slots_retired), 5231 EVENT_PTR(td_fetch_bubbles), 5232 EVENT_PTR(td_total_slots), 5233 EVENT_PTR(td_total_slots_scale), 5234 EVENT_PTR(td_recovery_bubbles), 5235 EVENT_PTR(td_recovery_bubbles_scale), 5236 NULL 5237 }; 5238 5239 static struct attribute *hsw_mem_events_attrs[] = { 5240 EVENT_PTR(mem_ld_hsw), 5241 EVENT_PTR(mem_st_hsw), 5242 NULL, 5243 }; 5244 5245 static struct attribute *hsw_tsx_events_attrs[] = { 5246 EVENT_PTR(tx_start), 5247 EVENT_PTR(tx_commit), 5248 EVENT_PTR(tx_abort), 5249 EVENT_PTR(tx_capacity), 5250 EVENT_PTR(tx_conflict), 5251 EVENT_PTR(el_start), 5252 EVENT_PTR(el_commit), 5253 EVENT_PTR(el_abort), 5254 EVENT_PTR(el_capacity), 5255 EVENT_PTR(el_conflict), 5256 EVENT_PTR(cycles_t), 5257 EVENT_PTR(cycles_ct), 5258 NULL 5259 }; 5260 5261 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80"); 5262 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2"); 5263 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80"); 5264 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2"); 5265 5266 static struct attribute *icl_events_attrs[] = { 5267 EVENT_PTR(mem_ld_hsw), 5268 EVENT_PTR(mem_st_hsw), 5269 NULL, 5270 }; 5271 5272 static struct attribute *icl_td_events_attrs[] = { 5273 EVENT_PTR(slots), 5274 EVENT_PTR(td_retiring), 5275 EVENT_PTR(td_bad_spec), 5276 EVENT_PTR(td_fe_bound), 5277 EVENT_PTR(td_be_bound), 5278 NULL, 5279 }; 5280 5281 static struct attribute *icl_tsx_events_attrs[] = { 5282 EVENT_PTR(tx_start), 5283 EVENT_PTR(tx_abort), 5284 EVENT_PTR(tx_commit), 5285 EVENT_PTR(tx_capacity_read), 5286 EVENT_PTR(tx_capacity_write), 5287 EVENT_PTR(tx_conflict), 5288 EVENT_PTR(el_start), 5289 EVENT_PTR(el_abort), 5290 EVENT_PTR(el_commit), 5291 EVENT_PTR(el_capacity_read), 5292 EVENT_PTR(el_capacity_write), 5293 EVENT_PTR(el_conflict), 5294 EVENT_PTR(cycles_t), 5295 EVENT_PTR(cycles_ct), 5296 NULL, 5297 }; 5298 5299 5300 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2"); 5301 EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82"); 5302 5303 static struct attribute *spr_events_attrs[] = { 5304 EVENT_PTR(mem_ld_hsw), 5305 EVENT_PTR(mem_st_spr), 5306 EVENT_PTR(mem_ld_aux), 5307 NULL, 5308 }; 5309 5310 static struct attribute *spr_td_events_attrs[] = { 5311 EVENT_PTR(slots), 5312 EVENT_PTR(td_retiring), 5313 EVENT_PTR(td_bad_spec), 5314 EVENT_PTR(td_fe_bound), 5315 EVENT_PTR(td_be_bound), 5316 EVENT_PTR(td_heavy_ops), 5317 EVENT_PTR(td_br_mispredict), 5318 EVENT_PTR(td_fetch_lat), 5319 EVENT_PTR(td_mem_bound), 5320 NULL, 5321 }; 5322 5323 static struct attribute *spr_tsx_events_attrs[] = { 5324 EVENT_PTR(tx_start), 5325 EVENT_PTR(tx_abort), 5326 EVENT_PTR(tx_commit), 5327 EVENT_PTR(tx_capacity_read), 5328 EVENT_PTR(tx_capacity_write), 5329 EVENT_PTR(tx_conflict), 5330 EVENT_PTR(cycles_t), 5331 EVENT_PTR(cycles_ct), 5332 NULL, 5333 }; 5334 5335 static ssize_t freeze_on_smi_show(struct device *cdev, 5336 struct device_attribute *attr, 5337 char *buf) 5338 { 5339 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 5340 } 5341 5342 static DEFINE_MUTEX(freeze_on_smi_mutex); 5343 5344 static ssize_t freeze_on_smi_store(struct device *cdev, 5345 struct device_attribute *attr, 5346 const char *buf, size_t count) 5347 { 5348 unsigned long val; 5349 ssize_t ret; 5350 5351 ret = kstrtoul(buf, 0, &val); 5352 if (ret) 5353 return ret; 5354 5355 if (val > 1) 5356 return -EINVAL; 5357 5358 mutex_lock(&freeze_on_smi_mutex); 5359 5360 if (x86_pmu.attr_freeze_on_smi == val) 5361 goto done; 5362 5363 x86_pmu.attr_freeze_on_smi = val; 5364 5365 cpus_read_lock(); 5366 on_each_cpu(flip_smm_bit, &val, 1); 5367 cpus_read_unlock(); 5368 done: 5369 mutex_unlock(&freeze_on_smi_mutex); 5370 5371 return count; 5372 } 5373 5374 static void update_tfa_sched(void *ignored) 5375 { 5376 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 5377 5378 /* 5379 * check if PMC3 is used 5380 * and if so force schedule out for all event types all contexts 5381 */ 5382 if (test_bit(3, cpuc->active_mask)) 5383 perf_pmu_resched(x86_get_pmu(smp_processor_id())); 5384 } 5385 5386 static ssize_t show_sysctl_tfa(struct device *cdev, 5387 struct device_attribute *attr, 5388 char *buf) 5389 { 5390 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort); 5391 } 5392 5393 static ssize_t set_sysctl_tfa(struct device *cdev, 5394 struct device_attribute *attr, 5395 const char *buf, size_t count) 5396 { 5397 bool val; 5398 ssize_t ret; 5399 5400 ret = kstrtobool(buf, &val); 5401 if (ret) 5402 return ret; 5403 5404 /* no change */ 5405 if (val == allow_tsx_force_abort) 5406 return count; 5407 5408 allow_tsx_force_abort = val; 5409 5410 cpus_read_lock(); 5411 on_each_cpu(update_tfa_sched, NULL, 1); 5412 cpus_read_unlock(); 5413 5414 return count; 5415 } 5416 5417 5418 static DEVICE_ATTR_RW(freeze_on_smi); 5419 5420 static ssize_t branches_show(struct device *cdev, 5421 struct device_attribute *attr, 5422 char *buf) 5423 { 5424 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); 5425 } 5426 5427 static DEVICE_ATTR_RO(branches); 5428 5429 static struct attribute *lbr_attrs[] = { 5430 &dev_attr_branches.attr, 5431 NULL 5432 }; 5433 5434 static char pmu_name_str[30]; 5435 5436 static ssize_t pmu_name_show(struct device *cdev, 5437 struct device_attribute *attr, 5438 char *buf) 5439 { 5440 return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str); 5441 } 5442 5443 static DEVICE_ATTR_RO(pmu_name); 5444 5445 static struct attribute *intel_pmu_caps_attrs[] = { 5446 &dev_attr_pmu_name.attr, 5447 NULL 5448 }; 5449 5450 static DEVICE_ATTR(allow_tsx_force_abort, 0644, 5451 show_sysctl_tfa, 5452 set_sysctl_tfa); 5453 5454 static struct attribute *intel_pmu_attrs[] = { 5455 &dev_attr_freeze_on_smi.attr, 5456 &dev_attr_allow_tsx_force_abort.attr, 5457 NULL, 5458 }; 5459 5460 static umode_t 5461 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5462 { 5463 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0; 5464 } 5465 5466 static umode_t 5467 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5468 { 5469 return x86_pmu.pebs ? attr->mode : 0; 5470 } 5471 5472 static umode_t 5473 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5474 { 5475 return x86_pmu.lbr_nr ? attr->mode : 0; 5476 } 5477 5478 static umode_t 5479 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5480 { 5481 return x86_pmu.version >= 2 ? attr->mode : 0; 5482 } 5483 5484 static umode_t 5485 default_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5486 { 5487 if (attr == &dev_attr_allow_tsx_force_abort.attr) 5488 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0; 5489 5490 return attr->mode; 5491 } 5492 5493 static struct attribute_group group_events_td = { 5494 .name = "events", 5495 }; 5496 5497 static struct attribute_group group_events_mem = { 5498 .name = "events", 5499 .is_visible = pebs_is_visible, 5500 }; 5501 5502 static struct attribute_group group_events_tsx = { 5503 .name = "events", 5504 .is_visible = tsx_is_visible, 5505 }; 5506 5507 static struct attribute_group group_caps_gen = { 5508 .name = "caps", 5509 .attrs = intel_pmu_caps_attrs, 5510 }; 5511 5512 static struct attribute_group group_caps_lbr = { 5513 .name = "caps", 5514 .attrs = lbr_attrs, 5515 .is_visible = lbr_is_visible, 5516 }; 5517 5518 static struct attribute_group group_format_extra = { 5519 .name = "format", 5520 .is_visible = exra_is_visible, 5521 }; 5522 5523 static struct attribute_group group_format_extra_skl = { 5524 .name = "format", 5525 .is_visible = exra_is_visible, 5526 }; 5527 5528 static struct attribute_group group_default = { 5529 .attrs = intel_pmu_attrs, 5530 .is_visible = default_is_visible, 5531 }; 5532 5533 static const struct attribute_group *attr_update[] = { 5534 &group_events_td, 5535 &group_events_mem, 5536 &group_events_tsx, 5537 &group_caps_gen, 5538 &group_caps_lbr, 5539 &group_format_extra, 5540 &group_format_extra_skl, 5541 &group_default, 5542 NULL, 5543 }; 5544 5545 EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big); 5546 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small); 5547 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small); 5548 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small); 5549 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small); 5550 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big); 5551 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big); 5552 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big); 5553 EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big); 5554 5555 static struct attribute *adl_hybrid_events_attrs[] = { 5556 EVENT_PTR(slots_adl), 5557 EVENT_PTR(td_retiring_adl), 5558 EVENT_PTR(td_bad_spec_adl), 5559 EVENT_PTR(td_fe_bound_adl), 5560 EVENT_PTR(td_be_bound_adl), 5561 EVENT_PTR(td_heavy_ops_adl), 5562 EVENT_PTR(td_br_mis_adl), 5563 EVENT_PTR(td_fetch_lat_adl), 5564 EVENT_PTR(td_mem_bound_adl), 5565 NULL, 5566 }; 5567 5568 /* Must be in IDX order */ 5569 EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small); 5570 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small); 5571 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big); 5572 5573 static struct attribute *adl_hybrid_mem_attrs[] = { 5574 EVENT_PTR(mem_ld_adl), 5575 EVENT_PTR(mem_st_adl), 5576 EVENT_PTR(mem_ld_aux_adl), 5577 NULL, 5578 }; 5579 5580 static struct attribute *mtl_hybrid_mem_attrs[] = { 5581 EVENT_PTR(mem_ld_adl), 5582 EVENT_PTR(mem_st_adl), 5583 NULL 5584 }; 5585 5586 EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big); 5587 EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big); 5588 EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big); 5589 EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big); 5590 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big); 5591 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big); 5592 EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big); 5593 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big); 5594 5595 static struct attribute *adl_hybrid_tsx_attrs[] = { 5596 EVENT_PTR(tx_start_adl), 5597 EVENT_PTR(tx_abort_adl), 5598 EVENT_PTR(tx_commit_adl), 5599 EVENT_PTR(tx_capacity_read_adl), 5600 EVENT_PTR(tx_capacity_write_adl), 5601 EVENT_PTR(tx_conflict_adl), 5602 EVENT_PTR(cycles_t_adl), 5603 EVENT_PTR(cycles_ct_adl), 5604 NULL, 5605 }; 5606 5607 FORMAT_ATTR_HYBRID(in_tx, hybrid_big); 5608 FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big); 5609 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small); 5610 FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small); 5611 FORMAT_ATTR_HYBRID(frontend, hybrid_big); 5612 5613 #define ADL_HYBRID_RTM_FORMAT_ATTR \ 5614 FORMAT_HYBRID_PTR(in_tx), \ 5615 FORMAT_HYBRID_PTR(in_tx_cp) 5616 5617 #define ADL_HYBRID_FORMAT_ATTR \ 5618 FORMAT_HYBRID_PTR(offcore_rsp), \ 5619 FORMAT_HYBRID_PTR(ldlat), \ 5620 FORMAT_HYBRID_PTR(frontend) 5621 5622 static struct attribute *adl_hybrid_extra_attr_rtm[] = { 5623 ADL_HYBRID_RTM_FORMAT_ATTR, 5624 ADL_HYBRID_FORMAT_ATTR, 5625 NULL 5626 }; 5627 5628 static struct attribute *adl_hybrid_extra_attr[] = { 5629 ADL_HYBRID_FORMAT_ATTR, 5630 NULL 5631 }; 5632 5633 PMU_FORMAT_ATTR_SHOW(snoop_rsp, "config1:0-63"); 5634 FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small); 5635 5636 static struct attribute *mtl_hybrid_extra_attr_rtm[] = { 5637 ADL_HYBRID_RTM_FORMAT_ATTR, 5638 ADL_HYBRID_FORMAT_ATTR, 5639 FORMAT_HYBRID_PTR(snoop_rsp), 5640 NULL 5641 }; 5642 5643 static struct attribute *mtl_hybrid_extra_attr[] = { 5644 ADL_HYBRID_FORMAT_ATTR, 5645 FORMAT_HYBRID_PTR(snoop_rsp), 5646 NULL 5647 }; 5648 5649 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr) 5650 { 5651 struct device *dev = kobj_to_dev(kobj); 5652 struct x86_hybrid_pmu *pmu = 5653 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5654 struct perf_pmu_events_hybrid_attr *pmu_attr = 5655 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr); 5656 5657 return pmu->cpu_type & pmu_attr->pmu_type; 5658 } 5659 5660 static umode_t hybrid_events_is_visible(struct kobject *kobj, 5661 struct attribute *attr, int i) 5662 { 5663 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0; 5664 } 5665 5666 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu) 5667 { 5668 int cpu = cpumask_first(&pmu->supported_cpus); 5669 5670 return (cpu >= nr_cpu_ids) ? -1 : cpu; 5671 } 5672 5673 static umode_t hybrid_tsx_is_visible(struct kobject *kobj, 5674 struct attribute *attr, int i) 5675 { 5676 struct device *dev = kobj_to_dev(kobj); 5677 struct x86_hybrid_pmu *pmu = 5678 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5679 int cpu = hybrid_find_supported_cpu(pmu); 5680 5681 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0; 5682 } 5683 5684 static umode_t hybrid_format_is_visible(struct kobject *kobj, 5685 struct attribute *attr, int i) 5686 { 5687 struct device *dev = kobj_to_dev(kobj); 5688 struct x86_hybrid_pmu *pmu = 5689 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5690 struct perf_pmu_format_hybrid_attr *pmu_attr = 5691 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr); 5692 int cpu = hybrid_find_supported_cpu(pmu); 5693 5694 return (cpu >= 0) && (pmu->cpu_type & pmu_attr->pmu_type) ? attr->mode : 0; 5695 } 5696 5697 static struct attribute_group hybrid_group_events_td = { 5698 .name = "events", 5699 .is_visible = hybrid_events_is_visible, 5700 }; 5701 5702 static struct attribute_group hybrid_group_events_mem = { 5703 .name = "events", 5704 .is_visible = hybrid_events_is_visible, 5705 }; 5706 5707 static struct attribute_group hybrid_group_events_tsx = { 5708 .name = "events", 5709 .is_visible = hybrid_tsx_is_visible, 5710 }; 5711 5712 static struct attribute_group hybrid_group_format_extra = { 5713 .name = "format", 5714 .is_visible = hybrid_format_is_visible, 5715 }; 5716 5717 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev, 5718 struct device_attribute *attr, 5719 char *buf) 5720 { 5721 struct x86_hybrid_pmu *pmu = 5722 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5723 5724 return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus); 5725 } 5726 5727 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL); 5728 static struct attribute *intel_hybrid_cpus_attrs[] = { 5729 &dev_attr_cpus.attr, 5730 NULL, 5731 }; 5732 5733 static struct attribute_group hybrid_group_cpus = { 5734 .attrs = intel_hybrid_cpus_attrs, 5735 }; 5736 5737 static const struct attribute_group *hybrid_attr_update[] = { 5738 &hybrid_group_events_td, 5739 &hybrid_group_events_mem, 5740 &hybrid_group_events_tsx, 5741 &group_caps_gen, 5742 &group_caps_lbr, 5743 &hybrid_group_format_extra, 5744 &group_default, 5745 &hybrid_group_cpus, 5746 NULL, 5747 }; 5748 5749 static struct attribute *empty_attrs; 5750 5751 static void intel_pmu_check_num_counters(int *num_counters, 5752 int *num_counters_fixed, 5753 u64 *intel_ctrl, u64 fixed_mask) 5754 { 5755 if (*num_counters > INTEL_PMC_MAX_GENERIC) { 5756 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 5757 *num_counters, INTEL_PMC_MAX_GENERIC); 5758 *num_counters = INTEL_PMC_MAX_GENERIC; 5759 } 5760 *intel_ctrl = (1ULL << *num_counters) - 1; 5761 5762 if (*num_counters_fixed > INTEL_PMC_MAX_FIXED) { 5763 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 5764 *num_counters_fixed, INTEL_PMC_MAX_FIXED); 5765 *num_counters_fixed = INTEL_PMC_MAX_FIXED; 5766 } 5767 5768 *intel_ctrl |= fixed_mask << INTEL_PMC_IDX_FIXED; 5769 } 5770 5771 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints, 5772 int num_counters, 5773 int num_counters_fixed, 5774 u64 intel_ctrl) 5775 { 5776 struct event_constraint *c; 5777 5778 if (!event_constraints) 5779 return; 5780 5781 /* 5782 * event on fixed counter2 (REF_CYCLES) only works on this 5783 * counter, so do not extend mask to generic counters 5784 */ 5785 for_each_event_constraint(c, event_constraints) { 5786 /* 5787 * Don't extend the topdown slots and metrics 5788 * events to the generic counters. 5789 */ 5790 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) { 5791 /* 5792 * Disable topdown slots and metrics events, 5793 * if slots event is not in CPUID. 5794 */ 5795 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl)) 5796 c->idxmsk64 = 0; 5797 c->weight = hweight64(c->idxmsk64); 5798 continue; 5799 } 5800 5801 if (c->cmask == FIXED_EVENT_FLAGS) { 5802 /* Disabled fixed counters which are not in CPUID */ 5803 c->idxmsk64 &= intel_ctrl; 5804 5805 /* 5806 * Don't extend the pseudo-encoding to the 5807 * generic counters 5808 */ 5809 if (!use_fixed_pseudo_encoding(c->code)) 5810 c->idxmsk64 |= (1ULL << num_counters) - 1; 5811 } 5812 c->idxmsk64 &= 5813 ~(~0ULL << (INTEL_PMC_IDX_FIXED + num_counters_fixed)); 5814 c->weight = hweight64(c->idxmsk64); 5815 } 5816 } 5817 5818 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs) 5819 { 5820 struct extra_reg *er; 5821 5822 /* 5823 * Access extra MSR may cause #GP under certain circumstances. 5824 * E.g. KVM doesn't support offcore event 5825 * Check all extra_regs here. 5826 */ 5827 if (!extra_regs) 5828 return; 5829 5830 for (er = extra_regs; er->msr; er++) { 5831 er->extra_msr_access = check_msr(er->msr, 0x11UL); 5832 /* Disable LBR select mapping */ 5833 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 5834 x86_pmu.lbr_sel_map = NULL; 5835 } 5836 } 5837 5838 static void intel_pmu_check_hybrid_pmus(u64 fixed_mask) 5839 { 5840 struct x86_hybrid_pmu *pmu; 5841 int i; 5842 5843 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { 5844 pmu = &x86_pmu.hybrid_pmu[i]; 5845 5846 intel_pmu_check_num_counters(&pmu->num_counters, 5847 &pmu->num_counters_fixed, 5848 &pmu->intel_ctrl, 5849 fixed_mask); 5850 5851 if (pmu->intel_cap.perf_metrics) { 5852 pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 5853 pmu->intel_ctrl |= INTEL_PMC_MSK_FIXED_SLOTS; 5854 } 5855 5856 if (pmu->intel_cap.pebs_output_pt_available) 5857 pmu->pmu.capabilities |= PERF_PMU_CAP_AUX_OUTPUT; 5858 5859 intel_pmu_check_event_constraints(pmu->event_constraints, 5860 pmu->num_counters, 5861 pmu->num_counters_fixed, 5862 pmu->intel_ctrl); 5863 5864 intel_pmu_check_extra_regs(pmu->extra_regs); 5865 } 5866 } 5867 5868 static __always_inline bool is_mtl(u8 x86_model) 5869 { 5870 return (x86_model == INTEL_FAM6_METEORLAKE) || 5871 (x86_model == INTEL_FAM6_METEORLAKE_L); 5872 } 5873 5874 __init int intel_pmu_init(void) 5875 { 5876 struct attribute **extra_skl_attr = &empty_attrs; 5877 struct attribute **extra_attr = &empty_attrs; 5878 struct attribute **td_attr = &empty_attrs; 5879 struct attribute **mem_attr = &empty_attrs; 5880 struct attribute **tsx_attr = &empty_attrs; 5881 union cpuid10_edx edx; 5882 union cpuid10_eax eax; 5883 union cpuid10_ebx ebx; 5884 unsigned int fixed_mask; 5885 bool pmem = false; 5886 int version, i; 5887 char *name; 5888 struct x86_hybrid_pmu *pmu; 5889 5890 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 5891 switch (boot_cpu_data.x86) { 5892 case 0x6: 5893 return p6_pmu_init(); 5894 case 0xb: 5895 return knc_pmu_init(); 5896 case 0xf: 5897 return p4_pmu_init(); 5898 } 5899 return -ENODEV; 5900 } 5901 5902 /* 5903 * Check whether the Architectural PerfMon supports 5904 * Branch Misses Retired hw_event or not. 5905 */ 5906 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full); 5907 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 5908 return -ENODEV; 5909 5910 version = eax.split.version_id; 5911 if (version < 2) 5912 x86_pmu = core_pmu; 5913 else 5914 x86_pmu = intel_pmu; 5915 5916 x86_pmu.version = version; 5917 x86_pmu.num_counters = eax.split.num_counters; 5918 x86_pmu.cntval_bits = eax.split.bit_width; 5919 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 5920 5921 x86_pmu.events_maskl = ebx.full; 5922 x86_pmu.events_mask_len = eax.split.mask_length; 5923 5924 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); 5925 x86_pmu.pebs_capable = PEBS_COUNTER_MASK; 5926 5927 /* 5928 * Quirk: v2 perfmon does not report fixed-purpose events, so 5929 * assume at least 3 events, when not running in a hypervisor: 5930 */ 5931 if (version > 1 && version < 5) { 5932 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 5933 5934 x86_pmu.num_counters_fixed = 5935 max((int)edx.split.num_counters_fixed, assume); 5936 5937 fixed_mask = (1L << x86_pmu.num_counters_fixed) - 1; 5938 } else if (version >= 5) 5939 x86_pmu.num_counters_fixed = fls(fixed_mask); 5940 5941 if (boot_cpu_has(X86_FEATURE_PDCM)) { 5942 u64 capabilities; 5943 5944 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); 5945 x86_pmu.intel_cap.capabilities = capabilities; 5946 } 5947 5948 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) { 5949 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32; 5950 x86_pmu.lbr_read = intel_pmu_lbr_read_32; 5951 } 5952 5953 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) 5954 intel_pmu_arch_lbr_init(); 5955 5956 intel_ds_init(); 5957 5958 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 5959 5960 if (version >= 5) { 5961 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated; 5962 if (x86_pmu.intel_cap.anythread_deprecated) 5963 pr_cont(" AnyThread deprecated, "); 5964 } 5965 5966 /* 5967 * Install the hw-cache-events table: 5968 */ 5969 switch (boot_cpu_data.x86_model) { 5970 case INTEL_FAM6_CORE_YONAH: 5971 pr_cont("Core events, "); 5972 name = "core"; 5973 break; 5974 5975 case INTEL_FAM6_CORE2_MEROM: 5976 x86_add_quirk(intel_clovertown_quirk); 5977 fallthrough; 5978 5979 case INTEL_FAM6_CORE2_MEROM_L: 5980 case INTEL_FAM6_CORE2_PENRYN: 5981 case INTEL_FAM6_CORE2_DUNNINGTON: 5982 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 5983 sizeof(hw_cache_event_ids)); 5984 5985 intel_pmu_lbr_init_core(); 5986 5987 x86_pmu.event_constraints = intel_core2_event_constraints; 5988 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 5989 pr_cont("Core2 events, "); 5990 name = "core2"; 5991 break; 5992 5993 case INTEL_FAM6_NEHALEM: 5994 case INTEL_FAM6_NEHALEM_EP: 5995 case INTEL_FAM6_NEHALEM_EX: 5996 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 5997 sizeof(hw_cache_event_ids)); 5998 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 5999 sizeof(hw_cache_extra_regs)); 6000 6001 intel_pmu_lbr_init_nhm(); 6002 6003 x86_pmu.event_constraints = intel_nehalem_event_constraints; 6004 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 6005 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 6006 x86_pmu.extra_regs = intel_nehalem_extra_regs; 6007 x86_pmu.limit_period = nhm_limit_period; 6008 6009 mem_attr = nhm_mem_events_attrs; 6010 6011 /* UOPS_ISSUED.STALLED_CYCLES */ 6012 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6013 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6014 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 6015 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 6016 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 6017 6018 intel_pmu_pebs_data_source_nhm(); 6019 x86_add_quirk(intel_nehalem_quirk); 6020 x86_pmu.pebs_no_tlb = 1; 6021 extra_attr = nhm_format_attr; 6022 6023 pr_cont("Nehalem events, "); 6024 name = "nehalem"; 6025 break; 6026 6027 case INTEL_FAM6_ATOM_BONNELL: 6028 case INTEL_FAM6_ATOM_BONNELL_MID: 6029 case INTEL_FAM6_ATOM_SALTWELL: 6030 case INTEL_FAM6_ATOM_SALTWELL_MID: 6031 case INTEL_FAM6_ATOM_SALTWELL_TABLET: 6032 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 6033 sizeof(hw_cache_event_ids)); 6034 6035 intel_pmu_lbr_init_atom(); 6036 6037 x86_pmu.event_constraints = intel_gen_event_constraints; 6038 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 6039 x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 6040 pr_cont("Atom events, "); 6041 name = "bonnell"; 6042 break; 6043 6044 case INTEL_FAM6_ATOM_SILVERMONT: 6045 case INTEL_FAM6_ATOM_SILVERMONT_D: 6046 case INTEL_FAM6_ATOM_SILVERMONT_MID: 6047 case INTEL_FAM6_ATOM_AIRMONT: 6048 case INTEL_FAM6_ATOM_AIRMONT_MID: 6049 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 6050 sizeof(hw_cache_event_ids)); 6051 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 6052 sizeof(hw_cache_extra_regs)); 6053 6054 intel_pmu_lbr_init_slm(); 6055 6056 x86_pmu.event_constraints = intel_slm_event_constraints; 6057 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 6058 x86_pmu.extra_regs = intel_slm_extra_regs; 6059 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6060 td_attr = slm_events_attrs; 6061 extra_attr = slm_format_attr; 6062 pr_cont("Silvermont events, "); 6063 name = "silvermont"; 6064 break; 6065 6066 case INTEL_FAM6_ATOM_GOLDMONT: 6067 case INTEL_FAM6_ATOM_GOLDMONT_D: 6068 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 6069 sizeof(hw_cache_event_ids)); 6070 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 6071 sizeof(hw_cache_extra_regs)); 6072 6073 intel_pmu_lbr_init_skl(); 6074 6075 x86_pmu.event_constraints = intel_slm_event_constraints; 6076 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 6077 x86_pmu.extra_regs = intel_glm_extra_regs; 6078 /* 6079 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 6080 * for precise cycles. 6081 * :pp is identical to :ppp 6082 */ 6083 x86_pmu.pebs_aliases = NULL; 6084 x86_pmu.pebs_prec_dist = true; 6085 x86_pmu.lbr_pt_coexist = true; 6086 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6087 td_attr = glm_events_attrs; 6088 extra_attr = slm_format_attr; 6089 pr_cont("Goldmont events, "); 6090 name = "goldmont"; 6091 break; 6092 6093 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 6094 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 6095 sizeof(hw_cache_event_ids)); 6096 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 6097 sizeof(hw_cache_extra_regs)); 6098 6099 intel_pmu_lbr_init_skl(); 6100 6101 x86_pmu.event_constraints = intel_slm_event_constraints; 6102 x86_pmu.extra_regs = intel_glm_extra_regs; 6103 /* 6104 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 6105 * for precise cycles. 6106 */ 6107 x86_pmu.pebs_aliases = NULL; 6108 x86_pmu.pebs_prec_dist = true; 6109 x86_pmu.lbr_pt_coexist = true; 6110 x86_pmu.pebs_capable = ~0ULL; 6111 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6112 x86_pmu.flags |= PMU_FL_PEBS_ALL; 6113 x86_pmu.get_event_constraints = glp_get_event_constraints; 6114 td_attr = glm_events_attrs; 6115 /* Goldmont Plus has 4-wide pipeline */ 6116 event_attr_td_total_slots_scale_glm.event_str = "4"; 6117 extra_attr = slm_format_attr; 6118 pr_cont("Goldmont plus events, "); 6119 name = "goldmont_plus"; 6120 break; 6121 6122 case INTEL_FAM6_ATOM_TREMONT_D: 6123 case INTEL_FAM6_ATOM_TREMONT: 6124 case INTEL_FAM6_ATOM_TREMONT_L: 6125 x86_pmu.late_ack = true; 6126 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 6127 sizeof(hw_cache_event_ids)); 6128 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 6129 sizeof(hw_cache_extra_regs)); 6130 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6131 6132 intel_pmu_lbr_init_skl(); 6133 6134 x86_pmu.event_constraints = intel_slm_event_constraints; 6135 x86_pmu.extra_regs = intel_tnt_extra_regs; 6136 /* 6137 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 6138 * for precise cycles. 6139 */ 6140 x86_pmu.pebs_aliases = NULL; 6141 x86_pmu.pebs_prec_dist = true; 6142 x86_pmu.lbr_pt_coexist = true; 6143 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6144 x86_pmu.get_event_constraints = tnt_get_event_constraints; 6145 td_attr = tnt_events_attrs; 6146 extra_attr = slm_format_attr; 6147 pr_cont("Tremont events, "); 6148 name = "Tremont"; 6149 break; 6150 6151 case INTEL_FAM6_ALDERLAKE_N: 6152 x86_pmu.mid_ack = true; 6153 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 6154 sizeof(hw_cache_event_ids)); 6155 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 6156 sizeof(hw_cache_extra_regs)); 6157 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6158 6159 x86_pmu.event_constraints = intel_slm_event_constraints; 6160 x86_pmu.pebs_constraints = intel_grt_pebs_event_constraints; 6161 x86_pmu.extra_regs = intel_grt_extra_regs; 6162 6163 x86_pmu.pebs_aliases = NULL; 6164 x86_pmu.pebs_prec_dist = true; 6165 x86_pmu.pebs_block = true; 6166 x86_pmu.lbr_pt_coexist = true; 6167 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6168 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6169 6170 intel_pmu_pebs_data_source_grt(); 6171 x86_pmu.pebs_latency_data = adl_latency_data_small; 6172 x86_pmu.get_event_constraints = tnt_get_event_constraints; 6173 x86_pmu.limit_period = spr_limit_period; 6174 td_attr = tnt_events_attrs; 6175 mem_attr = grt_mem_attrs; 6176 extra_attr = nhm_format_attr; 6177 pr_cont("Gracemont events, "); 6178 name = "gracemont"; 6179 break; 6180 6181 case INTEL_FAM6_WESTMERE: 6182 case INTEL_FAM6_WESTMERE_EP: 6183 case INTEL_FAM6_WESTMERE_EX: 6184 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 6185 sizeof(hw_cache_event_ids)); 6186 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 6187 sizeof(hw_cache_extra_regs)); 6188 6189 intel_pmu_lbr_init_nhm(); 6190 6191 x86_pmu.event_constraints = intel_westmere_event_constraints; 6192 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 6193 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 6194 x86_pmu.extra_regs = intel_westmere_extra_regs; 6195 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6196 6197 mem_attr = nhm_mem_events_attrs; 6198 6199 /* UOPS_ISSUED.STALLED_CYCLES */ 6200 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6201 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6202 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 6203 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 6204 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 6205 6206 intel_pmu_pebs_data_source_nhm(); 6207 extra_attr = nhm_format_attr; 6208 pr_cont("Westmere events, "); 6209 name = "westmere"; 6210 break; 6211 6212 case INTEL_FAM6_SANDYBRIDGE: 6213 case INTEL_FAM6_SANDYBRIDGE_X: 6214 x86_add_quirk(intel_sandybridge_quirk); 6215 x86_add_quirk(intel_ht_bug); 6216 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 6217 sizeof(hw_cache_event_ids)); 6218 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 6219 sizeof(hw_cache_extra_regs)); 6220 6221 intel_pmu_lbr_init_snb(); 6222 6223 x86_pmu.event_constraints = intel_snb_event_constraints; 6224 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 6225 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 6226 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X) 6227 x86_pmu.extra_regs = intel_snbep_extra_regs; 6228 else 6229 x86_pmu.extra_regs = intel_snb_extra_regs; 6230 6231 6232 /* all extra regs are per-cpu when HT is on */ 6233 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6234 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6235 6236 td_attr = snb_events_attrs; 6237 mem_attr = snb_mem_events_attrs; 6238 6239 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 6240 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6241 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6242 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 6243 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 6244 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 6245 6246 extra_attr = nhm_format_attr; 6247 6248 pr_cont("SandyBridge events, "); 6249 name = "sandybridge"; 6250 break; 6251 6252 case INTEL_FAM6_IVYBRIDGE: 6253 case INTEL_FAM6_IVYBRIDGE_X: 6254 x86_add_quirk(intel_ht_bug); 6255 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 6256 sizeof(hw_cache_event_ids)); 6257 /* dTLB-load-misses on IVB is different than SNB */ 6258 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 6259 6260 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 6261 sizeof(hw_cache_extra_regs)); 6262 6263 intel_pmu_lbr_init_snb(); 6264 6265 x86_pmu.event_constraints = intel_ivb_event_constraints; 6266 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 6267 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 6268 x86_pmu.pebs_prec_dist = true; 6269 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X) 6270 x86_pmu.extra_regs = intel_snbep_extra_regs; 6271 else 6272 x86_pmu.extra_regs = intel_snb_extra_regs; 6273 /* all extra regs are per-cpu when HT is on */ 6274 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6275 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6276 6277 td_attr = snb_events_attrs; 6278 mem_attr = snb_mem_events_attrs; 6279 6280 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 6281 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6282 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6283 6284 extra_attr = nhm_format_attr; 6285 6286 pr_cont("IvyBridge events, "); 6287 name = "ivybridge"; 6288 break; 6289 6290 6291 case INTEL_FAM6_HASWELL: 6292 case INTEL_FAM6_HASWELL_X: 6293 case INTEL_FAM6_HASWELL_L: 6294 case INTEL_FAM6_HASWELL_G: 6295 x86_add_quirk(intel_ht_bug); 6296 x86_add_quirk(intel_pebs_isolation_quirk); 6297 x86_pmu.late_ack = true; 6298 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6299 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6300 6301 intel_pmu_lbr_init_hsw(); 6302 6303 x86_pmu.event_constraints = intel_hsw_event_constraints; 6304 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 6305 x86_pmu.extra_regs = intel_snbep_extra_regs; 6306 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 6307 x86_pmu.pebs_prec_dist = true; 6308 /* all extra regs are per-cpu when HT is on */ 6309 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6310 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6311 6312 x86_pmu.hw_config = hsw_hw_config; 6313 x86_pmu.get_event_constraints = hsw_get_event_constraints; 6314 x86_pmu.lbr_double_abort = true; 6315 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6316 hsw_format_attr : nhm_format_attr; 6317 td_attr = hsw_events_attrs; 6318 mem_attr = hsw_mem_events_attrs; 6319 tsx_attr = hsw_tsx_events_attrs; 6320 pr_cont("Haswell events, "); 6321 name = "haswell"; 6322 break; 6323 6324 case INTEL_FAM6_BROADWELL: 6325 case INTEL_FAM6_BROADWELL_D: 6326 case INTEL_FAM6_BROADWELL_G: 6327 case INTEL_FAM6_BROADWELL_X: 6328 x86_add_quirk(intel_pebs_isolation_quirk); 6329 x86_pmu.late_ack = true; 6330 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6331 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6332 6333 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 6334 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 6335 BDW_L3_MISS|HSW_SNOOP_DRAM; 6336 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 6337 HSW_SNOOP_DRAM; 6338 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 6339 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 6340 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 6341 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 6342 6343 intel_pmu_lbr_init_hsw(); 6344 6345 x86_pmu.event_constraints = intel_bdw_event_constraints; 6346 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 6347 x86_pmu.extra_regs = intel_snbep_extra_regs; 6348 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 6349 x86_pmu.pebs_prec_dist = true; 6350 /* all extra regs are per-cpu when HT is on */ 6351 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6352 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6353 6354 x86_pmu.hw_config = hsw_hw_config; 6355 x86_pmu.get_event_constraints = hsw_get_event_constraints; 6356 x86_pmu.limit_period = bdw_limit_period; 6357 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6358 hsw_format_attr : nhm_format_attr; 6359 td_attr = hsw_events_attrs; 6360 mem_attr = hsw_mem_events_attrs; 6361 tsx_attr = hsw_tsx_events_attrs; 6362 pr_cont("Broadwell events, "); 6363 name = "broadwell"; 6364 break; 6365 6366 case INTEL_FAM6_XEON_PHI_KNL: 6367 case INTEL_FAM6_XEON_PHI_KNM: 6368 memcpy(hw_cache_event_ids, 6369 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6370 memcpy(hw_cache_extra_regs, 6371 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6372 intel_pmu_lbr_init_knl(); 6373 6374 x86_pmu.event_constraints = intel_slm_event_constraints; 6375 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 6376 x86_pmu.extra_regs = intel_knl_extra_regs; 6377 6378 /* all extra regs are per-cpu when HT is on */ 6379 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6380 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6381 extra_attr = slm_format_attr; 6382 pr_cont("Knights Landing/Mill events, "); 6383 name = "knights-landing"; 6384 break; 6385 6386 case INTEL_FAM6_SKYLAKE_X: 6387 pmem = true; 6388 fallthrough; 6389 case INTEL_FAM6_SKYLAKE_L: 6390 case INTEL_FAM6_SKYLAKE: 6391 case INTEL_FAM6_KABYLAKE_L: 6392 case INTEL_FAM6_KABYLAKE: 6393 case INTEL_FAM6_COMETLAKE_L: 6394 case INTEL_FAM6_COMETLAKE: 6395 x86_add_quirk(intel_pebs_isolation_quirk); 6396 x86_pmu.late_ack = true; 6397 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6398 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6399 intel_pmu_lbr_init_skl(); 6400 6401 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 6402 event_attr_td_recovery_bubbles.event_str_noht = 6403 "event=0xd,umask=0x1,cmask=1"; 6404 event_attr_td_recovery_bubbles.event_str_ht = 6405 "event=0xd,umask=0x1,cmask=1,any=1"; 6406 6407 x86_pmu.event_constraints = intel_skl_event_constraints; 6408 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 6409 x86_pmu.extra_regs = intel_skl_extra_regs; 6410 x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 6411 x86_pmu.pebs_prec_dist = true; 6412 /* all extra regs are per-cpu when HT is on */ 6413 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6414 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6415 6416 x86_pmu.hw_config = hsw_hw_config; 6417 x86_pmu.get_event_constraints = hsw_get_event_constraints; 6418 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6419 hsw_format_attr : nhm_format_attr; 6420 extra_skl_attr = skl_format_attr; 6421 td_attr = hsw_events_attrs; 6422 mem_attr = hsw_mem_events_attrs; 6423 tsx_attr = hsw_tsx_events_attrs; 6424 intel_pmu_pebs_data_source_skl(pmem); 6425 6426 /* 6427 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default. 6428 * TSX force abort hooks are not required on these systems. Only deploy 6429 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT. 6430 */ 6431 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) && 6432 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) { 6433 x86_pmu.flags |= PMU_FL_TFA; 6434 x86_pmu.get_event_constraints = tfa_get_event_constraints; 6435 x86_pmu.enable_all = intel_tfa_pmu_enable_all; 6436 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling; 6437 } 6438 6439 pr_cont("Skylake events, "); 6440 name = "skylake"; 6441 break; 6442 6443 case INTEL_FAM6_ICELAKE_X: 6444 case INTEL_FAM6_ICELAKE_D: 6445 x86_pmu.pebs_ept = 1; 6446 pmem = true; 6447 fallthrough; 6448 case INTEL_FAM6_ICELAKE_L: 6449 case INTEL_FAM6_ICELAKE: 6450 case INTEL_FAM6_TIGERLAKE_L: 6451 case INTEL_FAM6_TIGERLAKE: 6452 case INTEL_FAM6_ROCKETLAKE: 6453 x86_pmu.late_ack = true; 6454 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6455 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6456 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6457 intel_pmu_lbr_init_skl(); 6458 6459 x86_pmu.event_constraints = intel_icl_event_constraints; 6460 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints; 6461 x86_pmu.extra_regs = intel_icl_extra_regs; 6462 x86_pmu.pebs_aliases = NULL; 6463 x86_pmu.pebs_prec_dist = true; 6464 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6465 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6466 6467 x86_pmu.hw_config = hsw_hw_config; 6468 x86_pmu.get_event_constraints = icl_get_event_constraints; 6469 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6470 hsw_format_attr : nhm_format_attr; 6471 extra_skl_attr = skl_format_attr; 6472 mem_attr = icl_events_attrs; 6473 td_attr = icl_td_events_attrs; 6474 tsx_attr = icl_tsx_events_attrs; 6475 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6476 x86_pmu.lbr_pt_coexist = true; 6477 intel_pmu_pebs_data_source_skl(pmem); 6478 x86_pmu.num_topdown_events = 4; 6479 static_call_update(intel_pmu_update_topdown_event, 6480 &icl_update_topdown_event); 6481 static_call_update(intel_pmu_set_topdown_event_period, 6482 &icl_set_topdown_event_period); 6483 pr_cont("Icelake events, "); 6484 name = "icelake"; 6485 break; 6486 6487 case INTEL_FAM6_SAPPHIRERAPIDS_X: 6488 case INTEL_FAM6_EMERALDRAPIDS_X: 6489 pmem = true; 6490 x86_pmu.late_ack = true; 6491 memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6492 memcpy(hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6493 6494 x86_pmu.event_constraints = intel_spr_event_constraints; 6495 x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints; 6496 x86_pmu.extra_regs = intel_spr_extra_regs; 6497 x86_pmu.limit_period = spr_limit_period; 6498 x86_pmu.pebs_aliases = NULL; 6499 x86_pmu.pebs_prec_dist = true; 6500 x86_pmu.pebs_block = true; 6501 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6502 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6503 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6504 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 6505 6506 x86_pmu.hw_config = hsw_hw_config; 6507 x86_pmu.get_event_constraints = spr_get_event_constraints; 6508 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6509 hsw_format_attr : nhm_format_attr; 6510 extra_skl_attr = skl_format_attr; 6511 mem_attr = spr_events_attrs; 6512 td_attr = spr_td_events_attrs; 6513 tsx_attr = spr_tsx_events_attrs; 6514 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6515 x86_pmu.lbr_pt_coexist = true; 6516 intel_pmu_pebs_data_source_skl(pmem); 6517 x86_pmu.num_topdown_events = 8; 6518 static_call_update(intel_pmu_update_topdown_event, 6519 &icl_update_topdown_event); 6520 static_call_update(intel_pmu_set_topdown_event_period, 6521 &icl_set_topdown_event_period); 6522 pr_cont("Sapphire Rapids events, "); 6523 name = "sapphire_rapids"; 6524 break; 6525 6526 case INTEL_FAM6_ALDERLAKE: 6527 case INTEL_FAM6_ALDERLAKE_L: 6528 case INTEL_FAM6_RAPTORLAKE: 6529 case INTEL_FAM6_RAPTORLAKE_P: 6530 case INTEL_FAM6_RAPTORLAKE_S: 6531 case INTEL_FAM6_METEORLAKE: 6532 case INTEL_FAM6_METEORLAKE_L: 6533 /* 6534 * Alder Lake has 2 types of CPU, core and atom. 6535 * 6536 * Initialize the common PerfMon capabilities here. 6537 */ 6538 x86_pmu.hybrid_pmu = kcalloc(X86_HYBRID_NUM_PMUS, 6539 sizeof(struct x86_hybrid_pmu), 6540 GFP_KERNEL); 6541 if (!x86_pmu.hybrid_pmu) 6542 return -ENOMEM; 6543 static_branch_enable(&perf_is_hybrid); 6544 x86_pmu.num_hybrid_pmus = X86_HYBRID_NUM_PMUS; 6545 6546 x86_pmu.pebs_aliases = NULL; 6547 x86_pmu.pebs_prec_dist = true; 6548 x86_pmu.pebs_block = true; 6549 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6550 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6551 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6552 x86_pmu.lbr_pt_coexist = true; 6553 x86_pmu.pebs_latency_data = adl_latency_data_small; 6554 x86_pmu.num_topdown_events = 8; 6555 static_call_update(intel_pmu_update_topdown_event, 6556 &adl_update_topdown_event); 6557 static_call_update(intel_pmu_set_topdown_event_period, 6558 &adl_set_topdown_event_period); 6559 6560 x86_pmu.filter = intel_pmu_filter; 6561 x86_pmu.get_event_constraints = adl_get_event_constraints; 6562 x86_pmu.hw_config = adl_hw_config; 6563 x86_pmu.limit_period = spr_limit_period; 6564 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type; 6565 /* 6566 * The rtm_abort_event is used to check whether to enable GPRs 6567 * for the RTM abort event. Atom doesn't have the RTM abort 6568 * event. There is no harmful to set it in the common 6569 * x86_pmu.rtm_abort_event. 6570 */ 6571 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6572 6573 td_attr = adl_hybrid_events_attrs; 6574 mem_attr = adl_hybrid_mem_attrs; 6575 tsx_attr = adl_hybrid_tsx_attrs; 6576 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6577 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr; 6578 6579 /* Initialize big core specific PerfMon capabilities.*/ 6580 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 6581 pmu->name = "cpu_core"; 6582 pmu->cpu_type = hybrid_big; 6583 pmu->late_ack = true; 6584 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) { 6585 pmu->num_counters = x86_pmu.num_counters + 2; 6586 pmu->num_counters_fixed = x86_pmu.num_counters_fixed + 1; 6587 } else { 6588 pmu->num_counters = x86_pmu.num_counters; 6589 pmu->num_counters_fixed = x86_pmu.num_counters_fixed; 6590 } 6591 6592 /* 6593 * Quirk: For some Alder Lake machine, when all E-cores are disabled in 6594 * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However, 6595 * the X86_FEATURE_HYBRID_CPU is still set. The above codes will 6596 * mistakenly add extra counters for P-cores. Correct the number of 6597 * counters here. 6598 */ 6599 if ((pmu->num_counters > 8) || (pmu->num_counters_fixed > 4)) { 6600 pmu->num_counters = x86_pmu.num_counters; 6601 pmu->num_counters_fixed = x86_pmu.num_counters_fixed; 6602 } 6603 6604 pmu->max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, pmu->num_counters); 6605 pmu->unconstrained = (struct event_constraint) 6606 __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1, 6607 0, pmu->num_counters, 0, 0); 6608 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 6609 pmu->intel_cap.perf_metrics = 1; 6610 pmu->intel_cap.pebs_output_pt_available = 0; 6611 6612 memcpy(pmu->hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids)); 6613 memcpy(pmu->hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs)); 6614 pmu->event_constraints = intel_spr_event_constraints; 6615 pmu->pebs_constraints = intel_spr_pebs_event_constraints; 6616 pmu->extra_regs = intel_spr_extra_regs; 6617 6618 /* Initialize Atom core specific PerfMon capabilities.*/ 6619 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 6620 pmu->name = "cpu_atom"; 6621 pmu->cpu_type = hybrid_small; 6622 pmu->mid_ack = true; 6623 pmu->num_counters = x86_pmu.num_counters; 6624 pmu->num_counters_fixed = x86_pmu.num_counters_fixed; 6625 pmu->max_pebs_events = x86_pmu.max_pebs_events; 6626 pmu->unconstrained = (struct event_constraint) 6627 __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1, 6628 0, pmu->num_counters, 0, 0); 6629 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 6630 pmu->intel_cap.perf_metrics = 0; 6631 pmu->intel_cap.pebs_output_pt_available = 1; 6632 6633 memcpy(pmu->hw_cache_event_ids, glp_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids)); 6634 memcpy(pmu->hw_cache_extra_regs, tnt_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs)); 6635 pmu->hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6636 pmu->event_constraints = intel_slm_event_constraints; 6637 pmu->pebs_constraints = intel_grt_pebs_event_constraints; 6638 pmu->extra_regs = intel_grt_extra_regs; 6639 if (is_mtl(boot_cpu_data.x86_model)) { 6640 x86_pmu.pebs_latency_data = mtl_latency_data_small; 6641 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6642 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 6643 mem_attr = mtl_hybrid_mem_attrs; 6644 intel_pmu_pebs_data_source_mtl(); 6645 x86_pmu.get_event_constraints = mtl_get_event_constraints; 6646 pmu->extra_regs = intel_cmt_extra_regs; 6647 pr_cont("Meteorlake Hybrid events, "); 6648 name = "meteorlake_hybrid"; 6649 } else { 6650 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 6651 intel_pmu_pebs_data_source_adl(); 6652 pr_cont("Alderlake Hybrid events, "); 6653 name = "alderlake_hybrid"; 6654 } 6655 break; 6656 6657 default: 6658 switch (x86_pmu.version) { 6659 case 1: 6660 x86_pmu.event_constraints = intel_v1_event_constraints; 6661 pr_cont("generic architected perfmon v1, "); 6662 name = "generic_arch_v1"; 6663 break; 6664 case 2: 6665 case 3: 6666 case 4: 6667 /* 6668 * default constraints for v2 and up 6669 */ 6670 x86_pmu.event_constraints = intel_gen_event_constraints; 6671 pr_cont("generic architected perfmon, "); 6672 name = "generic_arch_v2+"; 6673 break; 6674 default: 6675 /* 6676 * The default constraints for v5 and up can support up to 6677 * 16 fixed counters. For the fixed counters 4 and later, 6678 * the pseudo-encoding is applied. 6679 * The constraints may be cut according to the CPUID enumeration 6680 * by inserting the EVENT_CONSTRAINT_END. 6681 */ 6682 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) 6683 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED; 6684 intel_v5_gen_event_constraints[x86_pmu.num_counters_fixed].weight = -1; 6685 x86_pmu.event_constraints = intel_v5_gen_event_constraints; 6686 pr_cont("generic architected perfmon, "); 6687 name = "generic_arch_v5+"; 6688 break; 6689 } 6690 } 6691 6692 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); 6693 6694 if (!is_hybrid()) { 6695 group_events_td.attrs = td_attr; 6696 group_events_mem.attrs = mem_attr; 6697 group_events_tsx.attrs = tsx_attr; 6698 group_format_extra.attrs = extra_attr; 6699 group_format_extra_skl.attrs = extra_skl_attr; 6700 6701 x86_pmu.attr_update = attr_update; 6702 } else { 6703 hybrid_group_events_td.attrs = td_attr; 6704 hybrid_group_events_mem.attrs = mem_attr; 6705 hybrid_group_events_tsx.attrs = tsx_attr; 6706 hybrid_group_format_extra.attrs = extra_attr; 6707 6708 x86_pmu.attr_update = hybrid_attr_update; 6709 } 6710 6711 intel_pmu_check_num_counters(&x86_pmu.num_counters, 6712 &x86_pmu.num_counters_fixed, 6713 &x86_pmu.intel_ctrl, 6714 (u64)fixed_mask); 6715 6716 /* AnyThread may be deprecated on arch perfmon v5 or later */ 6717 if (x86_pmu.intel_cap.anythread_deprecated) 6718 x86_pmu.format_attrs = intel_arch_formats_attr; 6719 6720 intel_pmu_check_event_constraints(x86_pmu.event_constraints, 6721 x86_pmu.num_counters, 6722 x86_pmu.num_counters_fixed, 6723 x86_pmu.intel_ctrl); 6724 /* 6725 * Access LBR MSR may cause #GP under certain circumstances. 6726 * Check all LBR MSR here. 6727 * Disable LBR access if any LBR MSRs can not be accessed. 6728 */ 6729 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 6730 x86_pmu.lbr_nr = 0; 6731 for (i = 0; i < x86_pmu.lbr_nr; i++) { 6732 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 6733 check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 6734 x86_pmu.lbr_nr = 0; 6735 } 6736 6737 if (x86_pmu.lbr_nr) { 6738 intel_pmu_lbr_init(); 6739 6740 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 6741 6742 /* only support branch_stack snapshot for perfmon >= v2 */ 6743 if (x86_pmu.disable_all == intel_pmu_disable_all) { 6744 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) { 6745 static_call_update(perf_snapshot_branch_stack, 6746 intel_pmu_snapshot_arch_branch_stack); 6747 } else { 6748 static_call_update(perf_snapshot_branch_stack, 6749 intel_pmu_snapshot_branch_stack); 6750 } 6751 } 6752 } 6753 6754 intel_pmu_check_extra_regs(x86_pmu.extra_regs); 6755 6756 /* Support full width counters using alternative MSR range */ 6757 if (x86_pmu.intel_cap.full_width_write) { 6758 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 6759 x86_pmu.perfctr = MSR_IA32_PMC0; 6760 pr_cont("full-width counters, "); 6761 } 6762 6763 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) 6764 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 6765 6766 if (is_hybrid()) 6767 intel_pmu_check_hybrid_pmus((u64)fixed_mask); 6768 6769 if (x86_pmu.intel_cap.pebs_timing_info) 6770 x86_pmu.flags |= PMU_FL_RETIRE_LATENCY; 6771 6772 intel_aux_output_init(); 6773 6774 return 0; 6775 } 6776 6777 /* 6778 * HT bug: phase 2 init 6779 * Called once we have valid topology information to check 6780 * whether or not HT is enabled 6781 * If HT is off, then we disable the workaround 6782 */ 6783 static __init int fixup_ht_bug(void) 6784 { 6785 int c; 6786 /* 6787 * problem not present on this CPU model, nothing to do 6788 */ 6789 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 6790 return 0; 6791 6792 if (topology_max_smt_threads() > 1) { 6793 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 6794 return 0; 6795 } 6796 6797 cpus_read_lock(); 6798 6799 hardlockup_detector_perf_stop(); 6800 6801 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 6802 6803 x86_pmu.start_scheduling = NULL; 6804 x86_pmu.commit_scheduling = NULL; 6805 x86_pmu.stop_scheduling = NULL; 6806 6807 hardlockup_detector_perf_restart(); 6808 6809 for_each_online_cpu(c) 6810 free_excl_cntrs(&per_cpu(cpu_hw_events, c)); 6811 6812 cpus_read_unlock(); 6813 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 6814 return 0; 6815 } 6816 subsys_initcall(fixup_ht_bug) 6817