1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 /* Generic device ID of a discovery table device */ 4 #define UNCORE_DISCOVERY_TABLE_DEVICE 0x09a7 5 /* Capability ID for a discovery table device */ 6 #define UNCORE_EXT_CAP_ID_DISCOVERY 0x23 7 /* First DVSEC offset */ 8 #define UNCORE_DISCOVERY_DVSEC_OFFSET 0x8 9 /* Mask of the supported discovery entry type */ 10 #define UNCORE_DISCOVERY_DVSEC_ID_MASK 0xffff 11 /* PMON discovery entry type ID */ 12 #define UNCORE_DISCOVERY_DVSEC_ID_PMON 0x1 13 /* Second DVSEC offset */ 14 #define UNCORE_DISCOVERY_DVSEC2_OFFSET 0xc 15 /* Mask of the discovery table BAR offset */ 16 #define UNCORE_DISCOVERY_DVSEC2_BIR_MASK 0x7 17 /* Discovery table BAR base offset */ 18 #define UNCORE_DISCOVERY_BIR_BASE 0x10 19 /* Discovery table BAR step */ 20 #define UNCORE_DISCOVERY_BIR_STEP 0x4 21 /* Mask of the discovery table offset */ 22 #define UNCORE_DISCOVERY_MASK 0xf 23 /* Global discovery table size */ 24 #define UNCORE_DISCOVERY_GLOBAL_MAP_SIZE 0x20 25 26 #define uncore_discovery_invalid_unit(unit) \ 27 (!unit.table1 || !unit.ctl || !unit.table3 || \ 28 unit.table1 == -1ULL || unit.ctl == -1ULL || \ 29 unit.table3 == -1ULL) 30 31 #define GENERIC_PMON_CTL_EV_SEL_MASK 0x000000ff 32 #define GENERIC_PMON_CTL_UMASK_MASK 0x0000ff00 33 #define GENERIC_PMON_CTL_EDGE_DET (1 << 18) 34 #define GENERIC_PMON_CTL_INVERT (1 << 23) 35 #define GENERIC_PMON_CTL_TRESH_MASK 0xff000000 36 #define GENERIC_PMON_RAW_EVENT_MASK (GENERIC_PMON_CTL_EV_SEL_MASK | \ 37 GENERIC_PMON_CTL_UMASK_MASK | \ 38 GENERIC_PMON_CTL_EDGE_DET | \ 39 GENERIC_PMON_CTL_INVERT | \ 40 GENERIC_PMON_CTL_TRESH_MASK) 41 42 #define GENERIC_PMON_BOX_CTL_FRZ (1 << 0) 43 #define GENERIC_PMON_BOX_CTL_RST_CTRL (1 << 8) 44 #define GENERIC_PMON_BOX_CTL_RST_CTRS (1 << 9) 45 #define GENERIC_PMON_BOX_CTL_INT (GENERIC_PMON_BOX_CTL_RST_CTRL | \ 46 GENERIC_PMON_BOX_CTL_RST_CTRS) 47 48 enum uncore_access_type { 49 UNCORE_ACCESS_MSR = 0, 50 UNCORE_ACCESS_MMIO, 51 UNCORE_ACCESS_PCI, 52 53 UNCORE_ACCESS_MAX, 54 }; 55 56 struct uncore_global_discovery { 57 union { 58 u64 table1; 59 struct { 60 u64 type : 8, 61 stride : 8, 62 max_units : 10, 63 __reserved_1 : 36, 64 access_type : 2; 65 }; 66 }; 67 68 u64 ctl; /* Global Control Address */ 69 70 union { 71 u64 table3; 72 struct { 73 u64 status_offset : 8, 74 num_status : 16, 75 __reserved_2 : 40; 76 }; 77 }; 78 }; 79 80 struct uncore_unit_discovery { 81 union { 82 u64 table1; 83 struct { 84 u64 num_regs : 8, 85 ctl_offset : 8, 86 bit_width : 8, 87 ctr_offset : 8, 88 status_offset : 8, 89 __reserved_1 : 22, 90 access_type : 2; 91 }; 92 }; 93 94 u64 ctl; /* Unit Control Address */ 95 96 union { 97 u64 table3; 98 struct { 99 u64 box_type : 16, 100 box_id : 16, 101 __reserved_2 : 32; 102 }; 103 }; 104 }; 105 106 struct intel_uncore_discovery_type { 107 struct rb_node node; 108 enum uncore_access_type access_type; 109 u64 box_ctrl; /* Unit ctrl addr of the first box */ 110 u64 *box_ctrl_die; /* Unit ctrl addr of the first box of each die */ 111 u16 type; /* Type ID of the uncore block */ 112 u8 num_counters; 113 u8 counter_width; 114 u8 ctl_offset; /* Counter Control 0 offset */ 115 u8 ctr_offset; /* Counter 0 offset */ 116 u16 num_boxes; /* number of boxes for the uncore block */ 117 unsigned int *ids; /* Box IDs */ 118 unsigned int *box_offset; /* Box offset */ 119 }; 120 121 bool intel_uncore_has_discovery_tables(void); 122 void intel_uncore_clear_discovery_tables(void); 123 void intel_uncore_generic_uncore_cpu_init(void); 124