xref: /linux/arch/x86/events/intel/uncore_discovery.h (revision edae1f06)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 /* Generic device ID of a discovery table device */
4 #define UNCORE_DISCOVERY_TABLE_DEVICE		0x09a7
5 /* Capability ID for a discovery table device */
6 #define UNCORE_EXT_CAP_ID_DISCOVERY		0x23
7 /* First DVSEC offset */
8 #define UNCORE_DISCOVERY_DVSEC_OFFSET		0x8
9 /* Mask of the supported discovery entry type */
10 #define UNCORE_DISCOVERY_DVSEC_ID_MASK		0xffff
11 /* PMON discovery entry type ID */
12 #define UNCORE_DISCOVERY_DVSEC_ID_PMON		0x1
13 /* Second DVSEC offset */
14 #define UNCORE_DISCOVERY_DVSEC2_OFFSET		0xc
15 /* Mask of the discovery table BAR offset */
16 #define UNCORE_DISCOVERY_DVSEC2_BIR_MASK	0x7
17 /* Discovery table BAR base offset */
18 #define UNCORE_DISCOVERY_BIR_BASE		0x10
19 /* Discovery table BAR step */
20 #define UNCORE_DISCOVERY_BIR_STEP		0x4
21 /* Mask of the discovery table offset */
22 #define UNCORE_DISCOVERY_MASK			0xf
23 /* Global discovery table size */
24 #define UNCORE_DISCOVERY_GLOBAL_MAP_SIZE	0x20
25 
26 #define uncore_discovery_invalid_unit(unit)			\
27 	(!unit.table1 || !unit.ctl || !unit.table3 ||	\
28 	 unit.table1 == -1ULL || unit.ctl == -1ULL ||	\
29 	 unit.table3 == -1ULL)
30 
31 enum uncore_access_type {
32 	UNCORE_ACCESS_MSR	= 0,
33 	UNCORE_ACCESS_MMIO,
34 	UNCORE_ACCESS_PCI,
35 
36 	UNCORE_ACCESS_MAX,
37 };
38 
39 struct uncore_global_discovery {
40 	union {
41 		u64	table1;
42 		struct {
43 			u64	type : 8,
44 				stride : 8,
45 				max_units : 10,
46 				__reserved_1 : 36,
47 				access_type : 2;
48 		};
49 	};
50 
51 	u64	ctl;		/* Global Control Address */
52 
53 	union {
54 		u64	table3;
55 		struct {
56 			u64	status_offset : 8,
57 				num_status : 16,
58 				__reserved_2 : 40;
59 		};
60 	};
61 };
62 
63 struct uncore_unit_discovery {
64 	union {
65 		u64	table1;
66 		struct {
67 			u64	num_regs : 8,
68 				ctl_offset : 8,
69 				bit_width : 8,
70 				ctr_offset : 8,
71 				status_offset : 8,
72 				__reserved_1 : 22,
73 				access_type : 2;
74 			};
75 		};
76 
77 	u64	ctl;		/* Unit Control Address */
78 
79 	union {
80 		u64	table3;
81 		struct {
82 			u64	box_type : 16,
83 				box_id : 16,
84 				__reserved_2 : 32;
85 		};
86 	};
87 };
88 
89 struct intel_uncore_discovery_type {
90 	struct rb_node	node;
91 	enum uncore_access_type	access_type;
92 	u64		box_ctrl;	/* Unit ctrl addr of the first box */
93 	u64		*box_ctrl_die;	/* Unit ctrl addr of the first box of each die */
94 	u16		type;		/* Type ID of the uncore block */
95 	u8		num_counters;
96 	u8		counter_width;
97 	u8		ctl_offset;	/* Counter Control 0 offset */
98 	u8		ctr_offset;	/* Counter 0 offset */
99 	u16		num_boxes;	/* number of boxes for the uncore block */
100 	unsigned int	*ids;		/* Box IDs */
101 	unsigned int	*box_offset;	/* Box offset */
102 };
103 
104 bool intel_uncore_has_discovery_tables(void);
105 void intel_uncore_clear_discovery_tables(void);
106