1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_IO_H 3 #define _ASM_X86_IO_H 4 5 /* 6 * This file contains the definitions for the x86 IO instructions 7 * inb/inw/inl/outb/outw/outl and the "string versions" of the same 8 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" 9 * versions of the single-IO instructions (inb_p/inw_p/..). 10 * 11 * This file is not meant to be obfuscating: it's just complicated 12 * to (a) handle it all in a way that makes gcc able to optimize it 13 * as well as possible and (b) trying to avoid writing the same thing 14 * over and over again with slight variations and possibly making a 15 * mistake somewhere. 16 */ 17 18 /* 19 * Thanks to James van Artsdalen for a better timing-fix than 20 * the two short jumps: using outb's to a nonexistent port seems 21 * to guarantee better timings even on fast machines. 22 * 23 * On the other hand, I'd like to be sure of a non-existent port: 24 * I feel a bit unsafe about using 0x80 (should be safe, though) 25 * 26 * Linus 27 */ 28 29 /* 30 * Bit simplified and optimized by Jan Hubicka 31 * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999. 32 * 33 * isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added, 34 * isa_read[wl] and isa_write[wl] fixed 35 * - Arnaldo Carvalho de Melo <acme@conectiva.com.br> 36 */ 37 38 #define ARCH_HAS_IOREMAP_WC 39 #define ARCH_HAS_IOREMAP_WT 40 41 #include <linux/string.h> 42 #include <linux/compiler.h> 43 #include <linux/cc_platform.h> 44 #include <asm/page.h> 45 #include <asm/early_ioremap.h> 46 #include <asm/pgtable_types.h> 47 #include <asm/shared/io.h> 48 49 #define build_mmio_read(name, size, type, reg, barrier) \ 50 static inline type name(const volatile void __iomem *addr) \ 51 { type ret; asm volatile("mov" size " %1,%0":reg (ret) \ 52 :"m" (*(volatile type __force *)addr) barrier); return ret; } 53 54 #define build_mmio_write(name, size, type, reg, barrier) \ 55 static inline void name(type val, volatile void __iomem *addr) \ 56 { asm volatile("mov" size " %0,%1": :reg (val), \ 57 "m" (*(volatile type __force *)addr) barrier); } 58 59 build_mmio_read(readb, "b", unsigned char, "=q", :"memory") 60 build_mmio_read(readw, "w", unsigned short, "=r", :"memory") 61 build_mmio_read(readl, "l", unsigned int, "=r", :"memory") 62 63 build_mmio_read(__readb, "b", unsigned char, "=q", ) 64 build_mmio_read(__readw, "w", unsigned short, "=r", ) 65 build_mmio_read(__readl, "l", unsigned int, "=r", ) 66 67 build_mmio_write(writeb, "b", unsigned char, "q", :"memory") 68 build_mmio_write(writew, "w", unsigned short, "r", :"memory") 69 build_mmio_write(writel, "l", unsigned int, "r", :"memory") 70 71 build_mmio_write(__writeb, "b", unsigned char, "q", ) 72 build_mmio_write(__writew, "w", unsigned short, "r", ) 73 build_mmio_write(__writel, "l", unsigned int, "r", ) 74 75 #define readb readb 76 #define readw readw 77 #define readl readl 78 #define readb_relaxed(a) __readb(a) 79 #define readw_relaxed(a) __readw(a) 80 #define readl_relaxed(a) __readl(a) 81 #define __raw_readb __readb 82 #define __raw_readw __readw 83 #define __raw_readl __readl 84 85 #define writeb writeb 86 #define writew writew 87 #define writel writel 88 #define writeb_relaxed(v, a) __writeb(v, a) 89 #define writew_relaxed(v, a) __writew(v, a) 90 #define writel_relaxed(v, a) __writel(v, a) 91 #define __raw_writeb __writeb 92 #define __raw_writew __writew 93 #define __raw_writel __writel 94 95 #ifdef CONFIG_X86_64 96 97 build_mmio_read(readq, "q", u64, "=r", :"memory") 98 build_mmio_read(__readq, "q", u64, "=r", ) 99 build_mmio_write(writeq, "q", u64, "r", :"memory") 100 build_mmio_write(__writeq, "q", u64, "r", ) 101 102 #define readq_relaxed(a) __readq(a) 103 #define writeq_relaxed(v, a) __writeq(v, a) 104 105 #define __raw_readq __readq 106 #define __raw_writeq __writeq 107 108 /* Let people know that we have them */ 109 #define readq readq 110 #define writeq writeq 111 112 #endif 113 114 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE 115 extern int valid_phys_addr_range(phys_addr_t addr, size_t size); 116 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); 117 118 /** 119 * virt_to_phys - map virtual addresses to physical 120 * @address: address to remap 121 * 122 * The returned physical address is the physical (CPU) mapping for 123 * the memory address given. It is only valid to use this function on 124 * addresses directly mapped or allocated via kmalloc. 125 * 126 * This function does not give bus mappings for DMA transfers. In 127 * almost all conceivable cases a device driver should not be using 128 * this function 129 */ 130 131 static inline phys_addr_t virt_to_phys(volatile void *address) 132 { 133 return __pa(address); 134 } 135 #define virt_to_phys virt_to_phys 136 137 /** 138 * phys_to_virt - map physical address to virtual 139 * @address: address to remap 140 * 141 * The returned virtual address is a current CPU mapping for 142 * the memory address given. It is only valid to use this function on 143 * addresses that have a kernel mapping 144 * 145 * This function does not handle bus mappings for DMA transfers. In 146 * almost all conceivable cases a device driver should not be using 147 * this function 148 */ 149 150 static inline void *phys_to_virt(phys_addr_t address) 151 { 152 return __va(address); 153 } 154 #define phys_to_virt phys_to_virt 155 156 /* 157 * Change "struct page" to physical address. 158 */ 159 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) 160 161 /* 162 * ISA I/O bus memory addresses are 1:1 with the physical address. 163 * However, we truncate the address to unsigned int to avoid undesirable 164 * promotions in legacy drivers. 165 */ 166 static inline unsigned int isa_virt_to_bus(volatile void *address) 167 { 168 return (unsigned int)virt_to_phys(address); 169 } 170 #define isa_bus_to_virt phys_to_virt 171 172 /* 173 * However PCI ones are not necessarily 1:1 and therefore these interfaces 174 * are forbidden in portable PCI drivers. 175 * 176 * Allow them on x86 for legacy drivers, though. 177 */ 178 #define virt_to_bus virt_to_phys 179 #define bus_to_virt phys_to_virt 180 181 /* 182 * The default ioremap() behavior is non-cached; if you need something 183 * else, you probably want one of the following. 184 */ 185 extern void __iomem *ioremap_uc(resource_size_t offset, unsigned long size); 186 #define ioremap_uc ioremap_uc 187 extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size); 188 #define ioremap_cache ioremap_cache 189 extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size, unsigned long prot_val); 190 #define ioremap_prot ioremap_prot 191 extern void __iomem *ioremap_encrypted(resource_size_t phys_addr, unsigned long size); 192 #define ioremap_encrypted ioremap_encrypted 193 194 /** 195 * ioremap - map bus memory into CPU space 196 * @offset: bus address of the memory 197 * @size: size of the resource to map 198 * 199 * ioremap performs a platform specific sequence of operations to 200 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 201 * writew/writel functions and the other mmio helpers. The returned 202 * address is not guaranteed to be usable directly as a virtual 203 * address. 204 * 205 * If the area you are trying to map is a PCI BAR you should have a 206 * look at pci_iomap(). 207 */ 208 void __iomem *ioremap(resource_size_t offset, unsigned long size); 209 #define ioremap ioremap 210 211 extern void iounmap(volatile void __iomem *addr); 212 #define iounmap iounmap 213 214 #ifdef __KERNEL__ 215 216 void memcpy_fromio(void *, const volatile void __iomem *, size_t); 217 void memcpy_toio(volatile void __iomem *, const void *, size_t); 218 void memset_io(volatile void __iomem *, int, size_t); 219 220 #define memcpy_fromio memcpy_fromio 221 #define memcpy_toio memcpy_toio 222 #define memset_io memset_io 223 224 #include <asm-generic/iomap.h> 225 226 /* 227 * ISA space is 'always mapped' on a typical x86 system, no need to 228 * explicitly ioremap() it. The fact that the ISA IO space is mapped 229 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values 230 * are physical addresses. The following constant pointer can be 231 * used as the IO-area pointer (it can be iounmapped as well, so the 232 * analogy with PCI is quite large): 233 */ 234 #define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET)) 235 236 #endif /* __KERNEL__ */ 237 238 extern void native_io_delay(void); 239 240 extern int io_delay_type; 241 extern void io_delay_init(void); 242 243 #if defined(CONFIG_PARAVIRT) 244 #include <asm/paravirt.h> 245 #else 246 247 static inline void slow_down_io(void) 248 { 249 native_io_delay(); 250 #ifdef REALLY_SLOW_IO 251 native_io_delay(); 252 native_io_delay(); 253 native_io_delay(); 254 #endif 255 } 256 257 #endif 258 259 #define BUILDIO(bwl, bw, type) \ 260 static inline void out##bwl##_p(type value, u16 port) \ 261 { \ 262 out##bwl(value, port); \ 263 slow_down_io(); \ 264 } \ 265 \ 266 static inline type in##bwl##_p(u16 port) \ 267 { \ 268 type value = in##bwl(port); \ 269 slow_down_io(); \ 270 return value; \ 271 } \ 272 \ 273 static inline void outs##bwl(u16 port, const void *addr, unsigned long count) \ 274 { \ 275 if (cc_platform_has(CC_ATTR_GUEST_UNROLL_STRING_IO)) { \ 276 type *value = (type *)addr; \ 277 while (count) { \ 278 out##bwl(*value, port); \ 279 value++; \ 280 count--; \ 281 } \ 282 } else { \ 283 asm volatile("rep; outs" #bwl \ 284 : "+S"(addr), "+c"(count) \ 285 : "d"(port) : "memory"); \ 286 } \ 287 } \ 288 \ 289 static inline void ins##bwl(u16 port, void *addr, unsigned long count) \ 290 { \ 291 if (cc_platform_has(CC_ATTR_GUEST_UNROLL_STRING_IO)) { \ 292 type *value = (type *)addr; \ 293 while (count) { \ 294 *value = in##bwl(port); \ 295 value++; \ 296 count--; \ 297 } \ 298 } else { \ 299 asm volatile("rep; ins" #bwl \ 300 : "+D"(addr), "+c"(count) \ 301 : "d"(port) : "memory"); \ 302 } \ 303 } 304 305 BUILDIO(b, b, u8) 306 BUILDIO(w, w, u16) 307 BUILDIO(l, , u32) 308 #undef BUILDIO 309 310 #define inb_p inb_p 311 #define inw_p inw_p 312 #define inl_p inl_p 313 #define insb insb 314 #define insw insw 315 #define insl insl 316 317 #define outb_p outb_p 318 #define outw_p outw_p 319 #define outl_p outl_p 320 #define outsb outsb 321 #define outsw outsw 322 #define outsl outsl 323 324 extern void *xlate_dev_mem_ptr(phys_addr_t phys); 325 extern void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr); 326 327 #define xlate_dev_mem_ptr xlate_dev_mem_ptr 328 #define unxlate_dev_mem_ptr unxlate_dev_mem_ptr 329 330 extern int ioremap_change_attr(unsigned long vaddr, unsigned long size, 331 enum page_cache_mode pcm); 332 extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size); 333 #define ioremap_wc ioremap_wc 334 extern void __iomem *ioremap_wt(resource_size_t offset, unsigned long size); 335 #define ioremap_wt ioremap_wt 336 337 extern bool is_early_ioremap_ptep(pte_t *ptep); 338 339 #define IO_SPACE_LIMIT 0xffff 340 341 #include <asm-generic/io.h> 342 #undef PCI_IOBASE 343 344 #ifdef CONFIG_MTRR 345 extern int __must_check arch_phys_wc_index(int handle); 346 #define arch_phys_wc_index arch_phys_wc_index 347 348 extern int __must_check arch_phys_wc_add(unsigned long base, 349 unsigned long size); 350 extern void arch_phys_wc_del(int handle); 351 #define arch_phys_wc_add arch_phys_wc_add 352 #endif 353 354 #ifdef CONFIG_X86_PAT 355 extern int arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size); 356 extern void arch_io_free_memtype_wc(resource_size_t start, resource_size_t size); 357 #define arch_io_reserve_memtype_wc arch_io_reserve_memtype_wc 358 #endif 359 360 #ifdef CONFIG_AMD_MEM_ENCRYPT 361 extern bool arch_memremap_can_ram_remap(resource_size_t offset, 362 unsigned long size, 363 unsigned long flags); 364 #define arch_memremap_can_ram_remap arch_memremap_can_ram_remap 365 366 extern bool phys_mem_access_encrypted(unsigned long phys_addr, 367 unsigned long size); 368 #else 369 static inline bool phys_mem_access_encrypted(unsigned long phys_addr, 370 unsigned long size) 371 { 372 return true; 373 } 374 #endif 375 376 /** 377 * iosubmit_cmds512 - copy data to single MMIO location, in 512-bit units 378 * @dst: destination, in MMIO space (must be 512-bit aligned) 379 * @src: source 380 * @count: number of 512 bits quantities to submit 381 * 382 * Submit data from kernel space to MMIO space, in units of 512 bits at a 383 * time. Order of access is not guaranteed, nor is a memory barrier 384 * performed afterwards. 385 * 386 * Warning: Do not use this helper unless your driver has checked that the CPU 387 * instruction is supported on the platform. 388 */ 389 static inline void iosubmit_cmds512(void __iomem *dst, const void *src, 390 size_t count) 391 { 392 const u8 *from = src; 393 const u8 *end = from + count * 64; 394 395 while (from < end) { 396 movdir64b(dst, from); 397 from += 64; 398 } 399 } 400 401 #endif /* _ASM_X86_IO_H */ 402