1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_MSR_INDEX_H 3 #define _ASM_X86_MSR_INDEX_H 4 5 #include <linux/bits.h> 6 7 /* 8 * CPU model specific register (MSR) numbers. 9 * 10 * Do not add new entries to this file unless the definitions are shared 11 * between multiple compilation units. 12 */ 13 14 /* x86-64 specific MSRs */ 15 #define MSR_EFER 0xc0000080 /* extended feature register */ 16 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 17 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 18 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 19 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 20 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 21 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 22 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 23 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 24 25 /* EFER bits: */ 26 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 27 #define _EFER_LME 8 /* Long mode enable */ 28 #define _EFER_LMA 10 /* Long mode active (read-only) */ 29 #define _EFER_NX 11 /* No execute enable */ 30 #define _EFER_SVME 12 /* Enable virtualization */ 31 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 32 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 33 34 #define EFER_SCE (1<<_EFER_SCE) 35 #define EFER_LME (1<<_EFER_LME) 36 #define EFER_LMA (1<<_EFER_LMA) 37 #define EFER_NX (1<<_EFER_NX) 38 #define EFER_SVME (1<<_EFER_SVME) 39 #define EFER_LMSLE (1<<_EFER_LMSLE) 40 #define EFER_FFXSR (1<<_EFER_FFXSR) 41 42 /* Intel MSRs. Some also available on other CPUs */ 43 44 #define MSR_TEST_CTRL 0x00000033 45 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 46 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) 47 48 #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 49 #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ 50 #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ 51 #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ 52 #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 53 #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 54 #define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */ 55 #define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT) 56 57 #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 58 #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ 59 60 #define MSR_PPIN_CTL 0x0000004e 61 #define MSR_PPIN 0x0000004f 62 63 #define MSR_IA32_PERFCTR0 0x000000c1 64 #define MSR_IA32_PERFCTR1 0x000000c2 65 #define MSR_FSB_FREQ 0x000000cd 66 #define MSR_PLATFORM_INFO 0x000000ce 67 #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 68 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 69 70 #define MSR_IA32_UMWAIT_CONTROL 0xe1 71 #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) 72 #define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) 73 /* 74 * The time field is bit[31:2], but representing a 32bit value with 75 * bit[1:0] zero. 76 */ 77 #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) 78 79 /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ 80 #define MSR_IA32_CORE_CAPS 0x000000cf 81 #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT 2 82 #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT) 83 #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 84 #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT) 85 86 #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 87 #define NHM_C3_AUTO_DEMOTE (1UL << 25) 88 #define NHM_C1_AUTO_DEMOTE (1UL << 26) 89 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 90 #define SNB_C3_AUTO_UNDEMOTE (1UL << 27) 91 #define SNB_C1_AUTO_UNDEMOTE (1UL << 28) 92 93 #define MSR_MTRRcap 0x000000fe 94 95 #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 96 #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ 97 #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ 98 #define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */ 99 #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ 100 #define ARCH_CAP_SSB_NO BIT(4) /* 101 * Not susceptible to Speculative Store Bypass 102 * attack, so no Speculative Store Bypass 103 * control required. 104 */ 105 #define ARCH_CAP_MDS_NO BIT(5) /* 106 * Not susceptible to 107 * Microarchitectural Data 108 * Sampling (MDS) vulnerabilities. 109 */ 110 #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* 111 * The processor is not susceptible to a 112 * machine check error due to modifying the 113 * code page size along with either the 114 * physical address or cache type 115 * without TLB invalidation. 116 */ 117 #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ 118 #define ARCH_CAP_TAA_NO BIT(8) /* 119 * Not susceptible to 120 * TSX Async Abort (TAA) vulnerabilities. 121 */ 122 #define ARCH_CAP_SBDR_SSDP_NO BIT(13) /* 123 * Not susceptible to SBDR and SSDP 124 * variants of Processor MMIO stale data 125 * vulnerabilities. 126 */ 127 #define ARCH_CAP_FBSDP_NO BIT(14) /* 128 * Not susceptible to FBSDP variant of 129 * Processor MMIO stale data 130 * vulnerabilities. 131 */ 132 #define ARCH_CAP_PSDP_NO BIT(15) /* 133 * Not susceptible to PSDP variant of 134 * Processor MMIO stale data 135 * vulnerabilities. 136 */ 137 #define ARCH_CAP_FB_CLEAR BIT(17) /* 138 * VERW clears CPU fill buffer 139 * even on MDS_NO CPUs. 140 */ 141 #define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /* 142 * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS] 143 * bit available to control VERW 144 * behavior. 145 */ 146 #define ARCH_CAP_RRSBA BIT(19) /* 147 * Indicates RET may use predictors 148 * other than the RSB. With eIBRS 149 * enabled predictions in kernel mode 150 * are restricted to targets in 151 * kernel. 152 */ 153 154 #define MSR_IA32_FLUSH_CMD 0x0000010b 155 #define L1D_FLUSH BIT(0) /* 156 * Writeback and invalidate the 157 * L1 data cache. 158 */ 159 160 #define MSR_IA32_BBL_CR_CTL 0x00000119 161 #define MSR_IA32_BBL_CR_CTL3 0x0000011e 162 163 #define MSR_IA32_TSX_CTRL 0x00000122 164 #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ 165 #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ 166 167 #define MSR_IA32_MCU_OPT_CTRL 0x00000123 168 #define RNGDS_MITG_DIS BIT(0) /* SRBDS support */ 169 #define RTM_ALLOW BIT(1) /* TSX development mode */ 170 #define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */ 171 172 #define MSR_IA32_SYSENTER_CS 0x00000174 173 #define MSR_IA32_SYSENTER_ESP 0x00000175 174 #define MSR_IA32_SYSENTER_EIP 0x00000176 175 176 #define MSR_IA32_MCG_CAP 0x00000179 177 #define MSR_IA32_MCG_STATUS 0x0000017a 178 #define MSR_IA32_MCG_CTL 0x0000017b 179 #define MSR_ERROR_CONTROL 0x0000017f 180 #define MSR_IA32_MCG_EXT_CTL 0x000004d0 181 182 #define MSR_OFFCORE_RSP_0 0x000001a6 183 #define MSR_OFFCORE_RSP_1 0x000001a7 184 #define MSR_TURBO_RATIO_LIMIT 0x000001ad 185 #define MSR_TURBO_RATIO_LIMIT1 0x000001ae 186 #define MSR_TURBO_RATIO_LIMIT2 0x000001af 187 188 #define MSR_LBR_SELECT 0x000001c8 189 #define MSR_LBR_TOS 0x000001c9 190 191 #define MSR_IA32_POWER_CTL 0x000001fc 192 #define MSR_IA32_POWER_CTL_BIT_EE 19 193 194 /* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */ 195 #define MSR_INTEGRITY_CAPS 0x000002d9 196 #define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4 197 #define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT) 198 199 #define MSR_LBR_NHM_FROM 0x00000680 200 #define MSR_LBR_NHM_TO 0x000006c0 201 #define MSR_LBR_CORE_FROM 0x00000040 202 #define MSR_LBR_CORE_TO 0x00000060 203 204 #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 205 #define LBR_INFO_MISPRED BIT_ULL(63) 206 #define LBR_INFO_IN_TX BIT_ULL(62) 207 #define LBR_INFO_ABORT BIT_ULL(61) 208 #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) 209 #define LBR_INFO_CYCLES 0xffff 210 #define LBR_INFO_BR_TYPE_OFFSET 56 211 #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) 212 213 #define MSR_ARCH_LBR_CTL 0x000014ce 214 #define ARCH_LBR_CTL_LBREN BIT(0) 215 #define ARCH_LBR_CTL_CPL_OFFSET 1 216 #define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET) 217 #define ARCH_LBR_CTL_STACK_OFFSET 3 218 #define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET) 219 #define ARCH_LBR_CTL_FILTER_OFFSET 16 220 #define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET) 221 #define MSR_ARCH_LBR_DEPTH 0x000014cf 222 #define MSR_ARCH_LBR_FROM_0 0x00001500 223 #define MSR_ARCH_LBR_TO_0 0x00001600 224 #define MSR_ARCH_LBR_INFO_0 0x00001200 225 226 #define MSR_IA32_PEBS_ENABLE 0x000003f1 227 #define MSR_PEBS_DATA_CFG 0x000003f2 228 #define MSR_IA32_DS_AREA 0x00000600 229 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 230 #define PERF_CAP_METRICS_IDX 15 231 #define PERF_CAP_PT_IDX 16 232 233 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 234 235 #define MSR_IA32_RTIT_CTL 0x00000570 236 #define RTIT_CTL_TRACEEN BIT(0) 237 #define RTIT_CTL_CYCLEACC BIT(1) 238 #define RTIT_CTL_OS BIT(2) 239 #define RTIT_CTL_USR BIT(3) 240 #define RTIT_CTL_PWR_EVT_EN BIT(4) 241 #define RTIT_CTL_FUP_ON_PTW BIT(5) 242 #define RTIT_CTL_FABRIC_EN BIT(6) 243 #define RTIT_CTL_CR3EN BIT(7) 244 #define RTIT_CTL_TOPA BIT(8) 245 #define RTIT_CTL_MTC_EN BIT(9) 246 #define RTIT_CTL_TSC_EN BIT(10) 247 #define RTIT_CTL_DISRETC BIT(11) 248 #define RTIT_CTL_PTW_EN BIT(12) 249 #define RTIT_CTL_BRANCH_EN BIT(13) 250 #define RTIT_CTL_EVENT_EN BIT(31) 251 #define RTIT_CTL_NOTNT BIT_ULL(55) 252 #define RTIT_CTL_MTC_RANGE_OFFSET 14 253 #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 254 #define RTIT_CTL_CYC_THRESH_OFFSET 19 255 #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 256 #define RTIT_CTL_PSB_FREQ_OFFSET 24 257 #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 258 #define RTIT_CTL_ADDR0_OFFSET 32 259 #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 260 #define RTIT_CTL_ADDR1_OFFSET 36 261 #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 262 #define RTIT_CTL_ADDR2_OFFSET 40 263 #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 264 #define RTIT_CTL_ADDR3_OFFSET 44 265 #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 266 #define MSR_IA32_RTIT_STATUS 0x00000571 267 #define RTIT_STATUS_FILTEREN BIT(0) 268 #define RTIT_STATUS_CONTEXTEN BIT(1) 269 #define RTIT_STATUS_TRIGGEREN BIT(2) 270 #define RTIT_STATUS_BUFFOVF BIT(3) 271 #define RTIT_STATUS_ERROR BIT(4) 272 #define RTIT_STATUS_STOPPED BIT(5) 273 #define RTIT_STATUS_BYTECNT_OFFSET 32 274 #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) 275 #define MSR_IA32_RTIT_ADDR0_A 0x00000580 276 #define MSR_IA32_RTIT_ADDR0_B 0x00000581 277 #define MSR_IA32_RTIT_ADDR1_A 0x00000582 278 #define MSR_IA32_RTIT_ADDR1_B 0x00000583 279 #define MSR_IA32_RTIT_ADDR2_A 0x00000584 280 #define MSR_IA32_RTIT_ADDR2_B 0x00000585 281 #define MSR_IA32_RTIT_ADDR3_A 0x00000586 282 #define MSR_IA32_RTIT_ADDR3_B 0x00000587 283 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 284 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 285 #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 286 287 #define MSR_MTRRfix64K_00000 0x00000250 288 #define MSR_MTRRfix16K_80000 0x00000258 289 #define MSR_MTRRfix16K_A0000 0x00000259 290 #define MSR_MTRRfix4K_C0000 0x00000268 291 #define MSR_MTRRfix4K_C8000 0x00000269 292 #define MSR_MTRRfix4K_D0000 0x0000026a 293 #define MSR_MTRRfix4K_D8000 0x0000026b 294 #define MSR_MTRRfix4K_E0000 0x0000026c 295 #define MSR_MTRRfix4K_E8000 0x0000026d 296 #define MSR_MTRRfix4K_F0000 0x0000026e 297 #define MSR_MTRRfix4K_F8000 0x0000026f 298 #define MSR_MTRRdefType 0x000002ff 299 300 #define MSR_IA32_CR_PAT 0x00000277 301 302 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 303 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 304 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 305 #define MSR_IA32_LASTINTFROMIP 0x000001dd 306 #define MSR_IA32_LASTINTTOIP 0x000001de 307 308 #define MSR_IA32_PASID 0x00000d93 309 #define MSR_IA32_PASID_VALID BIT_ULL(31) 310 311 /* DEBUGCTLMSR bits (others vary by model): */ 312 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 313 #define DEBUGCTLMSR_BTF_SHIFT 1 314 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 315 #define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2) 316 #define DEBUGCTLMSR_TR (1UL << 6) 317 #define DEBUGCTLMSR_BTS (1UL << 7) 318 #define DEBUGCTLMSR_BTINT (1UL << 8) 319 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 320 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 321 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 322 #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) 323 #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 324 #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 325 326 #define MSR_PEBS_FRONTEND 0x000003f7 327 328 #define MSR_IA32_MC0_CTL 0x00000400 329 #define MSR_IA32_MC0_STATUS 0x00000401 330 #define MSR_IA32_MC0_ADDR 0x00000402 331 #define MSR_IA32_MC0_MISC 0x00000403 332 333 /* C-state Residency Counters */ 334 #define MSR_PKG_C3_RESIDENCY 0x000003f8 335 #define MSR_PKG_C6_RESIDENCY 0x000003f9 336 #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 337 #define MSR_PKG_C7_RESIDENCY 0x000003fa 338 #define MSR_CORE_C3_RESIDENCY 0x000003fc 339 #define MSR_CORE_C6_RESIDENCY 0x000003fd 340 #define MSR_CORE_C7_RESIDENCY 0x000003fe 341 #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 342 #define MSR_PKG_C2_RESIDENCY 0x0000060d 343 #define MSR_PKG_C8_RESIDENCY 0x00000630 344 #define MSR_PKG_C9_RESIDENCY 0x00000631 345 #define MSR_PKG_C10_RESIDENCY 0x00000632 346 347 /* Interrupt Response Limit */ 348 #define MSR_PKGC3_IRTL 0x0000060a 349 #define MSR_PKGC6_IRTL 0x0000060b 350 #define MSR_PKGC7_IRTL 0x0000060c 351 #define MSR_PKGC8_IRTL 0x00000633 352 #define MSR_PKGC9_IRTL 0x00000634 353 #define MSR_PKGC10_IRTL 0x00000635 354 355 /* Run Time Average Power Limiting (RAPL) Interface */ 356 357 #define MSR_VR_CURRENT_CONFIG 0x00000601 358 #define MSR_RAPL_POWER_UNIT 0x00000606 359 360 #define MSR_PKG_POWER_LIMIT 0x00000610 361 #define MSR_PKG_ENERGY_STATUS 0x00000611 362 #define MSR_PKG_PERF_STATUS 0x00000613 363 #define MSR_PKG_POWER_INFO 0x00000614 364 365 #define MSR_DRAM_POWER_LIMIT 0x00000618 366 #define MSR_DRAM_ENERGY_STATUS 0x00000619 367 #define MSR_DRAM_PERF_STATUS 0x0000061b 368 #define MSR_DRAM_POWER_INFO 0x0000061c 369 370 #define MSR_PP0_POWER_LIMIT 0x00000638 371 #define MSR_PP0_ENERGY_STATUS 0x00000639 372 #define MSR_PP0_POLICY 0x0000063a 373 #define MSR_PP0_PERF_STATUS 0x0000063b 374 375 #define MSR_PP1_POWER_LIMIT 0x00000640 376 #define MSR_PP1_ENERGY_STATUS 0x00000641 377 #define MSR_PP1_POLICY 0x00000642 378 379 #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 380 #define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a 381 #define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b 382 383 /* Config TDP MSRs */ 384 #define MSR_CONFIG_TDP_NOMINAL 0x00000648 385 #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 386 #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 387 #define MSR_CONFIG_TDP_CONTROL 0x0000064B 388 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 389 390 #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 391 392 #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 393 #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 394 #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 395 #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 396 397 #define MSR_CORE_C1_RES 0x00000660 398 #define MSR_MODULE_C6_RES_MS 0x00000664 399 400 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 401 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 402 403 #define MSR_ATOM_CORE_RATIOS 0x0000066a 404 #define MSR_ATOM_CORE_VIDS 0x0000066b 405 #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 406 #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 407 408 #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 409 #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 410 #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 411 412 /* Control-flow Enforcement Technology MSRs */ 413 #define MSR_IA32_U_CET 0x000006a0 /* user mode cet */ 414 #define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */ 415 #define CET_SHSTK_EN BIT_ULL(0) 416 #define CET_WRSS_EN BIT_ULL(1) 417 #define CET_ENDBR_EN BIT_ULL(2) 418 #define CET_LEG_IW_EN BIT_ULL(3) 419 #define CET_NO_TRACK_EN BIT_ULL(4) 420 #define CET_SUPPRESS_DISABLE BIT_ULL(5) 421 #define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9)) 422 #define CET_SUPPRESS BIT_ULL(10) 423 #define CET_WAIT_ENDBR BIT_ULL(11) 424 425 #define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */ 426 #define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */ 427 #define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */ 428 #define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */ 429 #define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */ 430 431 /* Hardware P state interface */ 432 #define MSR_PPERF 0x0000064e 433 #define MSR_PERF_LIMIT_REASONS 0x0000064f 434 #define MSR_PM_ENABLE 0x00000770 435 #define MSR_HWP_CAPABILITIES 0x00000771 436 #define MSR_HWP_REQUEST_PKG 0x00000772 437 #define MSR_HWP_INTERRUPT 0x00000773 438 #define MSR_HWP_REQUEST 0x00000774 439 #define MSR_HWP_STATUS 0x00000777 440 441 /* CPUID.6.EAX */ 442 #define HWP_BASE_BIT (1<<7) 443 #define HWP_NOTIFICATIONS_BIT (1<<8) 444 #define HWP_ACTIVITY_WINDOW_BIT (1<<9) 445 #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 446 #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 447 448 /* IA32_HWP_CAPABILITIES */ 449 #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 450 #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 451 #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 452 #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 453 454 /* IA32_HWP_REQUEST */ 455 #define HWP_MIN_PERF(x) (x & 0xff) 456 #define HWP_MAX_PERF(x) ((x & 0xff) << 8) 457 #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 458 #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 459 #define HWP_EPP_PERFORMANCE 0x00 460 #define HWP_EPP_BALANCE_PERFORMANCE 0x80 461 #define HWP_EPP_BALANCE_POWERSAVE 0xC0 462 #define HWP_EPP_POWERSAVE 0xFF 463 #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 464 #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 465 466 /* IA32_HWP_STATUS */ 467 #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 468 #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 469 470 /* IA32_HWP_INTERRUPT */ 471 #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 472 #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 473 474 #define MSR_AMD64_MC0_MASK 0xc0010044 475 476 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 477 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 478 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 479 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 480 481 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 482 483 /* These are consecutive and not in the normal 4er MCE bank block */ 484 #define MSR_IA32_MC0_CTL2 0x00000280 485 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 486 487 #define MSR_P6_PERFCTR0 0x000000c1 488 #define MSR_P6_PERFCTR1 0x000000c2 489 #define MSR_P6_EVNTSEL0 0x00000186 490 #define MSR_P6_EVNTSEL1 0x00000187 491 492 #define MSR_KNC_PERFCTR0 0x00000020 493 #define MSR_KNC_PERFCTR1 0x00000021 494 #define MSR_KNC_EVNTSEL0 0x00000028 495 #define MSR_KNC_EVNTSEL1 0x00000029 496 497 /* Alternative perfctr range with full access. */ 498 #define MSR_IA32_PMC0 0x000004c1 499 500 /* Auto-reload via MSR instead of DS area */ 501 #define MSR_RELOAD_PMC0 0x000014c1 502 #define MSR_RELOAD_FIXED_CTR0 0x00001309 503 504 /* 505 * AMD64 MSRs. Not complete. See the architecture manual for a more 506 * complete list. 507 */ 508 #define MSR_AMD64_PATCH_LEVEL 0x0000008b 509 #define MSR_AMD64_TSC_RATIO 0xc0000104 510 #define MSR_AMD64_NB_CFG 0xc001001f 511 #define MSR_AMD64_PATCH_LOADER 0xc0010020 512 #define MSR_AMD_PERF_CTL 0xc0010062 513 #define MSR_AMD_PERF_STATUS 0xc0010063 514 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 515 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 516 #define MSR_AMD64_OSVW_STATUS 0xc0010141 517 #define MSR_AMD_PPIN_CTL 0xc00102f0 518 #define MSR_AMD_PPIN 0xc00102f1 519 #define MSR_AMD64_CPUID_FN_1 0xc0011004 520 #define MSR_AMD64_LS_CFG 0xc0011020 521 #define MSR_AMD64_DC_CFG 0xc0011022 522 #define MSR_AMD64_BU_CFG2 0xc001102a 523 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 524 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 525 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 526 #define MSR_AMD64_IBSFETCH_REG_COUNT 3 527 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 528 #define MSR_AMD64_IBSOPCTL 0xc0011033 529 #define MSR_AMD64_IBSOPRIP 0xc0011034 530 #define MSR_AMD64_IBSOPDATA 0xc0011035 531 #define MSR_AMD64_IBSOPDATA2 0xc0011036 532 #define MSR_AMD64_IBSOPDATA3 0xc0011037 533 #define MSR_AMD64_IBSDCLINAD 0xc0011038 534 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 535 #define MSR_AMD64_IBSOP_REG_COUNT 7 536 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 537 #define MSR_AMD64_IBSCTL 0xc001103a 538 #define MSR_AMD64_IBSBRTARGET 0xc001103b 539 #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c 540 #define MSR_AMD64_IBSOPDATA4 0xc001103d 541 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 542 #define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b 543 #define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e 544 #define MSR_AMD64_SEV_ES_GHCB 0xc0010130 545 #define MSR_AMD64_SEV 0xc0010131 546 #define MSR_AMD64_SEV_ENABLED_BIT 0 547 #define MSR_AMD64_SEV_ES_ENABLED_BIT 1 548 #define MSR_AMD64_SEV_SNP_ENABLED_BIT 2 549 #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 550 #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) 551 #define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) 552 553 #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 554 555 /* AMD Collaborative Processor Performance Control MSRs */ 556 #define MSR_AMD_CPPC_CAP1 0xc00102b0 557 #define MSR_AMD_CPPC_ENABLE 0xc00102b1 558 #define MSR_AMD_CPPC_CAP2 0xc00102b2 559 #define MSR_AMD_CPPC_REQ 0xc00102b3 560 #define MSR_AMD_CPPC_STATUS 0xc00102b4 561 562 #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) 563 #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) 564 #define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff) 565 #define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff) 566 567 #define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0) 568 #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) 569 #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) 570 #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) 571 572 /* AMD Performance Counter Global Status and Control MSRs */ 573 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 574 #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 575 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 576 577 /* Fam 17h MSRs */ 578 #define MSR_F17H_IRPERF 0xc00000e9 579 580 #define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 581 #define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1) 582 583 /* Fam 16h MSRs */ 584 #define MSR_F16H_L2I_PERF_CTL 0xc0010230 585 #define MSR_F16H_L2I_PERF_CTR 0xc0010231 586 #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 587 #define MSR_F16H_DR2_ADDR_MASK 0xc001101a 588 #define MSR_F16H_DR3_ADDR_MASK 0xc001101b 589 #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 590 591 /* Fam 15h MSRs */ 592 #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a 593 #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b 594 #define MSR_F15H_PERF_CTL 0xc0010200 595 #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 596 #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 597 #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 598 #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 599 #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 600 #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 601 602 #define MSR_F15H_PERF_CTR 0xc0010201 603 #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 604 #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 605 #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 606 #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 607 #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 608 #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 609 610 #define MSR_F15H_NB_PERF_CTL 0xc0010240 611 #define MSR_F15H_NB_PERF_CTR 0xc0010241 612 #define MSR_F15H_PTSC 0xc0010280 613 #define MSR_F15H_IC_CFG 0xc0011021 614 #define MSR_F15H_EX_CFG 0xc001102c 615 616 /* Fam 10h MSRs */ 617 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 618 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 619 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 620 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 621 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 622 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 623 #define MSR_FAM10H_NODE_ID 0xc001100c 624 #define MSR_F10H_DECFG 0xc0011029 625 #define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 626 #define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT) 627 628 /* K8 MSRs */ 629 #define MSR_K8_TOP_MEM1 0xc001001a 630 #define MSR_K8_TOP_MEM2 0xc001001d 631 #define MSR_AMD64_SYSCFG 0xc0010010 632 #define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23 633 #define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT) 634 #define MSR_K8_INT_PENDING_MSG 0xc0010055 635 /* C1E active bits in int pending message */ 636 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 637 #define MSR_K8_TSEG_ADDR 0xc0010112 638 #define MSR_K8_TSEG_MASK 0xc0010113 639 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 640 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 641 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 642 643 /* K7 MSRs */ 644 #define MSR_K7_EVNTSEL0 0xc0010000 645 #define MSR_K7_PERFCTR0 0xc0010004 646 #define MSR_K7_EVNTSEL1 0xc0010001 647 #define MSR_K7_PERFCTR1 0xc0010005 648 #define MSR_K7_EVNTSEL2 0xc0010002 649 #define MSR_K7_PERFCTR2 0xc0010006 650 #define MSR_K7_EVNTSEL3 0xc0010003 651 #define MSR_K7_PERFCTR3 0xc0010007 652 #define MSR_K7_CLK_CTL 0xc001001b 653 #define MSR_K7_HWCR 0xc0010015 654 #define MSR_K7_HWCR_SMMLOCK_BIT 0 655 #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 656 #define MSR_K7_HWCR_IRPERF_EN_BIT 30 657 #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) 658 #define MSR_K7_FID_VID_CTL 0xc0010041 659 #define MSR_K7_FID_VID_STATUS 0xc0010042 660 661 /* K6 MSRs */ 662 #define MSR_K6_WHCR 0xc0000082 663 #define MSR_K6_UWCCR 0xc0000085 664 #define MSR_K6_EPMR 0xc0000086 665 #define MSR_K6_PSOR 0xc0000087 666 #define MSR_K6_PFIR 0xc0000088 667 668 /* Centaur-Hauls/IDT defined MSRs. */ 669 #define MSR_IDT_FCR1 0x00000107 670 #define MSR_IDT_FCR2 0x00000108 671 #define MSR_IDT_FCR3 0x00000109 672 #define MSR_IDT_FCR4 0x0000010a 673 674 #define MSR_IDT_MCR0 0x00000110 675 #define MSR_IDT_MCR1 0x00000111 676 #define MSR_IDT_MCR2 0x00000112 677 #define MSR_IDT_MCR3 0x00000113 678 #define MSR_IDT_MCR4 0x00000114 679 #define MSR_IDT_MCR5 0x00000115 680 #define MSR_IDT_MCR6 0x00000116 681 #define MSR_IDT_MCR7 0x00000117 682 #define MSR_IDT_MCR_CTRL 0x00000120 683 684 /* VIA Cyrix defined MSRs*/ 685 #define MSR_VIA_FCR 0x00001107 686 #define MSR_VIA_LONGHAUL 0x0000110a 687 #define MSR_VIA_RNG 0x0000110b 688 #define MSR_VIA_BCR2 0x00001147 689 690 /* Transmeta defined MSRs */ 691 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 692 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 693 #define MSR_TMTA_LRTI_READOUT 0x80868018 694 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 695 696 /* Intel defined MSRs. */ 697 #define MSR_IA32_P5_MC_ADDR 0x00000000 698 #define MSR_IA32_P5_MC_TYPE 0x00000001 699 #define MSR_IA32_TSC 0x00000010 700 #define MSR_IA32_PLATFORM_ID 0x00000017 701 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 702 #define MSR_EBC_FREQUENCY_ID 0x0000002c 703 #define MSR_SMI_COUNT 0x00000034 704 705 /* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ 706 #define MSR_IA32_FEAT_CTL 0x0000003a 707 #define FEAT_CTL_LOCKED BIT(0) 708 #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) 709 #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) 710 #define FEAT_CTL_SGX_LC_ENABLED BIT(17) 711 #define FEAT_CTL_SGX_ENABLED BIT(18) 712 #define FEAT_CTL_LMCE_ENABLED BIT(20) 713 714 #define MSR_IA32_TSC_ADJUST 0x0000003b 715 #define MSR_IA32_BNDCFGS 0x00000d90 716 717 #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 718 719 #define MSR_IA32_XFD 0x000001c4 720 #define MSR_IA32_XFD_ERR 0x000001c5 721 #define MSR_IA32_XSS 0x00000da0 722 723 #define MSR_IA32_APICBASE 0x0000001b 724 #define MSR_IA32_APICBASE_BSP (1<<8) 725 #define MSR_IA32_APICBASE_ENABLE (1<<11) 726 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 727 728 #define MSR_IA32_UCODE_WRITE 0x00000079 729 #define MSR_IA32_UCODE_REV 0x0000008b 730 731 /* Intel SGX Launch Enclave Public Key Hash MSRs */ 732 #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C 733 #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D 734 #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E 735 #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F 736 737 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 738 #define MSR_IA32_SMBASE 0x0000009e 739 740 #define MSR_IA32_PERF_STATUS 0x00000198 741 #define MSR_IA32_PERF_CTL 0x00000199 742 #define INTEL_PERF_CTL_MASK 0xffff 743 744 /* AMD Branch Sampling configuration */ 745 #define MSR_AMD_DBG_EXTN_CFG 0xc000010f 746 #define MSR_AMD_SAMP_BR_FROM 0xc0010300 747 748 #define MSR_IA32_MPERF 0x000000e7 749 #define MSR_IA32_APERF 0x000000e8 750 751 #define MSR_IA32_THERM_CONTROL 0x0000019a 752 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 753 754 #define THERM_INT_HIGH_ENABLE (1 << 0) 755 #define THERM_INT_LOW_ENABLE (1 << 1) 756 #define THERM_INT_PLN_ENABLE (1 << 24) 757 758 #define MSR_IA32_THERM_STATUS 0x0000019c 759 760 #define THERM_STATUS_PROCHOT (1 << 0) 761 #define THERM_STATUS_POWER_LIMIT (1 << 10) 762 763 #define MSR_THERM2_CTL 0x0000019d 764 765 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 766 767 #define MSR_IA32_MISC_ENABLE 0x000001a0 768 769 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 770 771 #define MSR_MISC_FEATURE_CONTROL 0x000001a4 772 #define MSR_MISC_PWR_MGMT 0x000001aa 773 774 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 775 #define ENERGY_PERF_BIAS_PERFORMANCE 0 776 #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 777 #define ENERGY_PERF_BIAS_NORMAL 6 778 #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 779 #define ENERGY_PERF_BIAS_POWERSAVE 15 780 781 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 782 783 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 784 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 785 #define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26) 786 787 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 788 789 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 790 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 791 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 792 #define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25) 793 794 /* Thermal Thresholds Support */ 795 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 796 #define THERM_SHIFT_THRESHOLD0 8 797 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 798 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 799 #define THERM_SHIFT_THRESHOLD1 16 800 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 801 #define THERM_STATUS_THRESHOLD0 (1 << 6) 802 #define THERM_LOG_THRESHOLD0 (1 << 7) 803 #define THERM_STATUS_THRESHOLD1 (1 << 8) 804 #define THERM_LOG_THRESHOLD1 (1 << 9) 805 806 /* MISC_ENABLE bits: architectural */ 807 #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 808 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 809 #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 810 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 811 #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 812 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 813 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 814 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 815 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 816 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 817 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 818 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 819 #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 820 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 821 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 822 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 823 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 824 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 825 #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 826 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 827 828 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 829 #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 830 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 831 #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 832 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 833 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 834 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 835 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 836 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 837 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 838 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 839 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 840 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 841 #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 842 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 843 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 844 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 845 #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 846 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 847 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 848 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 849 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 850 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 851 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 852 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 853 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 854 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 855 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 856 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 857 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 858 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 859 860 /* MISC_FEATURES_ENABLES non-architectural features */ 861 #define MSR_MISC_FEATURES_ENABLES 0x00000140 862 863 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 864 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 865 #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 866 867 #define MSR_IA32_TSC_DEADLINE 0x000006E0 868 869 870 #define MSR_TSX_FORCE_ABORT 0x0000010F 871 872 #define MSR_TFA_RTM_FORCE_ABORT_BIT 0 873 #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) 874 #define MSR_TFA_TSX_CPUID_CLEAR_BIT 1 875 #define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT) 876 #define MSR_TFA_SDV_ENABLE_RTM_BIT 2 877 #define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT) 878 879 /* P4/Xeon+ specific */ 880 #define MSR_IA32_MCG_EAX 0x00000180 881 #define MSR_IA32_MCG_EBX 0x00000181 882 #define MSR_IA32_MCG_ECX 0x00000182 883 #define MSR_IA32_MCG_EDX 0x00000183 884 #define MSR_IA32_MCG_ESI 0x00000184 885 #define MSR_IA32_MCG_EDI 0x00000185 886 #define MSR_IA32_MCG_EBP 0x00000186 887 #define MSR_IA32_MCG_ESP 0x00000187 888 #define MSR_IA32_MCG_EFLAGS 0x00000188 889 #define MSR_IA32_MCG_EIP 0x00000189 890 #define MSR_IA32_MCG_RESERVED 0x0000018a 891 892 /* Pentium IV performance counter MSRs */ 893 #define MSR_P4_BPU_PERFCTR0 0x00000300 894 #define MSR_P4_BPU_PERFCTR1 0x00000301 895 #define MSR_P4_BPU_PERFCTR2 0x00000302 896 #define MSR_P4_BPU_PERFCTR3 0x00000303 897 #define MSR_P4_MS_PERFCTR0 0x00000304 898 #define MSR_P4_MS_PERFCTR1 0x00000305 899 #define MSR_P4_MS_PERFCTR2 0x00000306 900 #define MSR_P4_MS_PERFCTR3 0x00000307 901 #define MSR_P4_FLAME_PERFCTR0 0x00000308 902 #define MSR_P4_FLAME_PERFCTR1 0x00000309 903 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 904 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 905 #define MSR_P4_IQ_PERFCTR0 0x0000030c 906 #define MSR_P4_IQ_PERFCTR1 0x0000030d 907 #define MSR_P4_IQ_PERFCTR2 0x0000030e 908 #define MSR_P4_IQ_PERFCTR3 0x0000030f 909 #define MSR_P4_IQ_PERFCTR4 0x00000310 910 #define MSR_P4_IQ_PERFCTR5 0x00000311 911 #define MSR_P4_BPU_CCCR0 0x00000360 912 #define MSR_P4_BPU_CCCR1 0x00000361 913 #define MSR_P4_BPU_CCCR2 0x00000362 914 #define MSR_P4_BPU_CCCR3 0x00000363 915 #define MSR_P4_MS_CCCR0 0x00000364 916 #define MSR_P4_MS_CCCR1 0x00000365 917 #define MSR_P4_MS_CCCR2 0x00000366 918 #define MSR_P4_MS_CCCR3 0x00000367 919 #define MSR_P4_FLAME_CCCR0 0x00000368 920 #define MSR_P4_FLAME_CCCR1 0x00000369 921 #define MSR_P4_FLAME_CCCR2 0x0000036a 922 #define MSR_P4_FLAME_CCCR3 0x0000036b 923 #define MSR_P4_IQ_CCCR0 0x0000036c 924 #define MSR_P4_IQ_CCCR1 0x0000036d 925 #define MSR_P4_IQ_CCCR2 0x0000036e 926 #define MSR_P4_IQ_CCCR3 0x0000036f 927 #define MSR_P4_IQ_CCCR4 0x00000370 928 #define MSR_P4_IQ_CCCR5 0x00000371 929 #define MSR_P4_ALF_ESCR0 0x000003ca 930 #define MSR_P4_ALF_ESCR1 0x000003cb 931 #define MSR_P4_BPU_ESCR0 0x000003b2 932 #define MSR_P4_BPU_ESCR1 0x000003b3 933 #define MSR_P4_BSU_ESCR0 0x000003a0 934 #define MSR_P4_BSU_ESCR1 0x000003a1 935 #define MSR_P4_CRU_ESCR0 0x000003b8 936 #define MSR_P4_CRU_ESCR1 0x000003b9 937 #define MSR_P4_CRU_ESCR2 0x000003cc 938 #define MSR_P4_CRU_ESCR3 0x000003cd 939 #define MSR_P4_CRU_ESCR4 0x000003e0 940 #define MSR_P4_CRU_ESCR5 0x000003e1 941 #define MSR_P4_DAC_ESCR0 0x000003a8 942 #define MSR_P4_DAC_ESCR1 0x000003a9 943 #define MSR_P4_FIRM_ESCR0 0x000003a4 944 #define MSR_P4_FIRM_ESCR1 0x000003a5 945 #define MSR_P4_FLAME_ESCR0 0x000003a6 946 #define MSR_P4_FLAME_ESCR1 0x000003a7 947 #define MSR_P4_FSB_ESCR0 0x000003a2 948 #define MSR_P4_FSB_ESCR1 0x000003a3 949 #define MSR_P4_IQ_ESCR0 0x000003ba 950 #define MSR_P4_IQ_ESCR1 0x000003bb 951 #define MSR_P4_IS_ESCR0 0x000003b4 952 #define MSR_P4_IS_ESCR1 0x000003b5 953 #define MSR_P4_ITLB_ESCR0 0x000003b6 954 #define MSR_P4_ITLB_ESCR1 0x000003b7 955 #define MSR_P4_IX_ESCR0 0x000003c8 956 #define MSR_P4_IX_ESCR1 0x000003c9 957 #define MSR_P4_MOB_ESCR0 0x000003aa 958 #define MSR_P4_MOB_ESCR1 0x000003ab 959 #define MSR_P4_MS_ESCR0 0x000003c0 960 #define MSR_P4_MS_ESCR1 0x000003c1 961 #define MSR_P4_PMH_ESCR0 0x000003ac 962 #define MSR_P4_PMH_ESCR1 0x000003ad 963 #define MSR_P4_RAT_ESCR0 0x000003bc 964 #define MSR_P4_RAT_ESCR1 0x000003bd 965 #define MSR_P4_SAAT_ESCR0 0x000003ae 966 #define MSR_P4_SAAT_ESCR1 0x000003af 967 #define MSR_P4_SSU_ESCR0 0x000003be 968 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 969 970 #define MSR_P4_TBPU_ESCR0 0x000003c2 971 #define MSR_P4_TBPU_ESCR1 0x000003c3 972 #define MSR_P4_TC_ESCR0 0x000003c4 973 #define MSR_P4_TC_ESCR1 0x000003c5 974 #define MSR_P4_U2L_ESCR0 0x000003b0 975 #define MSR_P4_U2L_ESCR1 0x000003b1 976 977 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 978 979 /* Intel Core-based CPU performance counters */ 980 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 981 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 982 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 983 #define MSR_CORE_PERF_FIXED_CTR3 0x0000030c 984 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 985 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 986 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 987 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 988 989 #define MSR_PERF_METRICS 0x00000329 990 991 /* PERF_GLOBAL_OVF_CTL bits */ 992 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 993 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) 994 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 995 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) 996 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 997 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) 998 999 /* Geode defined MSRs */ 1000 #define MSR_GEODE_BUSCONT_CONF0 0x00001900 1001 1002 /* Intel VT MSRs */ 1003 #define MSR_IA32_VMX_BASIC 0x00000480 1004 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 1005 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 1006 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 1007 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 1008 #define MSR_IA32_VMX_MISC 0x00000485 1009 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 1010 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 1011 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 1012 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 1013 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 1014 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 1015 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 1016 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 1017 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 1018 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 1019 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 1020 #define MSR_IA32_VMX_VMFUNC 0x00000491 1021 1022 /* VMX_BASIC bits and bitmasks */ 1023 #define VMX_BASIC_VMCS_SIZE_SHIFT 32 1024 #define VMX_BASIC_TRUE_CTLS (1ULL << 55) 1025 #define VMX_BASIC_64 0x0001000000000000LLU 1026 #define VMX_BASIC_MEM_TYPE_SHIFT 50 1027 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 1028 #define VMX_BASIC_MEM_TYPE_WB 6LLU 1029 #define VMX_BASIC_INOUT 0x0040000000000000LLU 1030 1031 /* MSR_IA32_VMX_MISC bits */ 1032 #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) 1033 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 1034 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 1035 /* AMD-V MSRs */ 1036 1037 #define MSR_VM_CR 0xc0010114 1038 #define MSR_VM_IGNNE 0xc0010115 1039 #define MSR_VM_HSAVE_PA 0xc0010117 1040 1041 /* Hardware Feedback Interface */ 1042 #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 1043 #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 1044 1045 #endif /* _ASM_X86_MSR_INDEX_H */ 1046