1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_SPECIAL_INSNS_H 3 #define _ASM_X86_SPECIAL_INSNS_H 4 5 6 #ifdef __KERNEL__ 7 8 #include <asm/nops.h> 9 #include <asm/processor-flags.h> 10 #include <linux/irqflags.h> 11 #include <linux/jump_label.h> 12 13 /* 14 * The compiler should not reorder volatile asm statements with respect to each 15 * other: they should execute in program order. However GCC 4.9.x and 5.x have 16 * a bug (which was fixed in 8.1, 7.3 and 6.5) where they might reorder 17 * volatile asm. The write functions are not affected since they have memory 18 * clobbers preventing reordering. To prevent reads from being reordered with 19 * respect to writes, use a dummy memory operand. 20 */ 21 22 #define __FORCE_ORDER "m"(*(unsigned int *)0x1000UL) 23 24 void native_write_cr0(unsigned long val); 25 26 static inline unsigned long native_read_cr0(void) 27 { 28 unsigned long val; 29 asm volatile("mov %%cr0,%0\n\t" : "=r" (val) : __FORCE_ORDER); 30 return val; 31 } 32 33 static __always_inline unsigned long native_read_cr2(void) 34 { 35 unsigned long val; 36 asm volatile("mov %%cr2,%0\n\t" : "=r" (val) : __FORCE_ORDER); 37 return val; 38 } 39 40 static __always_inline void native_write_cr2(unsigned long val) 41 { 42 asm volatile("mov %0,%%cr2": : "r" (val) : "memory"); 43 } 44 45 static inline unsigned long __native_read_cr3(void) 46 { 47 unsigned long val; 48 asm volatile("mov %%cr3,%0\n\t" : "=r" (val) : __FORCE_ORDER); 49 return val; 50 } 51 52 static inline void native_write_cr3(unsigned long val) 53 { 54 asm volatile("mov %0,%%cr3": : "r" (val) : "memory"); 55 } 56 57 static inline unsigned long native_read_cr4(void) 58 { 59 unsigned long val; 60 #ifdef CONFIG_X86_32 61 /* 62 * This could fault if CR4 does not exist. Non-existent CR4 63 * is functionally equivalent to CR4 == 0. Keep it simple and pretend 64 * that CR4 == 0 on CPUs that don't have CR4. 65 */ 66 asm volatile("1: mov %%cr4, %0\n" 67 "2:\n" 68 _ASM_EXTABLE(1b, 2b) 69 : "=r" (val) : "0" (0), __FORCE_ORDER); 70 #else 71 /* CR4 always exists on x86_64. */ 72 asm volatile("mov %%cr4,%0\n\t" : "=r" (val) : __FORCE_ORDER); 73 #endif 74 return val; 75 } 76 77 void native_write_cr4(unsigned long val); 78 79 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 80 static inline u32 rdpkru(void) 81 { 82 u32 ecx = 0; 83 u32 edx, pkru; 84 85 /* 86 * "rdpkru" instruction. Places PKRU contents in to EAX, 87 * clears EDX and requires that ecx=0. 88 */ 89 asm volatile(".byte 0x0f,0x01,0xee\n\t" 90 : "=a" (pkru), "=d" (edx) 91 : "c" (ecx)); 92 return pkru; 93 } 94 95 static inline void wrpkru(u32 pkru) 96 { 97 u32 ecx = 0, edx = 0; 98 99 /* 100 * "wrpkru" instruction. Loads contents in EAX to PKRU, 101 * requires that ecx = edx = 0. 102 */ 103 asm volatile(".byte 0x0f,0x01,0xef\n\t" 104 : : "a" (pkru), "c"(ecx), "d"(edx)); 105 } 106 107 #else 108 static inline u32 rdpkru(void) 109 { 110 return 0; 111 } 112 113 static inline void wrpkru(u32 pkru) 114 { 115 } 116 #endif 117 118 static inline void native_wbinvd(void) 119 { 120 asm volatile("wbinvd": : :"memory"); 121 } 122 123 extern asmlinkage void asm_load_gs_index(unsigned int selector); 124 125 static inline void native_load_gs_index(unsigned int selector) 126 { 127 unsigned long flags; 128 129 local_irq_save(flags); 130 asm_load_gs_index(selector); 131 local_irq_restore(flags); 132 } 133 134 static inline unsigned long __read_cr4(void) 135 { 136 return native_read_cr4(); 137 } 138 139 #ifdef CONFIG_PARAVIRT_XXL 140 #include <asm/paravirt.h> 141 #else 142 143 static inline unsigned long read_cr0(void) 144 { 145 return native_read_cr0(); 146 } 147 148 static inline void write_cr0(unsigned long x) 149 { 150 native_write_cr0(x); 151 } 152 153 static __always_inline unsigned long read_cr2(void) 154 { 155 return native_read_cr2(); 156 } 157 158 static __always_inline void write_cr2(unsigned long x) 159 { 160 native_write_cr2(x); 161 } 162 163 /* 164 * Careful! CR3 contains more than just an address. You probably want 165 * read_cr3_pa() instead. 166 */ 167 static inline unsigned long __read_cr3(void) 168 { 169 return __native_read_cr3(); 170 } 171 172 static inline void write_cr3(unsigned long x) 173 { 174 native_write_cr3(x); 175 } 176 177 static inline void __write_cr4(unsigned long x) 178 { 179 native_write_cr4(x); 180 } 181 182 static inline void wbinvd(void) 183 { 184 native_wbinvd(); 185 } 186 187 188 static inline void load_gs_index(unsigned int selector) 189 { 190 #ifdef CONFIG_X86_64 191 native_load_gs_index(selector); 192 #else 193 loadsegment(gs, selector); 194 #endif 195 } 196 197 #endif /* CONFIG_PARAVIRT_XXL */ 198 199 static inline void clflush(volatile void *__p) 200 { 201 asm volatile("clflush %0" : "+m" (*(volatile char __force *)__p)); 202 } 203 204 static inline void clflushopt(volatile void *__p) 205 { 206 alternative_io(".byte 0x3e; clflush %P0", 207 ".byte 0x66; clflush %P0", 208 X86_FEATURE_CLFLUSHOPT, 209 "+m" (*(volatile char __force *)__p)); 210 } 211 212 static inline void clwb(volatile void *__p) 213 { 214 volatile struct { char x[64]; } *p = __p; 215 216 asm volatile(ALTERNATIVE_2( 217 ".byte 0x3e; clflush (%[pax])", 218 ".byte 0x66; clflush (%[pax])", /* clflushopt (%%rax) */ 219 X86_FEATURE_CLFLUSHOPT, 220 ".byte 0x66, 0x0f, 0xae, 0x30", /* clwb (%%rax) */ 221 X86_FEATURE_CLWB) 222 : [p] "+m" (*p) 223 : [pax] "a" (p)); 224 } 225 226 #define nop() asm volatile ("nop") 227 228 static inline void serialize(void) 229 { 230 /* Instruction opcode for SERIALIZE; supported in binutils >= 2.35. */ 231 asm volatile(".byte 0xf, 0x1, 0xe8" ::: "memory"); 232 } 233 234 /* The dst parameter must be 64-bytes aligned */ 235 static inline void movdir64b(void __iomem *dst, const void *src) 236 { 237 const struct { char _[64]; } *__src = src; 238 struct { char _[64]; } __iomem *__dst = dst; 239 240 /* 241 * MOVDIR64B %(rdx), rax. 242 * 243 * Both __src and __dst must be memory constraints in order to tell the 244 * compiler that no other memory accesses should be reordered around 245 * this one. 246 * 247 * Also, both must be supplied as lvalues because this tells 248 * the compiler what the object is (its size) the instruction accesses. 249 * I.e., not the pointers but what they point to, thus the deref'ing '*'. 250 */ 251 asm volatile(".byte 0x66, 0x0f, 0x38, 0xf8, 0x02" 252 : "+m" (*__dst) 253 : "m" (*__src), "a" (__dst), "d" (__src)); 254 } 255 256 /** 257 * enqcmds - Enqueue a command in supervisor (CPL0) mode 258 * @dst: destination, in MMIO space (must be 512-bit aligned) 259 * @src: 512 bits memory operand 260 * 261 * The ENQCMDS instruction allows software to write a 512-bit command to 262 * a 512-bit-aligned special MMIO region that supports the instruction. 263 * A return status is loaded into the ZF flag in the RFLAGS register. 264 * ZF = 0 equates to success, and ZF = 1 indicates retry or error. 265 * 266 * This function issues the ENQCMDS instruction to submit data from 267 * kernel space to MMIO space, in a unit of 512 bits. Order of data access 268 * is not guaranteed, nor is a memory barrier performed afterwards. It 269 * returns 0 on success and -EAGAIN on failure. 270 * 271 * Warning: Do not use this helper unless your driver has checked that the 272 * ENQCMDS instruction is supported on the platform and the device accepts 273 * ENQCMDS. 274 */ 275 static inline int enqcmds(void __iomem *dst, const void *src) 276 { 277 const struct { char _[64]; } *__src = src; 278 struct { char _[64]; } __iomem *__dst = dst; 279 bool zf; 280 281 /* 282 * ENQCMDS %(rdx), rax 283 * 284 * See movdir64b()'s comment on operand specification. 285 */ 286 asm volatile(".byte 0xf3, 0x0f, 0x38, 0xf8, 0x02, 0x66, 0x90" 287 CC_SET(z) 288 : CC_OUT(z) (zf), "+m" (*__dst) 289 : "m" (*__src), "a" (__dst), "d" (__src)); 290 291 /* Submission failure is indicated via EFLAGS.ZF=1 */ 292 if (zf) 293 return -EAGAIN; 294 295 return 0; 296 } 297 298 static inline void tile_release(void) 299 { 300 /* 301 * Instruction opcode for TILERELEASE; supported in binutils 302 * version >= 2.36. 303 */ 304 asm volatile(".byte 0xc4, 0xe2, 0x78, 0x49, 0xc0"); 305 } 306 307 #endif /* __KERNEL__ */ 308 309 #endif /* _ASM_X86_SPECIAL_INSNS_H */ 310