1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Resource Director Technology(RDT) 4 * - Cache Allocation code. 5 * 6 * Copyright (C) 2016 Intel Corporation 7 * 8 * Authors: 9 * Fenghua Yu <fenghua.yu@intel.com> 10 * Tony Luck <tony.luck@intel.com> 11 * Vikas Shivappa <vikas.shivappa@intel.com> 12 * 13 * More information about RDT be found in the Intel (R) x86 Architecture 14 * Software Developer Manual June 2016, volume 3, section 17.17. 15 */ 16 17 #define pr_fmt(fmt) "resctrl: " fmt 18 19 #include <linux/slab.h> 20 #include <linux/err.h> 21 #include <linux/cacheinfo.h> 22 #include <linux/cpuhotplug.h> 23 24 #include <asm/intel-family.h> 25 #include <asm/resctrl.h> 26 #include "internal.h" 27 28 /* Mutex to protect rdtgroup access. */ 29 DEFINE_MUTEX(rdtgroup_mutex); 30 31 /* 32 * The cached resctrl_pqr_state is strictly per CPU and can never be 33 * updated from a remote CPU. Functions which modify the state 34 * are called with interrupts disabled and no preemption, which 35 * is sufficient for the protection. 36 */ 37 DEFINE_PER_CPU(struct resctrl_pqr_state, pqr_state); 38 39 /* 40 * Used to store the max resource name width and max resource data width 41 * to display the schemata in a tabular format 42 */ 43 int max_name_width, max_data_width; 44 45 /* 46 * Global boolean for rdt_alloc which is true if any 47 * resource allocation is enabled. 48 */ 49 bool rdt_alloc_capable; 50 51 static void 52 mba_wrmsr_intel(struct rdt_domain *d, struct msr_param *m, 53 struct rdt_resource *r); 54 static void 55 cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r); 56 static void 57 mba_wrmsr_amd(struct rdt_domain *d, struct msr_param *m, 58 struct rdt_resource *r); 59 60 #define domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].r_resctrl.domains) 61 62 struct rdt_hw_resource rdt_resources_all[] = { 63 [RDT_RESOURCE_L3] = 64 { 65 .r_resctrl = { 66 .rid = RDT_RESOURCE_L3, 67 .name = "L3", 68 .cache_level = 3, 69 .domains = domain_init(RDT_RESOURCE_L3), 70 .parse_ctrlval = parse_cbm, 71 .format_str = "%d=%0*x", 72 .fflags = RFTYPE_RES_CACHE, 73 }, 74 .msr_base = MSR_IA32_L3_CBM_BASE, 75 .msr_update = cat_wrmsr, 76 }, 77 [RDT_RESOURCE_L2] = 78 { 79 .r_resctrl = { 80 .rid = RDT_RESOURCE_L2, 81 .name = "L2", 82 .cache_level = 2, 83 .domains = domain_init(RDT_RESOURCE_L2), 84 .parse_ctrlval = parse_cbm, 85 .format_str = "%d=%0*x", 86 .fflags = RFTYPE_RES_CACHE, 87 }, 88 .msr_base = MSR_IA32_L2_CBM_BASE, 89 .msr_update = cat_wrmsr, 90 }, 91 [RDT_RESOURCE_MBA] = 92 { 93 .r_resctrl = { 94 .rid = RDT_RESOURCE_MBA, 95 .name = "MB", 96 .cache_level = 3, 97 .domains = domain_init(RDT_RESOURCE_MBA), 98 .parse_ctrlval = parse_bw, 99 .format_str = "%d=%*u", 100 .fflags = RFTYPE_RES_MB, 101 }, 102 }, 103 }; 104 105 /* 106 * cache_alloc_hsw_probe() - Have to probe for Intel haswell server CPUs 107 * as they do not have CPUID enumeration support for Cache allocation. 108 * The check for Vendor/Family/Model is not enough to guarantee that 109 * the MSRs won't #GP fault because only the following SKUs support 110 * CAT: 111 * Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz 112 * Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz 113 * Intel(R) Xeon(R) CPU E5-2628L v3 @ 2.00GHz 114 * Intel(R) Xeon(R) CPU E5-2618L v3 @ 2.30GHz 115 * Intel(R) Xeon(R) CPU E5-2608L v3 @ 2.00GHz 116 * Intel(R) Xeon(R) CPU E5-2658A v3 @ 2.20GHz 117 * 118 * Probe by trying to write the first of the L3 cache mask registers 119 * and checking that the bits stick. Max CLOSids is always 4 and max cbm length 120 * is always 20 on hsw server parts. The minimum cache bitmask length 121 * allowed for HSW server is always 2 bits. Hardcode all of them. 122 */ 123 static inline void cache_alloc_hsw_probe(void) 124 { 125 struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_L3]; 126 struct rdt_resource *r = &hw_res->r_resctrl; 127 u32 l, h, max_cbm = BIT_MASK(20) - 1; 128 129 if (wrmsr_safe(MSR_IA32_L3_CBM_BASE, max_cbm, 0)) 130 return; 131 132 rdmsr(MSR_IA32_L3_CBM_BASE, l, h); 133 134 /* If all the bits were set in MSR, return success */ 135 if (l != max_cbm) 136 return; 137 138 hw_res->num_closid = 4; 139 r->default_ctrl = max_cbm; 140 r->cache.cbm_len = 20; 141 r->cache.shareable_bits = 0xc0000; 142 r->cache.min_cbm_bits = 2; 143 r->alloc_capable = true; 144 145 rdt_alloc_capable = true; 146 } 147 148 bool is_mba_sc(struct rdt_resource *r) 149 { 150 if (!r) 151 return rdt_resources_all[RDT_RESOURCE_MBA].r_resctrl.membw.mba_sc; 152 153 return r->membw.mba_sc; 154 } 155 156 /* 157 * rdt_get_mb_table() - get a mapping of bandwidth(b/w) percentage values 158 * exposed to user interface and the h/w understandable delay values. 159 * 160 * The non-linear delay values have the granularity of power of two 161 * and also the h/w does not guarantee a curve for configured delay 162 * values vs. actual b/w enforced. 163 * Hence we need a mapping that is pre calibrated so the user can 164 * express the memory b/w as a percentage value. 165 */ 166 static inline bool rdt_get_mb_table(struct rdt_resource *r) 167 { 168 /* 169 * There are no Intel SKUs as of now to support non-linear delay. 170 */ 171 pr_info("MBA b/w map not implemented for cpu:%d, model:%d", 172 boot_cpu_data.x86, boot_cpu_data.x86_model); 173 174 return false; 175 } 176 177 static bool __get_mem_config_intel(struct rdt_resource *r) 178 { 179 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 180 union cpuid_0x10_3_eax eax; 181 union cpuid_0x10_x_edx edx; 182 u32 ebx, ecx, max_delay; 183 184 cpuid_count(0x00000010, 3, &eax.full, &ebx, &ecx, &edx.full); 185 hw_res->num_closid = edx.split.cos_max + 1; 186 max_delay = eax.split.max_delay + 1; 187 r->default_ctrl = MAX_MBA_BW; 188 r->membw.arch_needs_linear = true; 189 if (ecx & MBA_IS_LINEAR) { 190 r->membw.delay_linear = true; 191 r->membw.min_bw = MAX_MBA_BW - max_delay; 192 r->membw.bw_gran = MAX_MBA_BW - max_delay; 193 } else { 194 if (!rdt_get_mb_table(r)) 195 return false; 196 r->membw.arch_needs_linear = false; 197 } 198 r->data_width = 3; 199 200 if (boot_cpu_has(X86_FEATURE_PER_THREAD_MBA)) 201 r->membw.throttle_mode = THREAD_THROTTLE_PER_THREAD; 202 else 203 r->membw.throttle_mode = THREAD_THROTTLE_MAX; 204 thread_throttle_mode_init(); 205 206 r->alloc_capable = true; 207 208 return true; 209 } 210 211 static bool __rdt_get_mem_config_amd(struct rdt_resource *r) 212 { 213 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 214 union cpuid_0x10_3_eax eax; 215 union cpuid_0x10_x_edx edx; 216 u32 ebx, ecx; 217 218 cpuid_count(0x80000020, 1, &eax.full, &ebx, &ecx, &edx.full); 219 hw_res->num_closid = edx.split.cos_max + 1; 220 r->default_ctrl = MAX_MBA_BW_AMD; 221 222 /* AMD does not use delay */ 223 r->membw.delay_linear = false; 224 r->membw.arch_needs_linear = false; 225 226 /* 227 * AMD does not use memory delay throttle model to control 228 * the allocation like Intel does. 229 */ 230 r->membw.throttle_mode = THREAD_THROTTLE_UNDEFINED; 231 r->membw.min_bw = 0; 232 r->membw.bw_gran = 1; 233 /* Max value is 2048, Data width should be 4 in decimal */ 234 r->data_width = 4; 235 236 r->alloc_capable = true; 237 238 return true; 239 } 240 241 static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r) 242 { 243 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 244 union cpuid_0x10_1_eax eax; 245 union cpuid_0x10_x_edx edx; 246 u32 ebx, ecx; 247 248 cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx, &edx.full); 249 hw_res->num_closid = edx.split.cos_max + 1; 250 r->cache.cbm_len = eax.split.cbm_len + 1; 251 r->default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1; 252 r->cache.shareable_bits = ebx & r->default_ctrl; 253 r->data_width = (r->cache.cbm_len + 3) / 4; 254 r->alloc_capable = true; 255 } 256 257 static void rdt_get_cdp_config(int level) 258 { 259 /* 260 * By default, CDP is disabled. CDP can be enabled by mount parameter 261 * "cdp" during resctrl file system mount time. 262 */ 263 rdt_resources_all[level].cdp_enabled = false; 264 rdt_resources_all[level].r_resctrl.cdp_capable = true; 265 } 266 267 static void rdt_get_cdp_l3_config(void) 268 { 269 rdt_get_cdp_config(RDT_RESOURCE_L3); 270 } 271 272 static void rdt_get_cdp_l2_config(void) 273 { 274 rdt_get_cdp_config(RDT_RESOURCE_L2); 275 } 276 277 static void 278 mba_wrmsr_amd(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r) 279 { 280 unsigned int i; 281 struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d); 282 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 283 284 for (i = m->low; i < m->high; i++) 285 wrmsrl(hw_res->msr_base + i, hw_dom->ctrl_val[i]); 286 } 287 288 /* 289 * Map the memory b/w percentage value to delay values 290 * that can be written to QOS_MSRs. 291 * There are currently no SKUs which support non linear delay values. 292 */ 293 static u32 delay_bw_map(unsigned long bw, struct rdt_resource *r) 294 { 295 if (r->membw.delay_linear) 296 return MAX_MBA_BW - bw; 297 298 pr_warn_once("Non Linear delay-bw map not supported but queried\n"); 299 return r->default_ctrl; 300 } 301 302 static void 303 mba_wrmsr_intel(struct rdt_domain *d, struct msr_param *m, 304 struct rdt_resource *r) 305 { 306 unsigned int i; 307 struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d); 308 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 309 310 /* Write the delay values for mba. */ 311 for (i = m->low; i < m->high; i++) 312 wrmsrl(hw_res->msr_base + i, delay_bw_map(hw_dom->ctrl_val[i], r)); 313 } 314 315 static void 316 cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r) 317 { 318 unsigned int i; 319 struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d); 320 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 321 322 for (i = m->low; i < m->high; i++) 323 wrmsrl(hw_res->msr_base + i, hw_dom->ctrl_val[i]); 324 } 325 326 struct rdt_domain *get_domain_from_cpu(int cpu, struct rdt_resource *r) 327 { 328 struct rdt_domain *d; 329 330 list_for_each_entry(d, &r->domains, list) { 331 /* Find the domain that contains this CPU */ 332 if (cpumask_test_cpu(cpu, &d->cpu_mask)) 333 return d; 334 } 335 336 return NULL; 337 } 338 339 u32 resctrl_arch_get_num_closid(struct rdt_resource *r) 340 { 341 return resctrl_to_arch_res(r)->num_closid; 342 } 343 344 void rdt_ctrl_update(void *arg) 345 { 346 struct msr_param *m = arg; 347 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res); 348 struct rdt_resource *r = m->res; 349 int cpu = smp_processor_id(); 350 struct rdt_domain *d; 351 352 d = get_domain_from_cpu(cpu, r); 353 if (d) { 354 hw_res->msr_update(d, m, r); 355 return; 356 } 357 pr_warn_once("cpu %d not found in any domain for resource %s\n", 358 cpu, r->name); 359 } 360 361 /* 362 * rdt_find_domain - Find a domain in a resource that matches input resource id 363 * 364 * Search resource r's domain list to find the resource id. If the resource 365 * id is found in a domain, return the domain. Otherwise, if requested by 366 * caller, return the first domain whose id is bigger than the input id. 367 * The domain list is sorted by id in ascending order. 368 */ 369 struct rdt_domain *rdt_find_domain(struct rdt_resource *r, int id, 370 struct list_head **pos) 371 { 372 struct rdt_domain *d; 373 struct list_head *l; 374 375 if (id < 0) 376 return ERR_PTR(-ENODEV); 377 378 list_for_each(l, &r->domains) { 379 d = list_entry(l, struct rdt_domain, list); 380 /* When id is found, return its domain. */ 381 if (id == d->id) 382 return d; 383 /* Stop searching when finding id's position in sorted list. */ 384 if (id < d->id) 385 break; 386 } 387 388 if (pos) 389 *pos = l; 390 391 return NULL; 392 } 393 394 static void setup_default_ctrlval(struct rdt_resource *r, u32 *dc) 395 { 396 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 397 int i; 398 399 /* 400 * Initialize the Control MSRs to having no control. 401 * For Cache Allocation: Set all bits in cbm 402 * For Memory Allocation: Set b/w requested to 100% 403 */ 404 for (i = 0; i < hw_res->num_closid; i++, dc++) 405 *dc = r->default_ctrl; 406 } 407 408 static void domain_free(struct rdt_hw_domain *hw_dom) 409 { 410 kfree(hw_dom->arch_mbm_total); 411 kfree(hw_dom->arch_mbm_local); 412 kfree(hw_dom->ctrl_val); 413 kfree(hw_dom); 414 } 415 416 static int domain_setup_ctrlval(struct rdt_resource *r, struct rdt_domain *d) 417 { 418 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 419 struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d); 420 struct msr_param m; 421 u32 *dc; 422 423 dc = kmalloc_array(hw_res->num_closid, sizeof(*hw_dom->ctrl_val), 424 GFP_KERNEL); 425 if (!dc) 426 return -ENOMEM; 427 428 hw_dom->ctrl_val = dc; 429 setup_default_ctrlval(r, dc); 430 431 m.low = 0; 432 m.high = hw_res->num_closid; 433 hw_res->msr_update(d, &m, r); 434 return 0; 435 } 436 437 /** 438 * arch_domain_mbm_alloc() - Allocate arch private storage for the MBM counters 439 * @num_rmid: The size of the MBM counter array 440 * @hw_dom: The domain that owns the allocated arrays 441 */ 442 static int arch_domain_mbm_alloc(u32 num_rmid, struct rdt_hw_domain *hw_dom) 443 { 444 size_t tsize; 445 446 if (is_mbm_total_enabled()) { 447 tsize = sizeof(*hw_dom->arch_mbm_total); 448 hw_dom->arch_mbm_total = kcalloc(num_rmid, tsize, GFP_KERNEL); 449 if (!hw_dom->arch_mbm_total) 450 return -ENOMEM; 451 } 452 if (is_mbm_local_enabled()) { 453 tsize = sizeof(*hw_dom->arch_mbm_local); 454 hw_dom->arch_mbm_local = kcalloc(num_rmid, tsize, GFP_KERNEL); 455 if (!hw_dom->arch_mbm_local) { 456 kfree(hw_dom->arch_mbm_total); 457 hw_dom->arch_mbm_total = NULL; 458 return -ENOMEM; 459 } 460 } 461 462 return 0; 463 } 464 465 /* 466 * domain_add_cpu - Add a cpu to a resource's domain list. 467 * 468 * If an existing domain in the resource r's domain list matches the cpu's 469 * resource id, add the cpu in the domain. 470 * 471 * Otherwise, a new domain is allocated and inserted into the right position 472 * in the domain list sorted by id in ascending order. 473 * 474 * The order in the domain list is visible to users when we print entries 475 * in the schemata file and schemata input is validated to have the same order 476 * as this list. 477 */ 478 static void domain_add_cpu(int cpu, struct rdt_resource *r) 479 { 480 int id = get_cpu_cacheinfo_id(cpu, r->cache_level); 481 struct list_head *add_pos = NULL; 482 struct rdt_hw_domain *hw_dom; 483 struct rdt_domain *d; 484 int err; 485 486 d = rdt_find_domain(r, id, &add_pos); 487 if (IS_ERR(d)) { 488 pr_warn("Couldn't find cache id for CPU %d\n", cpu); 489 return; 490 } 491 492 if (d) { 493 cpumask_set_cpu(cpu, &d->cpu_mask); 494 if (r->cache.arch_has_per_cpu_cfg) 495 rdt_domain_reconfigure_cdp(r); 496 return; 497 } 498 499 hw_dom = kzalloc_node(sizeof(*hw_dom), GFP_KERNEL, cpu_to_node(cpu)); 500 if (!hw_dom) 501 return; 502 503 d = &hw_dom->d_resctrl; 504 d->id = id; 505 cpumask_set_cpu(cpu, &d->cpu_mask); 506 507 rdt_domain_reconfigure_cdp(r); 508 509 if (r->alloc_capable && domain_setup_ctrlval(r, d)) { 510 domain_free(hw_dom); 511 return; 512 } 513 514 if (r->mon_capable && arch_domain_mbm_alloc(r->num_rmid, hw_dom)) { 515 domain_free(hw_dom); 516 return; 517 } 518 519 list_add_tail(&d->list, add_pos); 520 521 err = resctrl_online_domain(r, d); 522 if (err) { 523 list_del(&d->list); 524 domain_free(hw_dom); 525 } 526 } 527 528 static void domain_remove_cpu(int cpu, struct rdt_resource *r) 529 { 530 int id = get_cpu_cacheinfo_id(cpu, r->cache_level); 531 struct rdt_hw_domain *hw_dom; 532 struct rdt_domain *d; 533 534 d = rdt_find_domain(r, id, NULL); 535 if (IS_ERR_OR_NULL(d)) { 536 pr_warn("Couldn't find cache id for CPU %d\n", cpu); 537 return; 538 } 539 hw_dom = resctrl_to_arch_dom(d); 540 541 cpumask_clear_cpu(cpu, &d->cpu_mask); 542 if (cpumask_empty(&d->cpu_mask)) { 543 resctrl_offline_domain(r, d); 544 list_del(&d->list); 545 546 /* 547 * rdt_domain "d" is going to be freed below, so clear 548 * its pointer from pseudo_lock_region struct. 549 */ 550 if (d->plr) 551 d->plr->d = NULL; 552 domain_free(hw_dom); 553 554 return; 555 } 556 557 if (r == &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl) { 558 if (is_mbm_enabled() && cpu == d->mbm_work_cpu) { 559 cancel_delayed_work(&d->mbm_over); 560 mbm_setup_overflow_handler(d, 0); 561 } 562 if (is_llc_occupancy_enabled() && cpu == d->cqm_work_cpu && 563 has_busy_rmid(r, d)) { 564 cancel_delayed_work(&d->cqm_limbo); 565 cqm_setup_limbo_handler(d, 0); 566 } 567 } 568 } 569 570 static void clear_closid_rmid(int cpu) 571 { 572 struct resctrl_pqr_state *state = this_cpu_ptr(&pqr_state); 573 574 state->default_closid = 0; 575 state->default_rmid = 0; 576 state->cur_closid = 0; 577 state->cur_rmid = 0; 578 wrmsr(IA32_PQR_ASSOC, 0, 0); 579 } 580 581 static int resctrl_online_cpu(unsigned int cpu) 582 { 583 struct rdt_resource *r; 584 585 mutex_lock(&rdtgroup_mutex); 586 for_each_capable_rdt_resource(r) 587 domain_add_cpu(cpu, r); 588 /* The cpu is set in default rdtgroup after online. */ 589 cpumask_set_cpu(cpu, &rdtgroup_default.cpu_mask); 590 clear_closid_rmid(cpu); 591 mutex_unlock(&rdtgroup_mutex); 592 593 return 0; 594 } 595 596 static void clear_childcpus(struct rdtgroup *r, unsigned int cpu) 597 { 598 struct rdtgroup *cr; 599 600 list_for_each_entry(cr, &r->mon.crdtgrp_list, mon.crdtgrp_list) { 601 if (cpumask_test_and_clear_cpu(cpu, &cr->cpu_mask)) { 602 break; 603 } 604 } 605 } 606 607 static int resctrl_offline_cpu(unsigned int cpu) 608 { 609 struct rdtgroup *rdtgrp; 610 struct rdt_resource *r; 611 612 mutex_lock(&rdtgroup_mutex); 613 for_each_capable_rdt_resource(r) 614 domain_remove_cpu(cpu, r); 615 list_for_each_entry(rdtgrp, &rdt_all_groups, rdtgroup_list) { 616 if (cpumask_test_and_clear_cpu(cpu, &rdtgrp->cpu_mask)) { 617 clear_childcpus(rdtgrp, cpu); 618 break; 619 } 620 } 621 clear_closid_rmid(cpu); 622 mutex_unlock(&rdtgroup_mutex); 623 624 return 0; 625 } 626 627 /* 628 * Choose a width for the resource name and resource data based on the 629 * resource that has widest name and cbm. 630 */ 631 static __init void rdt_init_padding(void) 632 { 633 struct rdt_resource *r; 634 635 for_each_alloc_capable_rdt_resource(r) { 636 if (r->data_width > max_data_width) 637 max_data_width = r->data_width; 638 } 639 } 640 641 enum { 642 RDT_FLAG_CMT, 643 RDT_FLAG_MBM_TOTAL, 644 RDT_FLAG_MBM_LOCAL, 645 RDT_FLAG_L3_CAT, 646 RDT_FLAG_L3_CDP, 647 RDT_FLAG_L2_CAT, 648 RDT_FLAG_L2_CDP, 649 RDT_FLAG_MBA, 650 }; 651 652 #define RDT_OPT(idx, n, f) \ 653 [idx] = { \ 654 .name = n, \ 655 .flag = f \ 656 } 657 658 struct rdt_options { 659 char *name; 660 int flag; 661 bool force_off, force_on; 662 }; 663 664 static struct rdt_options rdt_options[] __initdata = { 665 RDT_OPT(RDT_FLAG_CMT, "cmt", X86_FEATURE_CQM_OCCUP_LLC), 666 RDT_OPT(RDT_FLAG_MBM_TOTAL, "mbmtotal", X86_FEATURE_CQM_MBM_TOTAL), 667 RDT_OPT(RDT_FLAG_MBM_LOCAL, "mbmlocal", X86_FEATURE_CQM_MBM_LOCAL), 668 RDT_OPT(RDT_FLAG_L3_CAT, "l3cat", X86_FEATURE_CAT_L3), 669 RDT_OPT(RDT_FLAG_L3_CDP, "l3cdp", X86_FEATURE_CDP_L3), 670 RDT_OPT(RDT_FLAG_L2_CAT, "l2cat", X86_FEATURE_CAT_L2), 671 RDT_OPT(RDT_FLAG_L2_CDP, "l2cdp", X86_FEATURE_CDP_L2), 672 RDT_OPT(RDT_FLAG_MBA, "mba", X86_FEATURE_MBA), 673 }; 674 #define NUM_RDT_OPTIONS ARRAY_SIZE(rdt_options) 675 676 static int __init set_rdt_options(char *str) 677 { 678 struct rdt_options *o; 679 bool force_off; 680 char *tok; 681 682 if (*str == '=') 683 str++; 684 while ((tok = strsep(&str, ",")) != NULL) { 685 force_off = *tok == '!'; 686 if (force_off) 687 tok++; 688 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) { 689 if (strcmp(tok, o->name) == 0) { 690 if (force_off) 691 o->force_off = true; 692 else 693 o->force_on = true; 694 break; 695 } 696 } 697 } 698 return 1; 699 } 700 __setup("rdt", set_rdt_options); 701 702 static bool __init rdt_cpu_has(int flag) 703 { 704 bool ret = boot_cpu_has(flag); 705 struct rdt_options *o; 706 707 if (!ret) 708 return ret; 709 710 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) { 711 if (flag == o->flag) { 712 if (o->force_off) 713 ret = false; 714 if (o->force_on) 715 ret = true; 716 break; 717 } 718 } 719 return ret; 720 } 721 722 static __init bool get_mem_config(void) 723 { 724 struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_MBA]; 725 726 if (!rdt_cpu_has(X86_FEATURE_MBA)) 727 return false; 728 729 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 730 return __get_mem_config_intel(&hw_res->r_resctrl); 731 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 732 return __rdt_get_mem_config_amd(&hw_res->r_resctrl); 733 734 return false; 735 } 736 737 static __init bool get_rdt_alloc_resources(void) 738 { 739 struct rdt_resource *r; 740 bool ret = false; 741 742 if (rdt_alloc_capable) 743 return true; 744 745 if (!boot_cpu_has(X86_FEATURE_RDT_A)) 746 return false; 747 748 if (rdt_cpu_has(X86_FEATURE_CAT_L3)) { 749 r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; 750 rdt_get_cache_alloc_cfg(1, r); 751 if (rdt_cpu_has(X86_FEATURE_CDP_L3)) 752 rdt_get_cdp_l3_config(); 753 ret = true; 754 } 755 if (rdt_cpu_has(X86_FEATURE_CAT_L2)) { 756 /* CPUID 0x10.2 fields are same format at 0x10.1 */ 757 r = &rdt_resources_all[RDT_RESOURCE_L2].r_resctrl; 758 rdt_get_cache_alloc_cfg(2, r); 759 if (rdt_cpu_has(X86_FEATURE_CDP_L2)) 760 rdt_get_cdp_l2_config(); 761 ret = true; 762 } 763 764 if (get_mem_config()) 765 ret = true; 766 767 return ret; 768 } 769 770 static __init bool get_rdt_mon_resources(void) 771 { 772 struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; 773 774 if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) 775 rdt_mon_features |= (1 << QOS_L3_OCCUP_EVENT_ID); 776 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL)) 777 rdt_mon_features |= (1 << QOS_L3_MBM_TOTAL_EVENT_ID); 778 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL)) 779 rdt_mon_features |= (1 << QOS_L3_MBM_LOCAL_EVENT_ID); 780 781 if (!rdt_mon_features) 782 return false; 783 784 return !rdt_get_mon_l3_config(r); 785 } 786 787 static __init void __check_quirks_intel(void) 788 { 789 switch (boot_cpu_data.x86_model) { 790 case INTEL_FAM6_HASWELL_X: 791 if (!rdt_options[RDT_FLAG_L3_CAT].force_off) 792 cache_alloc_hsw_probe(); 793 break; 794 case INTEL_FAM6_SKYLAKE_X: 795 if (boot_cpu_data.x86_stepping <= 4) 796 set_rdt_options("!cmt,!mbmtotal,!mbmlocal,!l3cat"); 797 else 798 set_rdt_options("!l3cat"); 799 fallthrough; 800 case INTEL_FAM6_BROADWELL_X: 801 intel_rdt_mbm_apply_quirk(); 802 break; 803 } 804 } 805 806 static __init void check_quirks(void) 807 { 808 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 809 __check_quirks_intel(); 810 } 811 812 static __init bool get_rdt_resources(void) 813 { 814 rdt_alloc_capable = get_rdt_alloc_resources(); 815 rdt_mon_capable = get_rdt_mon_resources(); 816 817 return (rdt_mon_capable || rdt_alloc_capable); 818 } 819 820 static __init void rdt_init_res_defs_intel(void) 821 { 822 struct rdt_hw_resource *hw_res; 823 struct rdt_resource *r; 824 825 for_each_rdt_resource(r) { 826 hw_res = resctrl_to_arch_res(r); 827 828 if (r->rid == RDT_RESOURCE_L3 || 829 r->rid == RDT_RESOURCE_L2) { 830 r->cache.arch_has_sparse_bitmaps = false; 831 r->cache.arch_has_empty_bitmaps = false; 832 r->cache.arch_has_per_cpu_cfg = false; 833 r->cache.min_cbm_bits = 1; 834 } else if (r->rid == RDT_RESOURCE_MBA) { 835 hw_res->msr_base = MSR_IA32_MBA_THRTL_BASE; 836 hw_res->msr_update = mba_wrmsr_intel; 837 } 838 } 839 } 840 841 static __init void rdt_init_res_defs_amd(void) 842 { 843 struct rdt_hw_resource *hw_res; 844 struct rdt_resource *r; 845 846 for_each_rdt_resource(r) { 847 hw_res = resctrl_to_arch_res(r); 848 849 if (r->rid == RDT_RESOURCE_L3 || 850 r->rid == RDT_RESOURCE_L2) { 851 r->cache.arch_has_sparse_bitmaps = true; 852 r->cache.arch_has_empty_bitmaps = true; 853 r->cache.arch_has_per_cpu_cfg = true; 854 r->cache.min_cbm_bits = 0; 855 } else if (r->rid == RDT_RESOURCE_MBA) { 856 hw_res->msr_base = MSR_IA32_MBA_BW_BASE; 857 hw_res->msr_update = mba_wrmsr_amd; 858 } 859 } 860 } 861 862 static __init void rdt_init_res_defs(void) 863 { 864 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 865 rdt_init_res_defs_intel(); 866 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 867 rdt_init_res_defs_amd(); 868 } 869 870 static enum cpuhp_state rdt_online; 871 872 /* Runs once on the BSP during boot. */ 873 void resctrl_cpu_detect(struct cpuinfo_x86 *c) 874 { 875 if (!cpu_has(c, X86_FEATURE_CQM_LLC)) { 876 c->x86_cache_max_rmid = -1; 877 c->x86_cache_occ_scale = -1; 878 c->x86_cache_mbm_width_offset = -1; 879 return; 880 } 881 882 /* will be overridden if occupancy monitoring exists */ 883 c->x86_cache_max_rmid = cpuid_ebx(0xf); 884 885 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) || 886 cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) || 887 cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) { 888 u32 eax, ebx, ecx, edx; 889 890 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 891 cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx); 892 893 c->x86_cache_max_rmid = ecx; 894 c->x86_cache_occ_scale = ebx; 895 c->x86_cache_mbm_width_offset = eax & 0xff; 896 897 if (c->x86_vendor == X86_VENDOR_AMD && !c->x86_cache_mbm_width_offset) 898 c->x86_cache_mbm_width_offset = MBM_CNTR_WIDTH_OFFSET_AMD; 899 } 900 } 901 902 static int __init resctrl_late_init(void) 903 { 904 struct rdt_resource *r; 905 int state, ret; 906 907 /* 908 * Initialize functions(or definitions) that are different 909 * between vendors here. 910 */ 911 rdt_init_res_defs(); 912 913 check_quirks(); 914 915 if (!get_rdt_resources()) 916 return -ENODEV; 917 918 rdt_init_padding(); 919 920 state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 921 "x86/resctrl/cat:online:", 922 resctrl_online_cpu, resctrl_offline_cpu); 923 if (state < 0) 924 return state; 925 926 ret = rdtgroup_init(); 927 if (ret) { 928 cpuhp_remove_state(state); 929 return ret; 930 } 931 rdt_online = state; 932 933 for_each_alloc_capable_rdt_resource(r) 934 pr_info("%s allocation detected\n", r->name); 935 936 for_each_mon_capable_rdt_resource(r) 937 pr_info("%s monitoring detected\n", r->name); 938 939 return 0; 940 } 941 942 late_initcall(resctrl_late_init); 943 944 static void __exit resctrl_exit(void) 945 { 946 cpuhp_remove_state(rdt_online); 947 rdtgroup_exit(); 948 } 949 950 __exitcall(resctrl_exit); 951