1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Core of Xen paravirt_ops implementation. 4 * 5 * This file contains the xen_paravirt_ops structure itself, and the 6 * implementations for: 7 * - privileged instructions 8 * - interrupt flags 9 * - segment operations 10 * - booting and setup 11 * 12 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 13 */ 14 15 #include <linux/cpu.h> 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/smp.h> 19 #include <linux/preempt.h> 20 #include <linux/hardirq.h> 21 #include <linux/percpu.h> 22 #include <linux/delay.h> 23 #include <linux/start_kernel.h> 24 #include <linux/sched.h> 25 #include <linux/kprobes.h> 26 #include <linux/kstrtox.h> 27 #include <linux/memblock.h> 28 #include <linux/export.h> 29 #include <linux/mm.h> 30 #include <linux/page-flags.h> 31 #include <linux/pci.h> 32 #include <linux/gfp.h> 33 #include <linux/edd.h> 34 #include <linux/reboot.h> 35 #include <linux/virtio_anchor.h> 36 #include <linux/stackprotector.h> 37 38 #include <xen/xen.h> 39 #include <xen/events.h> 40 #include <xen/interface/xen.h> 41 #include <xen/interface/version.h> 42 #include <xen/interface/physdev.h> 43 #include <xen/interface/vcpu.h> 44 #include <xen/interface/memory.h> 45 #include <xen/interface/nmi.h> 46 #include <xen/interface/xen-mca.h> 47 #include <xen/features.h> 48 #include <xen/page.h> 49 #include <xen/hvc-console.h> 50 #include <xen/acpi.h> 51 52 #include <asm/paravirt.h> 53 #include <asm/apic.h> 54 #include <asm/page.h> 55 #include <asm/xen/pci.h> 56 #include <asm/xen/hypercall.h> 57 #include <asm/xen/hypervisor.h> 58 #include <asm/xen/cpuid.h> 59 #include <asm/fixmap.h> 60 #include <asm/processor.h> 61 #include <asm/proto.h> 62 #include <asm/msr-index.h> 63 #include <asm/traps.h> 64 #include <asm/setup.h> 65 #include <asm/desc.h> 66 #include <asm/pgalloc.h> 67 #include <asm/tlbflush.h> 68 #include <asm/reboot.h> 69 #include <asm/hypervisor.h> 70 #include <asm/mach_traps.h> 71 #include <asm/mwait.h> 72 #include <asm/pci_x86.h> 73 #include <asm/cpu.h> 74 #ifdef CONFIG_X86_IOPL_IOPERM 75 #include <asm/io_bitmap.h> 76 #endif 77 78 #ifdef CONFIG_ACPI 79 #include <linux/acpi.h> 80 #include <asm/acpi.h> 81 #include <acpi/pdc_intel.h> 82 #include <acpi/processor.h> 83 #include <xen/interface/platform.h> 84 #endif 85 86 #include "xen-ops.h" 87 #include "mmu.h" 88 #include "smp.h" 89 #include "multicalls.h" 90 #include "pmu.h" 91 92 #include "../kernel/cpu/cpu.h" /* get_cpu_cap() */ 93 94 void *xen_initial_gdt; 95 96 static int xen_cpu_up_prepare_pv(unsigned int cpu); 97 static int xen_cpu_dead_pv(unsigned int cpu); 98 99 struct tls_descs { 100 struct desc_struct desc[3]; 101 }; 102 103 /* 104 * Updating the 3 TLS descriptors in the GDT on every task switch is 105 * surprisingly expensive so we avoid updating them if they haven't 106 * changed. Since Xen writes different descriptors than the one 107 * passed in the update_descriptor hypercall we keep shadow copies to 108 * compare against. 109 */ 110 static DEFINE_PER_CPU(struct tls_descs, shadow_tls_desc); 111 112 static __read_mostly bool xen_msr_safe = IS_ENABLED(CONFIG_XEN_PV_MSR_SAFE); 113 114 static int __init parse_xen_msr_safe(char *str) 115 { 116 if (str) 117 return kstrtobool(str, &xen_msr_safe); 118 return -EINVAL; 119 } 120 early_param("xen_msr_safe", parse_xen_msr_safe); 121 122 static void __init xen_pv_init_platform(void) 123 { 124 /* PV guests can't operate virtio devices without grants. */ 125 if (IS_ENABLED(CONFIG_XEN_VIRTIO)) 126 virtio_set_mem_acc_cb(xen_virtio_restricted_mem_acc); 127 128 populate_extra_pte(fix_to_virt(FIX_PARAVIRT_BOOTMAP)); 129 130 set_fixmap(FIX_PARAVIRT_BOOTMAP, xen_start_info->shared_info); 131 HYPERVISOR_shared_info = (void *)fix_to_virt(FIX_PARAVIRT_BOOTMAP); 132 133 /* xen clock uses per-cpu vcpu_info, need to init it for boot cpu */ 134 xen_vcpu_info_reset(0); 135 136 /* pvclock is in shared info area */ 137 xen_init_time_ops(); 138 } 139 140 static void __init xen_pv_guest_late_init(void) 141 { 142 #ifndef CONFIG_SMP 143 /* Setup shared vcpu info for non-smp configurations */ 144 xen_setup_vcpu_info_placement(); 145 #endif 146 } 147 148 static __read_mostly unsigned int cpuid_leaf5_ecx_val; 149 static __read_mostly unsigned int cpuid_leaf5_edx_val; 150 151 static void xen_cpuid(unsigned int *ax, unsigned int *bx, 152 unsigned int *cx, unsigned int *dx) 153 { 154 unsigned maskebx = ~0; 155 156 /* 157 * Mask out inconvenient features, to try and disable as many 158 * unsupported kernel subsystems as possible. 159 */ 160 switch (*ax) { 161 case CPUID_MWAIT_LEAF: 162 /* Synthesize the values.. */ 163 *ax = 0; 164 *bx = 0; 165 *cx = cpuid_leaf5_ecx_val; 166 *dx = cpuid_leaf5_edx_val; 167 return; 168 169 case 0xb: 170 /* Suppress extended topology stuff */ 171 maskebx = 0; 172 break; 173 } 174 175 asm(XEN_EMULATE_PREFIX "cpuid" 176 : "=a" (*ax), 177 "=b" (*bx), 178 "=c" (*cx), 179 "=d" (*dx) 180 : "0" (*ax), "2" (*cx)); 181 182 *bx &= maskebx; 183 } 184 185 static bool __init xen_check_mwait(void) 186 { 187 #ifdef CONFIG_ACPI 188 struct xen_platform_op op = { 189 .cmd = XENPF_set_processor_pminfo, 190 .u.set_pminfo.id = -1, 191 .u.set_pminfo.type = XEN_PM_PDC, 192 }; 193 uint32_t buf[3]; 194 unsigned int ax, bx, cx, dx; 195 unsigned int mwait_mask; 196 197 /* We need to determine whether it is OK to expose the MWAIT 198 * capability to the kernel to harvest deeper than C3 states from ACPI 199 * _CST using the processor_harvest_xen.c module. For this to work, we 200 * need to gather the MWAIT_LEAF values (which the cstate.c code 201 * checks against). The hypervisor won't expose the MWAIT flag because 202 * it would break backwards compatibility; so we will find out directly 203 * from the hardware and hypercall. 204 */ 205 if (!xen_initial_domain()) 206 return false; 207 208 /* 209 * When running under platform earlier than Xen4.2, do not expose 210 * mwait, to avoid the risk of loading native acpi pad driver 211 */ 212 if (!xen_running_on_version_or_later(4, 2)) 213 return false; 214 215 ax = 1; 216 cx = 0; 217 218 native_cpuid(&ax, &bx, &cx, &dx); 219 220 mwait_mask = (1 << (X86_FEATURE_EST % 32)) | 221 (1 << (X86_FEATURE_MWAIT % 32)); 222 223 if ((cx & mwait_mask) != mwait_mask) 224 return false; 225 226 /* We need to emulate the MWAIT_LEAF and for that we need both 227 * ecx and edx. The hypercall provides only partial information. 228 */ 229 230 ax = CPUID_MWAIT_LEAF; 231 bx = 0; 232 cx = 0; 233 dx = 0; 234 235 native_cpuid(&ax, &bx, &cx, &dx); 236 237 /* Ask the Hypervisor whether to clear ACPI_PDC_C_C2C3_FFH. If so, 238 * don't expose MWAIT_LEAF and let ACPI pick the IOPORT version of C3. 239 */ 240 buf[0] = ACPI_PDC_REVISION_ID; 241 buf[1] = 1; 242 buf[2] = (ACPI_PDC_C_CAPABILITY_SMP | ACPI_PDC_EST_CAPABILITY_SWSMP); 243 244 set_xen_guest_handle(op.u.set_pminfo.pdc, buf); 245 246 if ((HYPERVISOR_platform_op(&op) == 0) && 247 (buf[2] & (ACPI_PDC_C_C1_FFH | ACPI_PDC_C_C2C3_FFH))) { 248 cpuid_leaf5_ecx_val = cx; 249 cpuid_leaf5_edx_val = dx; 250 } 251 return true; 252 #else 253 return false; 254 #endif 255 } 256 257 static bool __init xen_check_xsave(void) 258 { 259 unsigned int cx, xsave_mask; 260 261 cx = cpuid_ecx(1); 262 263 xsave_mask = (1 << (X86_FEATURE_XSAVE % 32)) | 264 (1 << (X86_FEATURE_OSXSAVE % 32)); 265 266 /* Xen will set CR4.OSXSAVE if supported and not disabled by force */ 267 return (cx & xsave_mask) == xsave_mask; 268 } 269 270 static void __init xen_init_capabilities(void) 271 { 272 setup_force_cpu_cap(X86_FEATURE_XENPV); 273 setup_clear_cpu_cap(X86_FEATURE_DCA); 274 setup_clear_cpu_cap(X86_FEATURE_APERFMPERF); 275 setup_clear_cpu_cap(X86_FEATURE_MTRR); 276 setup_clear_cpu_cap(X86_FEATURE_ACC); 277 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 278 setup_clear_cpu_cap(X86_FEATURE_SME); 279 setup_clear_cpu_cap(X86_FEATURE_LKGS); 280 281 /* 282 * Xen PV would need some work to support PCID: CR3 handling as well 283 * as xen_flush_tlb_others() would need updating. 284 */ 285 setup_clear_cpu_cap(X86_FEATURE_PCID); 286 287 if (!xen_initial_domain()) 288 setup_clear_cpu_cap(X86_FEATURE_ACPI); 289 290 if (xen_check_mwait()) 291 setup_force_cpu_cap(X86_FEATURE_MWAIT); 292 else 293 setup_clear_cpu_cap(X86_FEATURE_MWAIT); 294 295 if (!xen_check_xsave()) { 296 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 297 setup_clear_cpu_cap(X86_FEATURE_OSXSAVE); 298 } 299 } 300 301 static noinstr void xen_set_debugreg(int reg, unsigned long val) 302 { 303 HYPERVISOR_set_debugreg(reg, val); 304 } 305 306 static noinstr unsigned long xen_get_debugreg(int reg) 307 { 308 return HYPERVISOR_get_debugreg(reg); 309 } 310 311 static void xen_end_context_switch(struct task_struct *next) 312 { 313 xen_mc_flush(); 314 paravirt_end_context_switch(next); 315 } 316 317 static unsigned long xen_store_tr(void) 318 { 319 return 0; 320 } 321 322 /* 323 * Set the page permissions for a particular virtual address. If the 324 * address is a vmalloc mapping (or other non-linear mapping), then 325 * find the linear mapping of the page and also set its protections to 326 * match. 327 */ 328 static void set_aliased_prot(void *v, pgprot_t prot) 329 { 330 int level; 331 pte_t *ptep; 332 pte_t pte; 333 unsigned long pfn; 334 unsigned char dummy; 335 void *va; 336 337 ptep = lookup_address((unsigned long)v, &level); 338 BUG_ON(ptep == NULL); 339 340 pfn = pte_pfn(*ptep); 341 pte = pfn_pte(pfn, prot); 342 343 /* 344 * Careful: update_va_mapping() will fail if the virtual address 345 * we're poking isn't populated in the page tables. We don't 346 * need to worry about the direct map (that's always in the page 347 * tables), but we need to be careful about vmap space. In 348 * particular, the top level page table can lazily propagate 349 * entries between processes, so if we've switched mms since we 350 * vmapped the target in the first place, we might not have the 351 * top-level page table entry populated. 352 * 353 * We disable preemption because we want the same mm active when 354 * we probe the target and when we issue the hypercall. We'll 355 * have the same nominal mm, but if we're a kernel thread, lazy 356 * mm dropping could change our pgd. 357 * 358 * Out of an abundance of caution, this uses __get_user() to fault 359 * in the target address just in case there's some obscure case 360 * in which the target address isn't readable. 361 */ 362 363 preempt_disable(); 364 365 copy_from_kernel_nofault(&dummy, v, 1); 366 367 if (HYPERVISOR_update_va_mapping((unsigned long)v, pte, 0)) 368 BUG(); 369 370 va = __va(PFN_PHYS(pfn)); 371 372 if (va != v && HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0)) 373 BUG(); 374 375 preempt_enable(); 376 } 377 378 static void xen_alloc_ldt(struct desc_struct *ldt, unsigned entries) 379 { 380 const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE; 381 int i; 382 383 /* 384 * We need to mark the all aliases of the LDT pages RO. We 385 * don't need to call vm_flush_aliases(), though, since that's 386 * only responsible for flushing aliases out the TLBs, not the 387 * page tables, and Xen will flush the TLB for us if needed. 388 * 389 * To avoid confusing future readers: none of this is necessary 390 * to load the LDT. The hypervisor only checks this when the 391 * LDT is faulted in due to subsequent descriptor access. 392 */ 393 394 for (i = 0; i < entries; i += entries_per_page) 395 set_aliased_prot(ldt + i, PAGE_KERNEL_RO); 396 } 397 398 static void xen_free_ldt(struct desc_struct *ldt, unsigned entries) 399 { 400 const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE; 401 int i; 402 403 for (i = 0; i < entries; i += entries_per_page) 404 set_aliased_prot(ldt + i, PAGE_KERNEL); 405 } 406 407 static void xen_set_ldt(const void *addr, unsigned entries) 408 { 409 struct mmuext_op *op; 410 struct multicall_space mcs = xen_mc_entry(sizeof(*op)); 411 412 trace_xen_cpu_set_ldt(addr, entries); 413 414 op = mcs.args; 415 op->cmd = MMUEXT_SET_LDT; 416 op->arg1.linear_addr = (unsigned long)addr; 417 op->arg2.nr_ents = entries; 418 419 MULTI_mmuext_op(mcs.mc, op, 1, NULL, DOMID_SELF); 420 421 xen_mc_issue(PARAVIRT_LAZY_CPU); 422 } 423 424 static void xen_load_gdt(const struct desc_ptr *dtr) 425 { 426 unsigned long va = dtr->address; 427 unsigned int size = dtr->size + 1; 428 unsigned long pfn, mfn; 429 int level; 430 pte_t *ptep; 431 void *virt; 432 433 /* @size should be at most GDT_SIZE which is smaller than PAGE_SIZE. */ 434 BUG_ON(size > PAGE_SIZE); 435 BUG_ON(va & ~PAGE_MASK); 436 437 /* 438 * The GDT is per-cpu and is in the percpu data area. 439 * That can be virtually mapped, so we need to do a 440 * page-walk to get the underlying MFN for the 441 * hypercall. The page can also be in the kernel's 442 * linear range, so we need to RO that mapping too. 443 */ 444 ptep = lookup_address(va, &level); 445 BUG_ON(ptep == NULL); 446 447 pfn = pte_pfn(*ptep); 448 mfn = pfn_to_mfn(pfn); 449 virt = __va(PFN_PHYS(pfn)); 450 451 make_lowmem_page_readonly((void *)va); 452 make_lowmem_page_readonly(virt); 453 454 if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct))) 455 BUG(); 456 } 457 458 /* 459 * load_gdt for early boot, when the gdt is only mapped once 460 */ 461 static void __init xen_load_gdt_boot(const struct desc_ptr *dtr) 462 { 463 unsigned long va = dtr->address; 464 unsigned int size = dtr->size + 1; 465 unsigned long pfn, mfn; 466 pte_t pte; 467 468 /* @size should be at most GDT_SIZE which is smaller than PAGE_SIZE. */ 469 BUG_ON(size > PAGE_SIZE); 470 BUG_ON(va & ~PAGE_MASK); 471 472 pfn = virt_to_pfn(va); 473 mfn = pfn_to_mfn(pfn); 474 475 pte = pfn_pte(pfn, PAGE_KERNEL_RO); 476 477 if (HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0)) 478 BUG(); 479 480 if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct))) 481 BUG(); 482 } 483 484 static inline bool desc_equal(const struct desc_struct *d1, 485 const struct desc_struct *d2) 486 { 487 return !memcmp(d1, d2, sizeof(*d1)); 488 } 489 490 static void load_TLS_descriptor(struct thread_struct *t, 491 unsigned int cpu, unsigned int i) 492 { 493 struct desc_struct *shadow = &per_cpu(shadow_tls_desc, cpu).desc[i]; 494 struct desc_struct *gdt; 495 xmaddr_t maddr; 496 struct multicall_space mc; 497 498 if (desc_equal(shadow, &t->tls_array[i])) 499 return; 500 501 *shadow = t->tls_array[i]; 502 503 gdt = get_cpu_gdt_rw(cpu); 504 maddr = arbitrary_virt_to_machine(&gdt[GDT_ENTRY_TLS_MIN+i]); 505 mc = __xen_mc_entry(0); 506 507 MULTI_update_descriptor(mc.mc, maddr.maddr, t->tls_array[i]); 508 } 509 510 static void xen_load_tls(struct thread_struct *t, unsigned int cpu) 511 { 512 /* 513 * In lazy mode we need to zero %fs, otherwise we may get an 514 * exception between the new %fs descriptor being loaded and 515 * %fs being effectively cleared at __switch_to(). 516 */ 517 if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_CPU) 518 loadsegment(fs, 0); 519 520 xen_mc_batch(); 521 522 load_TLS_descriptor(t, cpu, 0); 523 load_TLS_descriptor(t, cpu, 1); 524 load_TLS_descriptor(t, cpu, 2); 525 526 xen_mc_issue(PARAVIRT_LAZY_CPU); 527 } 528 529 static void xen_load_gs_index(unsigned int idx) 530 { 531 if (HYPERVISOR_set_segment_base(SEGBASE_GS_USER_SEL, idx)) 532 BUG(); 533 } 534 535 static void xen_write_ldt_entry(struct desc_struct *dt, int entrynum, 536 const void *ptr) 537 { 538 xmaddr_t mach_lp = arbitrary_virt_to_machine(&dt[entrynum]); 539 u64 entry = *(u64 *)ptr; 540 541 trace_xen_cpu_write_ldt_entry(dt, entrynum, entry); 542 543 preempt_disable(); 544 545 xen_mc_flush(); 546 if (HYPERVISOR_update_descriptor(mach_lp.maddr, entry)) 547 BUG(); 548 549 preempt_enable(); 550 } 551 552 void noist_exc_debug(struct pt_regs *regs); 553 554 DEFINE_IDTENTRY_RAW(xenpv_exc_nmi) 555 { 556 /* On Xen PV, NMI doesn't use IST. The C part is the same as native. */ 557 exc_nmi(regs); 558 } 559 560 DEFINE_IDTENTRY_RAW_ERRORCODE(xenpv_exc_double_fault) 561 { 562 /* On Xen PV, DF doesn't use IST. The C part is the same as native. */ 563 exc_double_fault(regs, error_code); 564 } 565 566 DEFINE_IDTENTRY_RAW(xenpv_exc_debug) 567 { 568 /* 569 * There's no IST on Xen PV, but we still need to dispatch 570 * to the correct handler. 571 */ 572 if (user_mode(regs)) 573 noist_exc_debug(regs); 574 else 575 exc_debug(regs); 576 } 577 578 DEFINE_IDTENTRY_RAW(exc_xen_unknown_trap) 579 { 580 /* This should never happen and there is no way to handle it. */ 581 instrumentation_begin(); 582 pr_err("Unknown trap in Xen PV mode."); 583 BUG(); 584 instrumentation_end(); 585 } 586 587 #ifdef CONFIG_X86_MCE 588 DEFINE_IDTENTRY_RAW(xenpv_exc_machine_check) 589 { 590 /* 591 * There's no IST on Xen PV, but we still need to dispatch 592 * to the correct handler. 593 */ 594 if (user_mode(regs)) 595 noist_exc_machine_check(regs); 596 else 597 exc_machine_check(regs); 598 } 599 #endif 600 601 struct trap_array_entry { 602 void (*orig)(void); 603 void (*xen)(void); 604 bool ist_okay; 605 }; 606 607 #define TRAP_ENTRY(func, ist_ok) { \ 608 .orig = asm_##func, \ 609 .xen = xen_asm_##func, \ 610 .ist_okay = ist_ok } 611 612 #define TRAP_ENTRY_REDIR(func, ist_ok) { \ 613 .orig = asm_##func, \ 614 .xen = xen_asm_xenpv_##func, \ 615 .ist_okay = ist_ok } 616 617 static struct trap_array_entry trap_array[] = { 618 TRAP_ENTRY_REDIR(exc_debug, true ), 619 TRAP_ENTRY_REDIR(exc_double_fault, true ), 620 #ifdef CONFIG_X86_MCE 621 TRAP_ENTRY_REDIR(exc_machine_check, true ), 622 #endif 623 TRAP_ENTRY_REDIR(exc_nmi, true ), 624 TRAP_ENTRY(exc_int3, false ), 625 TRAP_ENTRY(exc_overflow, false ), 626 #ifdef CONFIG_IA32_EMULATION 627 { entry_INT80_compat, xen_entry_INT80_compat, false }, 628 #endif 629 TRAP_ENTRY(exc_page_fault, false ), 630 TRAP_ENTRY(exc_divide_error, false ), 631 TRAP_ENTRY(exc_bounds, false ), 632 TRAP_ENTRY(exc_invalid_op, false ), 633 TRAP_ENTRY(exc_device_not_available, false ), 634 TRAP_ENTRY(exc_coproc_segment_overrun, false ), 635 TRAP_ENTRY(exc_invalid_tss, false ), 636 TRAP_ENTRY(exc_segment_not_present, false ), 637 TRAP_ENTRY(exc_stack_segment, false ), 638 TRAP_ENTRY(exc_general_protection, false ), 639 TRAP_ENTRY(exc_spurious_interrupt_bug, false ), 640 TRAP_ENTRY(exc_coprocessor_error, false ), 641 TRAP_ENTRY(exc_alignment_check, false ), 642 TRAP_ENTRY(exc_simd_coprocessor_error, false ), 643 #ifdef CONFIG_X86_KERNEL_IBT 644 TRAP_ENTRY(exc_control_protection, false ), 645 #endif 646 }; 647 648 static bool __ref get_trap_addr(void **addr, unsigned int ist) 649 { 650 unsigned int nr; 651 bool ist_okay = false; 652 bool found = false; 653 654 /* 655 * Replace trap handler addresses by Xen specific ones. 656 * Check for known traps using IST and whitelist them. 657 * The debugger ones are the only ones we care about. 658 * Xen will handle faults like double_fault, so we should never see 659 * them. Warn if there's an unexpected IST-using fault handler. 660 */ 661 for (nr = 0; nr < ARRAY_SIZE(trap_array); nr++) { 662 struct trap_array_entry *entry = trap_array + nr; 663 664 if (*addr == entry->orig) { 665 *addr = entry->xen; 666 ist_okay = entry->ist_okay; 667 found = true; 668 break; 669 } 670 } 671 672 if (nr == ARRAY_SIZE(trap_array) && 673 *addr >= (void *)early_idt_handler_array[0] && 674 *addr < (void *)early_idt_handler_array[NUM_EXCEPTION_VECTORS]) { 675 nr = (*addr - (void *)early_idt_handler_array[0]) / 676 EARLY_IDT_HANDLER_SIZE; 677 *addr = (void *)xen_early_idt_handler_array[nr]; 678 found = true; 679 } 680 681 if (!found) 682 *addr = (void *)xen_asm_exc_xen_unknown_trap; 683 684 if (WARN_ON(found && ist != 0 && !ist_okay)) 685 return false; 686 687 return true; 688 } 689 690 static int cvt_gate_to_trap(int vector, const gate_desc *val, 691 struct trap_info *info) 692 { 693 unsigned long addr; 694 695 if (val->bits.type != GATE_TRAP && val->bits.type != GATE_INTERRUPT) 696 return 0; 697 698 info->vector = vector; 699 700 addr = gate_offset(val); 701 if (!get_trap_addr((void **)&addr, val->bits.ist)) 702 return 0; 703 info->address = addr; 704 705 info->cs = gate_segment(val); 706 info->flags = val->bits.dpl; 707 /* interrupt gates clear IF */ 708 if (val->bits.type == GATE_INTERRUPT) 709 info->flags |= 1 << 2; 710 711 return 1; 712 } 713 714 /* Locations of each CPU's IDT */ 715 static DEFINE_PER_CPU(struct desc_ptr, idt_desc); 716 717 /* Set an IDT entry. If the entry is part of the current IDT, then 718 also update Xen. */ 719 static void xen_write_idt_entry(gate_desc *dt, int entrynum, const gate_desc *g) 720 { 721 unsigned long p = (unsigned long)&dt[entrynum]; 722 unsigned long start, end; 723 724 trace_xen_cpu_write_idt_entry(dt, entrynum, g); 725 726 preempt_disable(); 727 728 start = __this_cpu_read(idt_desc.address); 729 end = start + __this_cpu_read(idt_desc.size) + 1; 730 731 xen_mc_flush(); 732 733 native_write_idt_entry(dt, entrynum, g); 734 735 if (p >= start && (p + 8) <= end) { 736 struct trap_info info[2]; 737 738 info[1].address = 0; 739 740 if (cvt_gate_to_trap(entrynum, g, &info[0])) 741 if (HYPERVISOR_set_trap_table(info)) 742 BUG(); 743 } 744 745 preempt_enable(); 746 } 747 748 static unsigned xen_convert_trap_info(const struct desc_ptr *desc, 749 struct trap_info *traps, bool full) 750 { 751 unsigned in, out, count; 752 753 count = (desc->size+1) / sizeof(gate_desc); 754 BUG_ON(count > 256); 755 756 for (in = out = 0; in < count; in++) { 757 gate_desc *entry = (gate_desc *)(desc->address) + in; 758 759 if (cvt_gate_to_trap(in, entry, &traps[out]) || full) 760 out++; 761 } 762 763 return out; 764 } 765 766 void xen_copy_trap_info(struct trap_info *traps) 767 { 768 const struct desc_ptr *desc = this_cpu_ptr(&idt_desc); 769 770 xen_convert_trap_info(desc, traps, true); 771 } 772 773 /* Load a new IDT into Xen. In principle this can be per-CPU, so we 774 hold a spinlock to protect the static traps[] array (static because 775 it avoids allocation, and saves stack space). */ 776 static void xen_load_idt(const struct desc_ptr *desc) 777 { 778 static DEFINE_SPINLOCK(lock); 779 static struct trap_info traps[257]; 780 static const struct trap_info zero = { }; 781 unsigned out; 782 783 trace_xen_cpu_load_idt(desc); 784 785 spin_lock(&lock); 786 787 memcpy(this_cpu_ptr(&idt_desc), desc, sizeof(idt_desc)); 788 789 out = xen_convert_trap_info(desc, traps, false); 790 traps[out] = zero; 791 792 xen_mc_flush(); 793 if (HYPERVISOR_set_trap_table(traps)) 794 BUG(); 795 796 spin_unlock(&lock); 797 } 798 799 /* Write a GDT descriptor entry. Ignore LDT descriptors, since 800 they're handled differently. */ 801 static void xen_write_gdt_entry(struct desc_struct *dt, int entry, 802 const void *desc, int type) 803 { 804 trace_xen_cpu_write_gdt_entry(dt, entry, desc, type); 805 806 preempt_disable(); 807 808 switch (type) { 809 case DESC_LDT: 810 case DESC_TSS: 811 /* ignore */ 812 break; 813 814 default: { 815 xmaddr_t maddr = arbitrary_virt_to_machine(&dt[entry]); 816 817 xen_mc_flush(); 818 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc)) 819 BUG(); 820 } 821 822 } 823 824 preempt_enable(); 825 } 826 827 /* 828 * Version of write_gdt_entry for use at early boot-time needed to 829 * update an entry as simply as possible. 830 */ 831 static void __init xen_write_gdt_entry_boot(struct desc_struct *dt, int entry, 832 const void *desc, int type) 833 { 834 trace_xen_cpu_write_gdt_entry(dt, entry, desc, type); 835 836 switch (type) { 837 case DESC_LDT: 838 case DESC_TSS: 839 /* ignore */ 840 break; 841 842 default: { 843 xmaddr_t maddr = virt_to_machine(&dt[entry]); 844 845 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc)) 846 dt[entry] = *(struct desc_struct *)desc; 847 } 848 849 } 850 } 851 852 static void xen_load_sp0(unsigned long sp0) 853 { 854 struct multicall_space mcs; 855 856 mcs = xen_mc_entry(0); 857 MULTI_stack_switch(mcs.mc, __KERNEL_DS, sp0); 858 xen_mc_issue(PARAVIRT_LAZY_CPU); 859 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); 860 } 861 862 #ifdef CONFIG_X86_IOPL_IOPERM 863 static void xen_invalidate_io_bitmap(void) 864 { 865 struct physdev_set_iobitmap iobitmap = { 866 .bitmap = NULL, 867 .nr_ports = 0, 868 }; 869 870 native_tss_invalidate_io_bitmap(); 871 HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap); 872 } 873 874 static void xen_update_io_bitmap(void) 875 { 876 struct physdev_set_iobitmap iobitmap; 877 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 878 879 native_tss_update_io_bitmap(); 880 881 iobitmap.bitmap = (uint8_t *)(&tss->x86_tss) + 882 tss->x86_tss.io_bitmap_base; 883 if (tss->x86_tss.io_bitmap_base == IO_BITMAP_OFFSET_INVALID) 884 iobitmap.nr_ports = 0; 885 else 886 iobitmap.nr_ports = IO_BITMAP_BITS; 887 888 HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap); 889 } 890 #endif 891 892 static void xen_io_delay(void) 893 { 894 } 895 896 static DEFINE_PER_CPU(unsigned long, xen_cr0_value); 897 898 static unsigned long xen_read_cr0(void) 899 { 900 unsigned long cr0 = this_cpu_read(xen_cr0_value); 901 902 if (unlikely(cr0 == 0)) { 903 cr0 = native_read_cr0(); 904 this_cpu_write(xen_cr0_value, cr0); 905 } 906 907 return cr0; 908 } 909 910 static void xen_write_cr0(unsigned long cr0) 911 { 912 struct multicall_space mcs; 913 914 this_cpu_write(xen_cr0_value, cr0); 915 916 /* Only pay attention to cr0.TS; everything else is 917 ignored. */ 918 mcs = xen_mc_entry(0); 919 920 MULTI_fpu_taskswitch(mcs.mc, (cr0 & X86_CR0_TS) != 0); 921 922 xen_mc_issue(PARAVIRT_LAZY_CPU); 923 } 924 925 static void xen_write_cr4(unsigned long cr4) 926 { 927 cr4 &= ~(X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PCE); 928 929 native_write_cr4(cr4); 930 } 931 932 static u64 xen_do_read_msr(unsigned int msr, int *err) 933 { 934 u64 val = 0; /* Avoid uninitialized value for safe variant. */ 935 936 if (pmu_msr_read(msr, &val, err)) 937 return val; 938 939 if (err) 940 val = native_read_msr_safe(msr, err); 941 else 942 val = native_read_msr(msr); 943 944 switch (msr) { 945 case MSR_IA32_APICBASE: 946 val &= ~X2APIC_ENABLE; 947 break; 948 } 949 return val; 950 } 951 952 static void set_seg(unsigned int which, unsigned int low, unsigned int high, 953 int *err) 954 { 955 u64 base = ((u64)high << 32) | low; 956 957 if (HYPERVISOR_set_segment_base(which, base) == 0) 958 return; 959 960 if (err) 961 *err = -EIO; 962 else 963 WARN(1, "Xen set_segment_base(%u, %llx) failed\n", which, base); 964 } 965 966 /* 967 * Support write_msr_safe() and write_msr() semantics. 968 * With err == NULL write_msr() semantics are selected. 969 * Supplying an err pointer requires err to be pre-initialized with 0. 970 */ 971 static void xen_do_write_msr(unsigned int msr, unsigned int low, 972 unsigned int high, int *err) 973 { 974 switch (msr) { 975 case MSR_FS_BASE: 976 set_seg(SEGBASE_FS, low, high, err); 977 break; 978 979 case MSR_KERNEL_GS_BASE: 980 set_seg(SEGBASE_GS_USER, low, high, err); 981 break; 982 983 case MSR_GS_BASE: 984 set_seg(SEGBASE_GS_KERNEL, low, high, err); 985 break; 986 987 case MSR_STAR: 988 case MSR_CSTAR: 989 case MSR_LSTAR: 990 case MSR_SYSCALL_MASK: 991 case MSR_IA32_SYSENTER_CS: 992 case MSR_IA32_SYSENTER_ESP: 993 case MSR_IA32_SYSENTER_EIP: 994 /* Fast syscall setup is all done in hypercalls, so 995 these are all ignored. Stub them out here to stop 996 Xen console noise. */ 997 break; 998 999 default: 1000 if (!pmu_msr_write(msr, low, high, err)) { 1001 if (err) 1002 *err = native_write_msr_safe(msr, low, high); 1003 else 1004 native_write_msr(msr, low, high); 1005 } 1006 } 1007 } 1008 1009 static u64 xen_read_msr_safe(unsigned int msr, int *err) 1010 { 1011 return xen_do_read_msr(msr, err); 1012 } 1013 1014 static int xen_write_msr_safe(unsigned int msr, unsigned int low, 1015 unsigned int high) 1016 { 1017 int err = 0; 1018 1019 xen_do_write_msr(msr, low, high, &err); 1020 1021 return err; 1022 } 1023 1024 static u64 xen_read_msr(unsigned int msr) 1025 { 1026 int err; 1027 1028 return xen_do_read_msr(msr, xen_msr_safe ? &err : NULL); 1029 } 1030 1031 static void xen_write_msr(unsigned int msr, unsigned low, unsigned high) 1032 { 1033 int err; 1034 1035 xen_do_write_msr(msr, low, high, xen_msr_safe ? &err : NULL); 1036 } 1037 1038 /* This is called once we have the cpu_possible_mask */ 1039 void __init xen_setup_vcpu_info_placement(void) 1040 { 1041 int cpu; 1042 1043 for_each_possible_cpu(cpu) { 1044 /* Set up direct vCPU id mapping for PV guests. */ 1045 per_cpu(xen_vcpu_id, cpu) = cpu; 1046 xen_vcpu_setup(cpu); 1047 } 1048 1049 pv_ops.irq.save_fl = __PV_IS_CALLEE_SAVE(xen_save_fl_direct); 1050 pv_ops.irq.irq_disable = __PV_IS_CALLEE_SAVE(xen_irq_disable_direct); 1051 pv_ops.irq.irq_enable = __PV_IS_CALLEE_SAVE(xen_irq_enable_direct); 1052 pv_ops.mmu.read_cr2 = __PV_IS_CALLEE_SAVE(xen_read_cr2_direct); 1053 } 1054 1055 static const struct pv_info xen_info __initconst = { 1056 .extra_user_64bit_cs = FLAT_USER_CS64, 1057 .name = "Xen", 1058 }; 1059 1060 static const typeof(pv_ops) xen_cpu_ops __initconst = { 1061 .cpu = { 1062 .cpuid = xen_cpuid, 1063 1064 .set_debugreg = xen_set_debugreg, 1065 .get_debugreg = xen_get_debugreg, 1066 1067 .read_cr0 = xen_read_cr0, 1068 .write_cr0 = xen_write_cr0, 1069 1070 .write_cr4 = xen_write_cr4, 1071 1072 .wbinvd = pv_native_wbinvd, 1073 1074 .read_msr = xen_read_msr, 1075 .write_msr = xen_write_msr, 1076 1077 .read_msr_safe = xen_read_msr_safe, 1078 .write_msr_safe = xen_write_msr_safe, 1079 1080 .read_pmc = xen_read_pmc, 1081 1082 .load_tr_desc = paravirt_nop, 1083 .set_ldt = xen_set_ldt, 1084 .load_gdt = xen_load_gdt, 1085 .load_idt = xen_load_idt, 1086 .load_tls = xen_load_tls, 1087 .load_gs_index = xen_load_gs_index, 1088 1089 .alloc_ldt = xen_alloc_ldt, 1090 .free_ldt = xen_free_ldt, 1091 1092 .store_tr = xen_store_tr, 1093 1094 .write_ldt_entry = xen_write_ldt_entry, 1095 .write_gdt_entry = xen_write_gdt_entry, 1096 .write_idt_entry = xen_write_idt_entry, 1097 .load_sp0 = xen_load_sp0, 1098 1099 #ifdef CONFIG_X86_IOPL_IOPERM 1100 .invalidate_io_bitmap = xen_invalidate_io_bitmap, 1101 .update_io_bitmap = xen_update_io_bitmap, 1102 #endif 1103 .io_delay = xen_io_delay, 1104 1105 .start_context_switch = paravirt_start_context_switch, 1106 .end_context_switch = xen_end_context_switch, 1107 }, 1108 }; 1109 1110 static void xen_restart(char *msg) 1111 { 1112 xen_reboot(SHUTDOWN_reboot); 1113 } 1114 1115 static void xen_machine_halt(void) 1116 { 1117 xen_reboot(SHUTDOWN_poweroff); 1118 } 1119 1120 static void xen_machine_power_off(void) 1121 { 1122 do_kernel_power_off(); 1123 xen_reboot(SHUTDOWN_poweroff); 1124 } 1125 1126 static void xen_crash_shutdown(struct pt_regs *regs) 1127 { 1128 xen_reboot(SHUTDOWN_crash); 1129 } 1130 1131 static const struct machine_ops xen_machine_ops __initconst = { 1132 .restart = xen_restart, 1133 .halt = xen_machine_halt, 1134 .power_off = xen_machine_power_off, 1135 .shutdown = xen_machine_halt, 1136 .crash_shutdown = xen_crash_shutdown, 1137 .emergency_restart = xen_emergency_restart, 1138 }; 1139 1140 static unsigned char xen_get_nmi_reason(void) 1141 { 1142 unsigned char reason = 0; 1143 1144 /* Construct a value which looks like it came from port 0x61. */ 1145 if (test_bit(_XEN_NMIREASON_io_error, 1146 &HYPERVISOR_shared_info->arch.nmi_reason)) 1147 reason |= NMI_REASON_IOCHK; 1148 if (test_bit(_XEN_NMIREASON_pci_serr, 1149 &HYPERVISOR_shared_info->arch.nmi_reason)) 1150 reason |= NMI_REASON_SERR; 1151 1152 return reason; 1153 } 1154 1155 static void __init xen_boot_params_init_edd(void) 1156 { 1157 #if IS_ENABLED(CONFIG_EDD) 1158 struct xen_platform_op op; 1159 struct edd_info *edd_info; 1160 u32 *mbr_signature; 1161 unsigned nr; 1162 int ret; 1163 1164 edd_info = boot_params.eddbuf; 1165 mbr_signature = boot_params.edd_mbr_sig_buffer; 1166 1167 op.cmd = XENPF_firmware_info; 1168 1169 op.u.firmware_info.type = XEN_FW_DISK_INFO; 1170 for (nr = 0; nr < EDDMAXNR; nr++) { 1171 struct edd_info *info = edd_info + nr; 1172 1173 op.u.firmware_info.index = nr; 1174 info->params.length = sizeof(info->params); 1175 set_xen_guest_handle(op.u.firmware_info.u.disk_info.edd_params, 1176 &info->params); 1177 ret = HYPERVISOR_platform_op(&op); 1178 if (ret) 1179 break; 1180 1181 #define C(x) info->x = op.u.firmware_info.u.disk_info.x 1182 C(device); 1183 C(version); 1184 C(interface_support); 1185 C(legacy_max_cylinder); 1186 C(legacy_max_head); 1187 C(legacy_sectors_per_track); 1188 #undef C 1189 } 1190 boot_params.eddbuf_entries = nr; 1191 1192 op.u.firmware_info.type = XEN_FW_DISK_MBR_SIGNATURE; 1193 for (nr = 0; nr < EDD_MBR_SIG_MAX; nr++) { 1194 op.u.firmware_info.index = nr; 1195 ret = HYPERVISOR_platform_op(&op); 1196 if (ret) 1197 break; 1198 mbr_signature[nr] = op.u.firmware_info.u.disk_mbr_signature.mbr_signature; 1199 } 1200 boot_params.edd_mbr_sig_buf_entries = nr; 1201 #endif 1202 } 1203 1204 /* 1205 * Set up the GDT and segment registers for -fstack-protector. Until 1206 * we do this, we have to be careful not to call any stack-protected 1207 * function, which is most of the kernel. 1208 */ 1209 static void __init xen_setup_gdt(int cpu) 1210 { 1211 pv_ops.cpu.write_gdt_entry = xen_write_gdt_entry_boot; 1212 pv_ops.cpu.load_gdt = xen_load_gdt_boot; 1213 1214 switch_gdt_and_percpu_base(cpu); 1215 1216 pv_ops.cpu.write_gdt_entry = xen_write_gdt_entry; 1217 pv_ops.cpu.load_gdt = xen_load_gdt; 1218 } 1219 1220 static void __init xen_dom0_set_legacy_features(void) 1221 { 1222 x86_platform.legacy.rtc = 1; 1223 } 1224 1225 static void __init xen_domu_set_legacy_features(void) 1226 { 1227 x86_platform.legacy.rtc = 0; 1228 } 1229 1230 extern void early_xen_iret_patch(void); 1231 1232 /* First C function to be called on Xen boot */ 1233 asmlinkage __visible void __init xen_start_kernel(struct start_info *si) 1234 { 1235 struct physdev_set_iopl set_iopl; 1236 unsigned long initrd_start = 0; 1237 int rc; 1238 1239 if (!si) 1240 return; 1241 1242 clear_bss(); 1243 1244 xen_start_info = si; 1245 1246 __text_gen_insn(&early_xen_iret_patch, 1247 JMP32_INSN_OPCODE, &early_xen_iret_patch, &xen_iret, 1248 JMP32_INSN_SIZE); 1249 1250 xen_domain_type = XEN_PV_DOMAIN; 1251 xen_start_flags = xen_start_info->flags; 1252 1253 xen_setup_features(); 1254 1255 /* Install Xen paravirt ops */ 1256 pv_info = xen_info; 1257 pv_ops.cpu = xen_cpu_ops.cpu; 1258 xen_init_irq_ops(); 1259 1260 /* 1261 * Setup xen_vcpu early because it is needed for 1262 * local_irq_disable(), irqs_disabled(), e.g. in printk(). 1263 * 1264 * Don't do the full vcpu_info placement stuff until we have 1265 * the cpu_possible_mask and a non-dummy shared_info. 1266 */ 1267 xen_vcpu_info_reset(0); 1268 1269 x86_platform.get_nmi_reason = xen_get_nmi_reason; 1270 x86_platform.realmode_reserve = x86_init_noop; 1271 x86_platform.realmode_init = x86_init_noop; 1272 1273 x86_init.resources.memory_setup = xen_memory_setup; 1274 x86_init.irqs.intr_mode_select = x86_init_noop; 1275 x86_init.irqs.intr_mode_init = x86_init_noop; 1276 x86_init.oem.arch_setup = xen_arch_setup; 1277 x86_init.oem.banner = xen_banner; 1278 x86_init.hyper.init_platform = xen_pv_init_platform; 1279 x86_init.hyper.guest_late_init = xen_pv_guest_late_init; 1280 1281 /* 1282 * Set up some pagetable state before starting to set any ptes. 1283 */ 1284 1285 xen_setup_machphys_mapping(); 1286 xen_init_mmu_ops(); 1287 1288 /* Prevent unwanted bits from being set in PTEs. */ 1289 __supported_pte_mask &= ~_PAGE_GLOBAL; 1290 __default_kernel_pte_mask &= ~_PAGE_GLOBAL; 1291 1292 /* Get mfn list */ 1293 xen_build_dynamic_phys_to_machine(); 1294 1295 /* Work out if we support NX */ 1296 get_cpu_cap(&boot_cpu_data); 1297 x86_configure_nx(); 1298 1299 /* 1300 * Set up kernel GDT and segment registers, mainly so that 1301 * -fstack-protector code can be executed. 1302 */ 1303 xen_setup_gdt(0); 1304 1305 /* Determine virtual and physical address sizes */ 1306 get_cpu_address_sizes(&boot_cpu_data); 1307 1308 /* Let's presume PV guests always boot on vCPU with id 0. */ 1309 per_cpu(xen_vcpu_id, 0) = 0; 1310 1311 idt_setup_early_handler(); 1312 1313 xen_init_capabilities(); 1314 1315 #ifdef CONFIG_X86_LOCAL_APIC 1316 /* 1317 * set up the basic apic ops. 1318 */ 1319 xen_init_apic(); 1320 #endif 1321 1322 machine_ops = xen_machine_ops; 1323 1324 /* 1325 * The only reliable way to retain the initial address of the 1326 * percpu gdt_page is to remember it here, so we can go and 1327 * mark it RW later, when the initial percpu area is freed. 1328 */ 1329 xen_initial_gdt = &per_cpu(gdt_page, 0); 1330 1331 xen_smp_init(); 1332 1333 #ifdef CONFIG_ACPI_NUMA 1334 /* 1335 * The pages we from Xen are not related to machine pages, so 1336 * any NUMA information the kernel tries to get from ACPI will 1337 * be meaningless. Prevent it from trying. 1338 */ 1339 disable_srat(); 1340 #endif 1341 WARN_ON(xen_cpuhp_setup(xen_cpu_up_prepare_pv, xen_cpu_dead_pv)); 1342 1343 local_irq_disable(); 1344 early_boot_irqs_disabled = true; 1345 1346 xen_raw_console_write("mapping kernel into physical memory\n"); 1347 xen_setup_kernel_pagetable((pgd_t *)xen_start_info->pt_base, 1348 xen_start_info->nr_pages); 1349 xen_reserve_special_pages(); 1350 1351 /* 1352 * We used to do this in xen_arch_setup, but that is too late 1353 * on AMD were early_cpu_init (run before ->arch_setup()) calls 1354 * early_amd_init which pokes 0xcf8 port. 1355 */ 1356 set_iopl.iopl = 1; 1357 rc = HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl); 1358 if (rc != 0) 1359 xen_raw_printk("physdev_op failed %d\n", rc); 1360 1361 1362 if (xen_start_info->mod_start) { 1363 if (xen_start_info->flags & SIF_MOD_START_PFN) 1364 initrd_start = PFN_PHYS(xen_start_info->mod_start); 1365 else 1366 initrd_start = __pa(xen_start_info->mod_start); 1367 } 1368 1369 /* Poke various useful things into boot_params */ 1370 boot_params.hdr.type_of_loader = (9 << 4) | 0; 1371 boot_params.hdr.ramdisk_image = initrd_start; 1372 boot_params.hdr.ramdisk_size = xen_start_info->mod_len; 1373 boot_params.hdr.cmd_line_ptr = __pa(xen_start_info->cmd_line); 1374 boot_params.hdr.hardware_subarch = X86_SUBARCH_XEN; 1375 1376 if (!xen_initial_domain()) { 1377 if (pci_xen) 1378 x86_init.pci.arch_init = pci_xen_init; 1379 x86_platform.set_legacy_features = 1380 xen_domu_set_legacy_features; 1381 } else { 1382 const struct dom0_vga_console_info *info = 1383 (void *)((char *)xen_start_info + 1384 xen_start_info->console.dom0.info_off); 1385 struct xen_platform_op op = { 1386 .cmd = XENPF_firmware_info, 1387 .interface_version = XENPF_INTERFACE_VERSION, 1388 .u.firmware_info.type = XEN_FW_KBD_SHIFT_FLAGS, 1389 }; 1390 1391 x86_platform.set_legacy_features = 1392 xen_dom0_set_legacy_features; 1393 xen_init_vga(info, xen_start_info->console.dom0.info_size, 1394 &boot_params.screen_info); 1395 xen_start_info->console.domU.mfn = 0; 1396 xen_start_info->console.domU.evtchn = 0; 1397 1398 if (HYPERVISOR_platform_op(&op) == 0) 1399 boot_params.kbd_status = op.u.firmware_info.u.kbd_shift_flags; 1400 1401 /* Make sure ACS will be enabled */ 1402 pci_request_acs(); 1403 1404 xen_acpi_sleep_register(); 1405 1406 xen_boot_params_init_edd(); 1407 1408 #ifdef CONFIG_ACPI 1409 /* 1410 * Disable selecting "Firmware First mode" for correctable 1411 * memory errors, as this is the duty of the hypervisor to 1412 * decide. 1413 */ 1414 acpi_disable_cmcff = 1; 1415 #endif 1416 } 1417 1418 xen_add_preferred_consoles(); 1419 1420 #ifdef CONFIG_PCI 1421 /* PCI BIOS service won't work from a PV guest. */ 1422 pci_probe &= ~PCI_PROBE_BIOS; 1423 #endif 1424 xen_raw_console_write("about to get started...\n"); 1425 1426 /* We need this for printk timestamps */ 1427 xen_setup_runstate_info(0); 1428 1429 xen_efi_init(&boot_params); 1430 1431 /* Start the world */ 1432 cr4_init_shadow(); /* 32b kernel does this in i386_start_kernel() */ 1433 x86_64_start_reservations((char *)__pa_symbol(&boot_params)); 1434 } 1435 1436 static int xen_cpu_up_prepare_pv(unsigned int cpu) 1437 { 1438 int rc; 1439 1440 if (per_cpu(xen_vcpu, cpu) == NULL) 1441 return -ENODEV; 1442 1443 xen_setup_timer(cpu); 1444 1445 rc = xen_smp_intr_init(cpu); 1446 if (rc) { 1447 WARN(1, "xen_smp_intr_init() for CPU %d failed: %d\n", 1448 cpu, rc); 1449 return rc; 1450 } 1451 1452 rc = xen_smp_intr_init_pv(cpu); 1453 if (rc) { 1454 WARN(1, "xen_smp_intr_init_pv() for CPU %d failed: %d\n", 1455 cpu, rc); 1456 return rc; 1457 } 1458 1459 return 0; 1460 } 1461 1462 static int xen_cpu_dead_pv(unsigned int cpu) 1463 { 1464 xen_smp_intr_free(cpu); 1465 xen_smp_intr_free_pv(cpu); 1466 1467 xen_teardown_timer(cpu); 1468 1469 return 0; 1470 } 1471 1472 static uint32_t __init xen_platform_pv(void) 1473 { 1474 if (xen_pv_domain()) 1475 return xen_cpuid_base(); 1476 1477 return 0; 1478 } 1479 1480 const __initconst struct hypervisor_x86 x86_hyper_xen_pv = { 1481 .name = "Xen PV", 1482 .detect = xen_platform_pv, 1483 .type = X86_HYPER_XEN_PV, 1484 .runtime.pin_vcpu = xen_pin_vcpu, 1485 .ignore_nopv = true, 1486 }; 1487