1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_TPC5_CFG_REGS_H_ 14 #define ASIC_REG_TPC5_CFG_REGS_H_ 15 16 /* 17 ***************************************** 18 * TPC5_CFG (Prototype: TPC) 19 ***************************************** 20 */ 21 22 #define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF46400 23 24 #define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF46404 25 26 #define mmTPC5_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF46408 27 28 #define mmTPC5_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF4640C 29 30 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF46410 31 32 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF46414 33 34 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF46418 35 36 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF4641C 37 38 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF46420 39 40 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF46424 41 42 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF46428 43 44 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF4642C 45 46 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF46430 47 48 #define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF46434 49 50 #define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF46438 51 52 #define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF4643C 53 54 #define mmTPC5_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF46440 55 56 #define mmTPC5_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF46444 57 58 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF46448 59 60 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF4644C 61 62 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF46450 63 64 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF46454 65 66 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF46458 67 68 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF4645C 69 70 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF46460 71 72 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF46464 73 74 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF46468 75 76 #define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF4646C 77 78 #define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF46470 79 80 #define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF46474 81 82 #define mmTPC5_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF46478 83 84 #define mmTPC5_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF4647C 85 86 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF46480 87 88 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF46484 89 90 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF46488 91 92 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF4648C 93 94 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF46490 95 96 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF46494 97 98 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF46498 99 100 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF4649C 101 102 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF464A0 103 104 #define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF464A4 105 106 #define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF464A8 107 108 #define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF464AC 109 110 #define mmTPC5_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF464B0 111 112 #define mmTPC5_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF464B4 113 114 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF464B8 115 116 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF464BC 117 118 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF464C0 119 120 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF464C4 121 122 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF464C8 123 124 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF464CC 125 126 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF464D0 127 128 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF464D4 129 130 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF464D8 131 132 #define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF464DC 133 134 #define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF464E0 135 136 #define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF464E4 137 138 #define mmTPC5_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF464E8 139 140 #define mmTPC5_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF464EC 141 142 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF464F0 143 144 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF464F4 145 146 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF464F8 147 148 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF464FC 149 150 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF46500 151 152 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF46504 153 154 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF46508 155 156 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF4650C 157 158 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF46510 159 160 #define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF46514 161 162 #define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF46518 163 164 #define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF4651C 165 166 #define mmTPC5_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF46520 167 168 #define mmTPC5_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF46524 169 170 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF46528 171 172 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF4652C 173 174 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF46530 175 176 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF46534 177 178 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF46538 179 180 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF4653C 181 182 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF46540 183 184 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF46544 185 186 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF46548 187 188 #define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF4654C 189 190 #define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF46550 191 192 #define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF46554 193 194 #define mmTPC5_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF46558 195 196 #define mmTPC5_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF4655C 197 198 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF46560 199 200 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF46564 201 202 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF46568 203 204 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF4656C 205 206 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF46570 207 208 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF46574 209 210 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF46578 211 212 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF4657C 213 214 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF46580 215 216 #define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF46584 217 218 #define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF46588 219 220 #define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF4658C 221 222 #define mmTPC5_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF46590 223 224 #define mmTPC5_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF46594 225 226 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF46598 227 228 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF4659C 229 230 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF465A0 231 232 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF465A4 233 234 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF465A8 235 236 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF465AC 237 238 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF465B0 239 240 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF465B4 241 242 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF465B8 243 244 #define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF465BC 245 246 #define mmTPC5_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xF465C0 247 248 #define mmTPC5_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xF465C4 249 250 #define mmTPC5_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xF465C8 251 252 #define mmTPC5_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xF465CC 253 254 #define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xF465D0 255 256 #define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xF465D4 257 258 #define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xF465D8 259 260 #define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xF465DC 261 262 #define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xF465E0 263 264 #define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xF465E4 265 266 #define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xF465E8 267 268 #define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xF465EC 269 270 #define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xF465F0 271 272 #define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xF465F4 273 274 #define mmTPC5_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xF465F8 275 276 #define mmTPC5_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xF465FC 277 278 #define mmTPC5_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xF46600 279 280 #define mmTPC5_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xF46604 281 282 #define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xF46608 283 284 #define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xF4660C 285 286 #define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xF46610 287 288 #define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xF46614 289 290 #define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xF46618 291 292 #define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xF4661C 293 294 #define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xF46620 295 296 #define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xF46624 297 298 #define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xF46628 299 300 #define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xF4662C 301 302 #define mmTPC5_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xF46630 303 304 #define mmTPC5_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xF46634 305 306 #define mmTPC5_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xF46638 307 308 #define mmTPC5_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xF4663C 309 310 #define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xF46640 311 312 #define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xF46644 313 314 #define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xF46648 315 316 #define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xF4664C 317 318 #define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xF46650 319 320 #define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xF46654 321 322 #define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xF46658 323 324 #define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xF4665C 325 326 #define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xF46660 327 328 #define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xF46664 329 330 #define mmTPC5_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xF46668 331 332 #define mmTPC5_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xF4666C 333 334 #define mmTPC5_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xF46670 335 336 #define mmTPC5_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xF46674 337 338 #define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xF46678 339 340 #define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xF4667C 341 342 #define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xF46680 343 344 #define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xF46684 345 346 #define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xF46688 347 348 #define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xF4668C 349 350 #define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xF46690 351 352 #define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xF46694 353 354 #define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xF46698 355 356 #define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xF4669C 357 358 #define mmTPC5_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xF466A0 359 360 #define mmTPC5_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xF466A4 361 362 #define mmTPC5_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xF466A8 363 364 #define mmTPC5_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xF466AC 365 366 #define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xF466B0 367 368 #define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xF466B4 369 370 #define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xF466B8 371 372 #define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xF466BC 373 374 #define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xF466C0 375 376 #define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xF466C4 377 378 #define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xF466C8 379 380 #define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xF466CC 381 382 #define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xF466D0 383 384 #define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xF466D4 385 386 #define mmTPC5_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xF466D8 387 388 #define mmTPC5_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xF466DC 389 390 #define mmTPC5_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xF466E0 391 392 #define mmTPC5_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xF466E4 393 394 #define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xF466E8 395 396 #define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xF466EC 397 398 #define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xF466F0 399 400 #define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xF466F4 401 402 #define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xF466F8 403 404 #define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xF466FC 405 406 #define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xF46700 407 408 #define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xF46704 409 410 #define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xF46708 411 412 #define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xF4670C 413 414 #define mmTPC5_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xF46710 415 416 #define mmTPC5_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xF46714 417 418 #define mmTPC5_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xF46718 419 420 #define mmTPC5_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xF4671C 421 422 #define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xF46720 423 424 #define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xF46724 425 426 #define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xF46728 427 428 #define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xF4672C 429 430 #define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xF46730 431 432 #define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xF46734 433 434 #define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xF46738 435 436 #define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xF4673C 437 438 #define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xF46740 439 440 #define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xF46744 441 442 #define mmTPC5_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xF46748 443 444 #define mmTPC5_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xF4674C 445 446 #define mmTPC5_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xF46750 447 448 #define mmTPC5_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xF46754 449 450 #define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xF46758 451 452 #define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xF4675C 453 454 #define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xF46760 455 456 #define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xF46764 457 458 #define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xF46768 459 460 #define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xF4676C 461 462 #define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xF46770 463 464 #define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xF46774 465 466 #define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xF46778 467 468 #define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xF4677C 469 470 #define mmTPC5_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF46780 471 472 #define mmTPC5_CFG_KERNEL_SYNC_OBJECT_ADDR 0xF46784 473 474 #define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF46788 475 476 #define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF4678C 477 478 #define mmTPC5_CFG_KERNEL_TID_BASE_DIM_0 0xF46790 479 480 #define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_0 0xF46794 481 482 #define mmTPC5_CFG_KERNEL_TID_BASE_DIM_1 0xF46798 483 484 #define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_1 0xF4679C 485 486 #define mmTPC5_CFG_KERNEL_TID_BASE_DIM_2 0xF467A0 487 488 #define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_2 0xF467A4 489 490 #define mmTPC5_CFG_KERNEL_TID_BASE_DIM_3 0xF467A8 491 492 #define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_3 0xF467AC 493 494 #define mmTPC5_CFG_KERNEL_TID_BASE_DIM_4 0xF467B0 495 496 #define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_4 0xF467B4 497 498 #define mmTPC5_CFG_KERNEL_KERNEL_CONFIG 0xF467B8 499 500 #define mmTPC5_CFG_KERNEL_KERNEL_ID 0xF467BC 501 502 #define mmTPC5_CFG_KERNEL_SRF_0 0xF467C0 503 504 #define mmTPC5_CFG_KERNEL_SRF_1 0xF467C4 505 506 #define mmTPC5_CFG_KERNEL_SRF_2 0xF467C8 507 508 #define mmTPC5_CFG_KERNEL_SRF_3 0xF467CC 509 510 #define mmTPC5_CFG_KERNEL_SRF_4 0xF467D0 511 512 #define mmTPC5_CFG_KERNEL_SRF_5 0xF467D4 513 514 #define mmTPC5_CFG_KERNEL_SRF_6 0xF467D8 515 516 #define mmTPC5_CFG_KERNEL_SRF_7 0xF467DC 517 518 #define mmTPC5_CFG_KERNEL_SRF_8 0xF467E0 519 520 #define mmTPC5_CFG_KERNEL_SRF_9 0xF467E4 521 522 #define mmTPC5_CFG_KERNEL_SRF_10 0xF467E8 523 524 #define mmTPC5_CFG_KERNEL_SRF_11 0xF467EC 525 526 #define mmTPC5_CFG_KERNEL_SRF_12 0xF467F0 527 528 #define mmTPC5_CFG_KERNEL_SRF_13 0xF467F4 529 530 #define mmTPC5_CFG_KERNEL_SRF_14 0xF467F8 531 532 #define mmTPC5_CFG_KERNEL_SRF_15 0xF467FC 533 534 #define mmTPC5_CFG_KERNEL_SRF_16 0xF46800 535 536 #define mmTPC5_CFG_KERNEL_SRF_17 0xF46804 537 538 #define mmTPC5_CFG_KERNEL_SRF_18 0xF46808 539 540 #define mmTPC5_CFG_KERNEL_SRF_19 0xF4680C 541 542 #define mmTPC5_CFG_KERNEL_SRF_20 0xF46810 543 544 #define mmTPC5_CFG_KERNEL_SRF_21 0xF46814 545 546 #define mmTPC5_CFG_KERNEL_SRF_22 0xF46818 547 548 #define mmTPC5_CFG_KERNEL_SRF_23 0xF4681C 549 550 #define mmTPC5_CFG_KERNEL_SRF_24 0xF46820 551 552 #define mmTPC5_CFG_KERNEL_SRF_25 0xF46824 553 554 #define mmTPC5_CFG_KERNEL_SRF_26 0xF46828 555 556 #define mmTPC5_CFG_KERNEL_SRF_27 0xF4682C 557 558 #define mmTPC5_CFG_KERNEL_SRF_28 0xF46830 559 560 #define mmTPC5_CFG_KERNEL_SRF_29 0xF46834 561 562 #define mmTPC5_CFG_KERNEL_SRF_30 0xF46838 563 564 #define mmTPC5_CFG_KERNEL_SRF_31 0xF4683C 565 566 #define mmTPC5_CFG_ROUND_CSR 0xF468FC 567 568 #define mmTPC5_CFG_PROT 0xF46900 569 570 #define mmTPC5_CFG_SEMAPHORE 0xF46908 571 572 #define mmTPC5_CFG_VFLAGS 0xF4690C 573 574 #define mmTPC5_CFG_SFLAGS 0xF46910 575 576 #define mmTPC5_CFG_LFSR_POLYNOM 0xF46918 577 578 #define mmTPC5_CFG_STATUS 0xF4691C 579 580 #define mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH 0xF46920 581 582 #define mmTPC5_CFG_CFG_SUBTRACT_VALUE 0xF46924 583 584 #define mmTPC5_CFG_SM_BASE_ADDRESS_HIGH 0xF4692C 585 586 #define mmTPC5_CFG_TPC_CMD 0xF46930 587 588 #define mmTPC5_CFG_TPC_EXECUTE 0xF46938 589 590 #define mmTPC5_CFG_TPC_STALL 0xF4693C 591 592 #define mmTPC5_CFG_ICACHE_BASE_ADDERESS_LOW 0xF46940 593 594 #define mmTPC5_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF46944 595 596 #define mmTPC5_CFG_RD_RATE_LIMIT 0xF46948 597 598 #define mmTPC5_CFG_WR_RATE_LIMIT 0xF46950 599 600 #define mmTPC5_CFG_MSS_CONFIG 0xF46954 601 602 #define mmTPC5_CFG_TPC_INTR_CAUSE 0xF46958 603 604 #define mmTPC5_CFG_TPC_INTR_MASK 0xF4695C 605 606 #define mmTPC5_CFG_WQ_CREDITS 0xF46960 607 608 #define mmTPC5_CFG_ARUSER_LO 0xF46964 609 610 #define mmTPC5_CFG_ARUSER_HI 0xF46968 611 612 #define mmTPC5_CFG_AWUSER_LO 0xF4696C 613 614 #define mmTPC5_CFG_AWUSER_HI 0xF46970 615 616 #define mmTPC5_CFG_OPCODE_EXEC 0xF46974 617 618 #define mmTPC5_CFG_LUT_FUNC32_BASE_ADDR_LO 0xF46978 619 620 #define mmTPC5_CFG_LUT_FUNC32_BASE_ADDR_HI 0xF4697C 621 622 #define mmTPC5_CFG_LUT_FUNC64_BASE_ADDR_LO 0xF46980 623 624 #define mmTPC5_CFG_LUT_FUNC64_BASE_ADDR_HI 0xF46984 625 626 #define mmTPC5_CFG_LUT_FUNC128_BASE_ADDR_LO 0xF46988 627 628 #define mmTPC5_CFG_LUT_FUNC128_BASE_ADDR_HI 0xF4698C 629 630 #define mmTPC5_CFG_LUT_FUNC256_BASE_ADDR_LO 0xF46990 631 632 #define mmTPC5_CFG_LUT_FUNC256_BASE_ADDR_HI 0xF46994 633 634 #define mmTPC5_CFG_TSB_CFG_MAX_SIZE 0xF46998 635 636 #define mmTPC5_CFG_TSB_CFG 0xF4699C 637 638 #define mmTPC5_CFG_DBGMEM_ADD 0xF469A0 639 640 #define mmTPC5_CFG_DBGMEM_DATA_WR 0xF469A4 641 642 #define mmTPC5_CFG_DBGMEM_DATA_RD 0xF469A8 643 644 #define mmTPC5_CFG_DBGMEM_CTRL 0xF469AC 645 646 #define mmTPC5_CFG_DBGMEM_RC 0xF469B0 647 648 #define mmTPC5_CFG_TSB_INFLIGHT_CNTR 0xF469B4 649 650 #define mmTPC5_CFG_WQ_INFLIGHT_CNTR 0xF469B8 651 652 #define mmTPC5_CFG_WQ_LBW_TOTAL_CNTR 0xF469BC 653 654 #define mmTPC5_CFG_WQ_HBW_TOTAL_CNTR 0xF469C0 655 656 #define mmTPC5_CFG_IRQ_OCCOUPY_CNTR 0xF469C4 657 658 #define mmTPC5_CFG_FUNC_MBIST_CNTRL 0xF469D0 659 660 #define mmTPC5_CFG_FUNC_MBIST_PAT 0xF469D4 661 662 #define mmTPC5_CFG_FUNC_MBIST_MEM_0 0xF469D8 663 664 #define mmTPC5_CFG_FUNC_MBIST_MEM_1 0xF469DC 665 666 #define mmTPC5_CFG_FUNC_MBIST_MEM_2 0xF469E0 667 668 #define mmTPC5_CFG_FUNC_MBIST_MEM_3 0xF469E4 669 670 #define mmTPC5_CFG_FUNC_MBIST_MEM_4 0xF469E8 671 672 #define mmTPC5_CFG_FUNC_MBIST_MEM_5 0xF469EC 673 674 #define mmTPC5_CFG_FUNC_MBIST_MEM_6 0xF469F0 675 676 #define mmTPC5_CFG_FUNC_MBIST_MEM_7 0xF469F4 677 678 #define mmTPC5_CFG_FUNC_MBIST_MEM_8 0xF469F8 679 680 #define mmTPC5_CFG_FUNC_MBIST_MEM_9 0xF469FC 681 682 #define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF46A00 683 684 #define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF46A04 685 686 #define mmTPC5_CFG_QM_TENSOR_0_PADDING_VALUE 0xF46A08 687 688 #define mmTPC5_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF46A0C 689 690 #define mmTPC5_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF46A10 691 692 #define mmTPC5_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF46A14 693 694 #define mmTPC5_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF46A18 695 696 #define mmTPC5_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF46A1C 697 698 #define mmTPC5_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF46A20 699 700 #define mmTPC5_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF46A24 701 702 #define mmTPC5_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF46A28 703 704 #define mmTPC5_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF46A2C 705 706 #define mmTPC5_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF46A30 707 708 #define mmTPC5_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF46A34 709 710 #define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF46A38 711 712 #define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF46A3C 713 714 #define mmTPC5_CFG_QM_TENSOR_1_PADDING_VALUE 0xF46A40 715 716 #define mmTPC5_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF46A44 717 718 #define mmTPC5_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF46A48 719 720 #define mmTPC5_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF46A4C 721 722 #define mmTPC5_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF46A50 723 724 #define mmTPC5_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF46A54 725 726 #define mmTPC5_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF46A58 727 728 #define mmTPC5_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF46A5C 729 730 #define mmTPC5_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF46A60 731 732 #define mmTPC5_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF46A64 733 734 #define mmTPC5_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF46A68 735 736 #define mmTPC5_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF46A6C 737 738 #define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF46A70 739 740 #define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF46A74 741 742 #define mmTPC5_CFG_QM_TENSOR_2_PADDING_VALUE 0xF46A78 743 744 #define mmTPC5_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF46A7C 745 746 #define mmTPC5_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF46A80 747 748 #define mmTPC5_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF46A84 749 750 #define mmTPC5_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF46A88 751 752 #define mmTPC5_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF46A8C 753 754 #define mmTPC5_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF46A90 755 756 #define mmTPC5_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF46A94 757 758 #define mmTPC5_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF46A98 759 760 #define mmTPC5_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF46A9C 761 762 #define mmTPC5_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF46AA0 763 764 #define mmTPC5_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF46AA4 765 766 #define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF46AA8 767 768 #define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF46AAC 769 770 #define mmTPC5_CFG_QM_TENSOR_3_PADDING_VALUE 0xF46AB0 771 772 #define mmTPC5_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF46AB4 773 774 #define mmTPC5_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF46AB8 775 776 #define mmTPC5_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF46ABC 777 778 #define mmTPC5_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF46AC0 779 780 #define mmTPC5_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF46AC4 781 782 #define mmTPC5_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF46AC8 783 784 #define mmTPC5_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF46ACC 785 786 #define mmTPC5_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF46AD0 787 788 #define mmTPC5_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF46AD4 789 790 #define mmTPC5_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF46AD8 791 792 #define mmTPC5_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF46ADC 793 794 #define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF46AE0 795 796 #define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF46AE4 797 798 #define mmTPC5_CFG_QM_TENSOR_4_PADDING_VALUE 0xF46AE8 799 800 #define mmTPC5_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF46AEC 801 802 #define mmTPC5_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF46AF0 803 804 #define mmTPC5_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF46AF4 805 806 #define mmTPC5_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF46AF8 807 808 #define mmTPC5_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF46AFC 809 810 #define mmTPC5_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF46B00 811 812 #define mmTPC5_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF46B04 813 814 #define mmTPC5_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF46B08 815 816 #define mmTPC5_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF46B0C 817 818 #define mmTPC5_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF46B10 819 820 #define mmTPC5_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF46B14 821 822 #define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF46B18 823 824 #define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF46B1C 825 826 #define mmTPC5_CFG_QM_TENSOR_5_PADDING_VALUE 0xF46B20 827 828 #define mmTPC5_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF46B24 829 830 #define mmTPC5_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF46B28 831 832 #define mmTPC5_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF46B2C 833 834 #define mmTPC5_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF46B30 835 836 #define mmTPC5_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF46B34 837 838 #define mmTPC5_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF46B38 839 840 #define mmTPC5_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF46B3C 841 842 #define mmTPC5_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF46B40 843 844 #define mmTPC5_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF46B44 845 846 #define mmTPC5_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF46B48 847 848 #define mmTPC5_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF46B4C 849 850 #define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF46B50 851 852 #define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF46B54 853 854 #define mmTPC5_CFG_QM_TENSOR_6_PADDING_VALUE 0xF46B58 855 856 #define mmTPC5_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF46B5C 857 858 #define mmTPC5_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF46B60 859 860 #define mmTPC5_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF46B64 861 862 #define mmTPC5_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF46B68 863 864 #define mmTPC5_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF46B6C 865 866 #define mmTPC5_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF46B70 867 868 #define mmTPC5_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF46B74 869 870 #define mmTPC5_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF46B78 871 872 #define mmTPC5_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF46B7C 873 874 #define mmTPC5_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF46B80 875 876 #define mmTPC5_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF46B84 877 878 #define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF46B88 879 880 #define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF46B8C 881 882 #define mmTPC5_CFG_QM_TENSOR_7_PADDING_VALUE 0xF46B90 883 884 #define mmTPC5_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF46B94 885 886 #define mmTPC5_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF46B98 887 888 #define mmTPC5_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF46B9C 889 890 #define mmTPC5_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF46BA0 891 892 #define mmTPC5_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF46BA4 893 894 #define mmTPC5_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF46BA8 895 896 #define mmTPC5_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF46BAC 897 898 #define mmTPC5_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF46BB0 899 900 #define mmTPC5_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF46BB4 901 902 #define mmTPC5_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF46BB8 903 904 #define mmTPC5_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF46BBC 905 906 #define mmTPC5_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xF46BC0 907 908 #define mmTPC5_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xF46BC4 909 910 #define mmTPC5_CFG_QM_TENSOR_8_PADDING_VALUE 0xF46BC8 911 912 #define mmTPC5_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xF46BCC 913 914 #define mmTPC5_CFG_QM_TENSOR_8_DIM_0_SIZE 0xF46BD0 915 916 #define mmTPC5_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xF46BD4 917 918 #define mmTPC5_CFG_QM_TENSOR_8_DIM_1_SIZE 0xF46BD8 919 920 #define mmTPC5_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xF46BDC 921 922 #define mmTPC5_CFG_QM_TENSOR_8_DIM_2_SIZE 0xF46BE0 923 924 #define mmTPC5_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xF46BE4 925 926 #define mmTPC5_CFG_QM_TENSOR_8_DIM_3_SIZE 0xF46BE8 927 928 #define mmTPC5_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xF46BEC 929 930 #define mmTPC5_CFG_QM_TENSOR_8_DIM_4_SIZE 0xF46BF0 931 932 #define mmTPC5_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xF46BF4 933 934 #define mmTPC5_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xF46BF8 935 936 #define mmTPC5_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xF46BFC 937 938 #define mmTPC5_CFG_QM_TENSOR_9_PADDING_VALUE 0xF46C00 939 940 #define mmTPC5_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xF46C04 941 942 #define mmTPC5_CFG_QM_TENSOR_9_DIM_0_SIZE 0xF46C08 943 944 #define mmTPC5_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xF46C0C 945 946 #define mmTPC5_CFG_QM_TENSOR_9_DIM_1_SIZE 0xF46C10 947 948 #define mmTPC5_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xF46C14 949 950 #define mmTPC5_CFG_QM_TENSOR_9_DIM_2_SIZE 0xF46C18 951 952 #define mmTPC5_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xF46C1C 953 954 #define mmTPC5_CFG_QM_TENSOR_9_DIM_3_SIZE 0xF46C20 955 956 #define mmTPC5_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xF46C24 957 958 #define mmTPC5_CFG_QM_TENSOR_9_DIM_4_SIZE 0xF46C28 959 960 #define mmTPC5_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xF46C2C 961 962 #define mmTPC5_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xF46C30 963 964 #define mmTPC5_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xF46C34 965 966 #define mmTPC5_CFG_QM_TENSOR_10_PADDING_VALUE 0xF46C38 967 968 #define mmTPC5_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xF46C3C 969 970 #define mmTPC5_CFG_QM_TENSOR_10_DIM_0_SIZE 0xF46C40 971 972 #define mmTPC5_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xF46C44 973 974 #define mmTPC5_CFG_QM_TENSOR_10_DIM_1_SIZE 0xF46C48 975 976 #define mmTPC5_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xF46C4C 977 978 #define mmTPC5_CFG_QM_TENSOR_10_DIM_2_SIZE 0xF46C50 979 980 #define mmTPC5_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xF46C54 981 982 #define mmTPC5_CFG_QM_TENSOR_10_DIM_3_SIZE 0xF46C58 983 984 #define mmTPC5_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xF46C5C 985 986 #define mmTPC5_CFG_QM_TENSOR_10_DIM_4_SIZE 0xF46C60 987 988 #define mmTPC5_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xF46C64 989 990 #define mmTPC5_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xF46C68 991 992 #define mmTPC5_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xF46C6C 993 994 #define mmTPC5_CFG_QM_TENSOR_11_PADDING_VALUE 0xF46C70 995 996 #define mmTPC5_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xF46C74 997 998 #define mmTPC5_CFG_QM_TENSOR_11_DIM_0_SIZE 0xF46C78 999 1000 #define mmTPC5_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xF46C7C 1001 1002 #define mmTPC5_CFG_QM_TENSOR_11_DIM_1_SIZE 0xF46C80 1003 1004 #define mmTPC5_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xF46C84 1005 1006 #define mmTPC5_CFG_QM_TENSOR_11_DIM_2_SIZE 0xF46C88 1007 1008 #define mmTPC5_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xF46C8C 1009 1010 #define mmTPC5_CFG_QM_TENSOR_11_DIM_3_SIZE 0xF46C90 1011 1012 #define mmTPC5_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xF46C94 1013 1014 #define mmTPC5_CFG_QM_TENSOR_11_DIM_4_SIZE 0xF46C98 1015 1016 #define mmTPC5_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xF46C9C 1017 1018 #define mmTPC5_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xF46CA0 1019 1020 #define mmTPC5_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xF46CA4 1021 1022 #define mmTPC5_CFG_QM_TENSOR_12_PADDING_VALUE 0xF46CA8 1023 1024 #define mmTPC5_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xF46CAC 1025 1026 #define mmTPC5_CFG_QM_TENSOR_12_DIM_0_SIZE 0xF46CB0 1027 1028 #define mmTPC5_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xF46CB4 1029 1030 #define mmTPC5_CFG_QM_TENSOR_12_DIM_1_SIZE 0xF46CB8 1031 1032 #define mmTPC5_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xF46CBC 1033 1034 #define mmTPC5_CFG_QM_TENSOR_12_DIM_2_SIZE 0xF46CC0 1035 1036 #define mmTPC5_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xF46CC4 1037 1038 #define mmTPC5_CFG_QM_TENSOR_12_DIM_3_SIZE 0xF46CC8 1039 1040 #define mmTPC5_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xF46CCC 1041 1042 #define mmTPC5_CFG_QM_TENSOR_12_DIM_4_SIZE 0xF46CD0 1043 1044 #define mmTPC5_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xF46CD4 1045 1046 #define mmTPC5_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xF46CD8 1047 1048 #define mmTPC5_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xF46CDC 1049 1050 #define mmTPC5_CFG_QM_TENSOR_13_PADDING_VALUE 0xF46CE0 1051 1052 #define mmTPC5_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xF46CE4 1053 1054 #define mmTPC5_CFG_QM_TENSOR_13_DIM_0_SIZE 0xF46CE8 1055 1056 #define mmTPC5_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xF46CEC 1057 1058 #define mmTPC5_CFG_QM_TENSOR_13_DIM_1_SIZE 0xF46CF0 1059 1060 #define mmTPC5_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xF46CF4 1061 1062 #define mmTPC5_CFG_QM_TENSOR_13_DIM_2_SIZE 0xF46CF8 1063 1064 #define mmTPC5_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xF46CFC 1065 1066 #define mmTPC5_CFG_QM_TENSOR_13_DIM_3_SIZE 0xF46D00 1067 1068 #define mmTPC5_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xF46D04 1069 1070 #define mmTPC5_CFG_QM_TENSOR_13_DIM_4_SIZE 0xF46D08 1071 1072 #define mmTPC5_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xF46D0C 1073 1074 #define mmTPC5_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xF46D10 1075 1076 #define mmTPC5_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xF46D14 1077 1078 #define mmTPC5_CFG_QM_TENSOR_14_PADDING_VALUE 0xF46D18 1079 1080 #define mmTPC5_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xF46D1C 1081 1082 #define mmTPC5_CFG_QM_TENSOR_14_DIM_0_SIZE 0xF46D20 1083 1084 #define mmTPC5_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xF46D24 1085 1086 #define mmTPC5_CFG_QM_TENSOR_14_DIM_1_SIZE 0xF46D28 1087 1088 #define mmTPC5_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xF46D2C 1089 1090 #define mmTPC5_CFG_QM_TENSOR_14_DIM_2_SIZE 0xF46D30 1091 1092 #define mmTPC5_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xF46D34 1093 1094 #define mmTPC5_CFG_QM_TENSOR_14_DIM_3_SIZE 0xF46D38 1095 1096 #define mmTPC5_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xF46D3C 1097 1098 #define mmTPC5_CFG_QM_TENSOR_14_DIM_4_SIZE 0xF46D40 1099 1100 #define mmTPC5_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xF46D44 1101 1102 #define mmTPC5_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xF46D48 1103 1104 #define mmTPC5_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xF46D4C 1105 1106 #define mmTPC5_CFG_QM_TENSOR_15_PADDING_VALUE 0xF46D50 1107 1108 #define mmTPC5_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xF46D54 1109 1110 #define mmTPC5_CFG_QM_TENSOR_15_DIM_0_SIZE 0xF46D58 1111 1112 #define mmTPC5_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xF46D5C 1113 1114 #define mmTPC5_CFG_QM_TENSOR_15_DIM_1_SIZE 0xF46D60 1115 1116 #define mmTPC5_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xF46D64 1117 1118 #define mmTPC5_CFG_QM_TENSOR_15_DIM_2_SIZE 0xF46D68 1119 1120 #define mmTPC5_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xF46D6C 1121 1122 #define mmTPC5_CFG_QM_TENSOR_15_DIM_3_SIZE 0xF46D70 1123 1124 #define mmTPC5_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xF46D74 1125 1126 #define mmTPC5_CFG_QM_TENSOR_15_DIM_4_SIZE 0xF46D78 1127 1128 #define mmTPC5_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xF46D7C 1129 1130 #define mmTPC5_CFG_QM_SYNC_OBJECT_MESSAGE 0xF46D80 1131 1132 #define mmTPC5_CFG_QM_SYNC_OBJECT_ADDR 0xF46D84 1133 1134 #define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF46D88 1135 1136 #define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF46D8C 1137 1138 #define mmTPC5_CFG_QM_TID_BASE_DIM_0 0xF46D90 1139 1140 #define mmTPC5_CFG_QM_TID_SIZE_DIM_0 0xF46D94 1141 1142 #define mmTPC5_CFG_QM_TID_BASE_DIM_1 0xF46D98 1143 1144 #define mmTPC5_CFG_QM_TID_SIZE_DIM_1 0xF46D9C 1145 1146 #define mmTPC5_CFG_QM_TID_BASE_DIM_2 0xF46DA0 1147 1148 #define mmTPC5_CFG_QM_TID_SIZE_DIM_2 0xF46DA4 1149 1150 #define mmTPC5_CFG_QM_TID_BASE_DIM_3 0xF46DA8 1151 1152 #define mmTPC5_CFG_QM_TID_SIZE_DIM_3 0xF46DAC 1153 1154 #define mmTPC5_CFG_QM_TID_BASE_DIM_4 0xF46DB0 1155 1156 #define mmTPC5_CFG_QM_TID_SIZE_DIM_4 0xF46DB4 1157 1158 #define mmTPC5_CFG_QM_KERNEL_CONFIG 0xF46DB8 1159 1160 #define mmTPC5_CFG_QM_KERNEL_ID 0xF46DBC 1161 1162 #define mmTPC5_CFG_QM_SRF_0 0xF46DC0 1163 1164 #define mmTPC5_CFG_QM_SRF_1 0xF46DC4 1165 1166 #define mmTPC5_CFG_QM_SRF_2 0xF46DC8 1167 1168 #define mmTPC5_CFG_QM_SRF_3 0xF46DCC 1169 1170 #define mmTPC5_CFG_QM_SRF_4 0xF46DD0 1171 1172 #define mmTPC5_CFG_QM_SRF_5 0xF46DD4 1173 1174 #define mmTPC5_CFG_QM_SRF_6 0xF46DD8 1175 1176 #define mmTPC5_CFG_QM_SRF_7 0xF46DDC 1177 1178 #define mmTPC5_CFG_QM_SRF_8 0xF46DE0 1179 1180 #define mmTPC5_CFG_QM_SRF_9 0xF46DE4 1181 1182 #define mmTPC5_CFG_QM_SRF_10 0xF46DE8 1183 1184 #define mmTPC5_CFG_QM_SRF_11 0xF46DEC 1185 1186 #define mmTPC5_CFG_QM_SRF_12 0xF46DF0 1187 1188 #define mmTPC5_CFG_QM_SRF_13 0xF46DF4 1189 1190 #define mmTPC5_CFG_QM_SRF_14 0xF46DF8 1191 1192 #define mmTPC5_CFG_QM_SRF_15 0xF46DFC 1193 1194 #define mmTPC5_CFG_QM_SRF_16 0xF46E00 1195 1196 #define mmTPC5_CFG_QM_SRF_17 0xF46E04 1197 1198 #define mmTPC5_CFG_QM_SRF_18 0xF46E08 1199 1200 #define mmTPC5_CFG_QM_SRF_19 0xF46E0C 1201 1202 #define mmTPC5_CFG_QM_SRF_20 0xF46E10 1203 1204 #define mmTPC5_CFG_QM_SRF_21 0xF46E14 1205 1206 #define mmTPC5_CFG_QM_SRF_22 0xF46E18 1207 1208 #define mmTPC5_CFG_QM_SRF_23 0xF46E1C 1209 1210 #define mmTPC5_CFG_QM_SRF_24 0xF46E20 1211 1212 #define mmTPC5_CFG_QM_SRF_25 0xF46E24 1213 1214 #define mmTPC5_CFG_QM_SRF_26 0xF46E28 1215 1216 #define mmTPC5_CFG_QM_SRF_27 0xF46E2C 1217 1218 #define mmTPC5_CFG_QM_SRF_28 0xF46E30 1219 1220 #define mmTPC5_CFG_QM_SRF_29 0xF46E34 1221 1222 #define mmTPC5_CFG_QM_SRF_30 0xF46E38 1223 1224 #define mmTPC5_CFG_QM_SRF_31 0xF46E3C 1225 1226 #endif /* ASIC_REG_TPC5_CFG_REGS_H_ */ 1227