1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_MASKS_H_ 14 #define ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_MASKS_H_ 15 16 /* 17 ***************************************** 18 * ARC_FARM_KDMA_CTX_AXUSER 19 * (Prototype: AXUSER) 20 ***************************************** 21 */ 22 23 /* ARC_FARM_KDMA_CTX_AXUSER_HB_ASID */ 24 #define ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_SHIFT 0 25 #define ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_MASK 0x3FF 26 #define ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_SHIFT 16 27 #define ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_MASK 0x3FF0000 28 29 /* ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP */ 30 #define ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_WR_SHIFT 0 31 #define ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_WR_MASK 0x1 32 #define ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_RD_SHIFT 4 33 #define ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_RD_MASK 0x10 34 35 /* ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER */ 36 #define ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER_WR_SHIFT 0 37 #define ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER_WR_MASK 0x1 38 #define ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER_RD_SHIFT 4 39 #define ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER_RD_MASK 0x10 40 41 /* ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP */ 42 #define ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP_WR_SHIFT 0 43 #define ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP_WR_MASK 0x1 44 #define ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP_RD_SHIFT 4 45 #define ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP_RD_MASK 0x10 46 47 /* ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION */ 48 #define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_IND_SHIFT 0 49 #define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_IND_MASK 0x1 50 #define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_DTYPE_SHIFT 4 51 #define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_DTYPE_MASK 0xF0 52 #define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_OP_SHIFT 8 53 #define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_OP_MASK 0x300 54 #define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_ROUND_SHIFT 12 55 #define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_ROUND_MASK 0x3000 56 #define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_MAX_SHIFT 16 57 #define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_MAX_MASK 0x10000 58 59 /* ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC */ 60 #define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_IND_SHIFT 0 61 #define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_IND_MASK 0x3 62 #define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_ADDITION_SIZE_SHIFT 4 63 #define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_ADDITION_SIZE_MASK 0xFF0 64 #define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_MSB_MASK_SHIFT 12 65 #define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_MSB_MASK_MASK 0x1F000 66 67 /* ARC_FARM_KDMA_CTX_AXUSER_HB_QOS */ 68 #define ARC_FARM_KDMA_CTX_AXUSER_HB_QOS_WR_SHIFT 0 69 #define ARC_FARM_KDMA_CTX_AXUSER_HB_QOS_WR_MASK 0xF 70 #define ARC_FARM_KDMA_CTX_AXUSER_HB_QOS_RD_SHIFT 4 71 #define ARC_FARM_KDMA_CTX_AXUSER_HB_QOS_RD_MASK 0x70 72 73 /* ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD */ 74 #define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_27_SHIFT 0 75 #define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_27_MASK 0x1 76 #define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_28_SHIFT 1 77 #define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_28_MASK 0x2 78 #define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_30_SHIFT 2 79 #define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_30_MASK 0x4 80 #define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_31_SHIFT 3 81 #define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_31_MASK 0x8 82 83 /* ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE */ 84 #define ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE_WR_SHIFT 0 85 #define ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE_WR_MASK 0x1 86 #define ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE_RD_SHIFT 4 87 #define ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE_RD_MASK 0x10 88 89 /* ARC_FARM_KDMA_CTX_AXUSER_HB_CORE */ 90 #define ARC_FARM_KDMA_CTX_AXUSER_HB_CORE_WR_SHIFT 0 91 #define ARC_FARM_KDMA_CTX_AXUSER_HB_CORE_WR_MASK 0x1 92 #define ARC_FARM_KDMA_CTX_AXUSER_HB_CORE_RD_SHIFT 4 93 #define ARC_FARM_KDMA_CTX_AXUSER_HB_CORE_RD_MASK 0x10 94 95 /* ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD */ 96 #define ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD_X_SHIFT 0 97 #define ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD_X_MASK 0x1F 98 #define ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD_Y_SHIFT 8 99 #define ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD_Y_MASK 0xF00 100 101 /* ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_LO */ 102 #define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_LO_VAL_SHIFT 0 103 #define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_LO_VAL_MASK 0xFFFFFFFF 104 105 /* ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_HI */ 106 #define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_HI_VAL_SHIFT 0 107 #define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_HI_VAL_MASK 0x3FF 108 109 /* ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_LO */ 110 #define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_LO_VAL_SHIFT 0 111 #define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_LO_VAL_MASK 0xFFFFFFFF 112 113 /* ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_HI */ 114 #define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_HI_VAL_SHIFT 0 115 #define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_HI_VAL_MASK 0x3FF 116 117 /* ARC_FARM_KDMA_CTX_AXUSER_LB_COORD */ 118 #define ARC_FARM_KDMA_CTX_AXUSER_LB_COORD_VAL_SHIFT 0 119 #define ARC_FARM_KDMA_CTX_AXUSER_LB_COORD_VAL_MASK 0x3FF 120 121 /* ARC_FARM_KDMA_CTX_AXUSER_LB_LOCK */ 122 #define ARC_FARM_KDMA_CTX_AXUSER_LB_LOCK_VAL_SHIFT 0 123 #define ARC_FARM_KDMA_CTX_AXUSER_LB_LOCK_VAL_MASK 0x1 124 125 /* ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD */ 126 #define ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD_BIT_21_11_SHIFT 0 127 #define ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD_BIT_21_11_MASK 0x7FF 128 #define ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD_BIT_22_SHIFT 12 129 #define ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD_BIT_22_MASK 0x1000 130 131 /* ARC_FARM_KDMA_CTX_AXUSER_LB_OVRD */ 132 #define ARC_FARM_KDMA_CTX_AXUSER_LB_OVRD_VAL_SHIFT 0 133 #define ARC_FARM_KDMA_CTX_AXUSER_LB_OVRD_VAL_MASK 0xFFFFFFFF 134 135 #endif /* ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_MASKS_H_ */ 136