1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2020 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_DCORE0_TPC0_EML_STM_REGS_H_
14 #define ASIC_REG_DCORE0_TPC0_EML_STM_REGS_H_
15 
16 /*
17  *****************************************
18  *   DCORE0_TPC0_EML_STM
19  *   (Prototype: STM)
20  *****************************************
21  */
22 
23 #define mmDCORE0_TPC0_EML_STM_STMDMASTARTR 0x3C04
24 
25 #define mmDCORE0_TPC0_EML_STM_STMDMASTOPR 0x3C08
26 
27 #define mmDCORE0_TPC0_EML_STM_STMDMASTATR 0x3C0C
28 
29 #define mmDCORE0_TPC0_EML_STM_STMDMACTLR 0x3C10
30 
31 #define mmDCORE0_TPC0_EML_STM_STMDMAIDR 0x3CFC
32 
33 #define mmDCORE0_TPC0_EML_STM_STMHEER 0x3D00
34 
35 #define mmDCORE0_TPC0_EML_STM_STMHETER 0x3D20
36 
37 #define mmDCORE0_TPC0_EML_STM_STMHEBSR 0x3D60
38 
39 #define mmDCORE0_TPC0_EML_STM_STMHEMCR 0x3D64
40 
41 #define mmDCORE0_TPC0_EML_STM_STMHEEXTMUXR 0x3D68
42 
43 #define mmDCORE0_TPC0_EML_STM_STMHEMASTR 0x3DF4
44 
45 #define mmDCORE0_TPC0_EML_STM_STMHEFEAT1R 0x3DF8
46 
47 #define mmDCORE0_TPC0_EML_STM_STMHEIDR 0x3DFC
48 
49 #define mmDCORE0_TPC0_EML_STM_STMSPER 0x3E00
50 
51 #define mmDCORE0_TPC0_EML_STM_STMSPTER 0x3E20
52 
53 #define mmDCORE0_TPC0_EML_STM_STMSPSCR 0x3E60
54 
55 #define mmDCORE0_TPC0_EML_STM_STMSPMSCR 0x3E64
56 
57 #define mmDCORE0_TPC0_EML_STM_STMSPOVERRIDER 0x3E68
58 
59 #define mmDCORE0_TPC0_EML_STM_STMSPMOVERRIDER 0x3E6C
60 
61 #define mmDCORE0_TPC0_EML_STM_STMSPTRIGCSR 0x3E70
62 
63 #define mmDCORE0_TPC0_EML_STM_STMTCSR 0x3E80
64 
65 #define mmDCORE0_TPC0_EML_STM_STMTSSTIMR 0x3E84
66 
67 #define mmDCORE0_TPC0_EML_STM_STMTSFREQR 0x3E8C
68 
69 #define mmDCORE0_TPC0_EML_STM_STMSYNCR 0x3E90
70 
71 #define mmDCORE0_TPC0_EML_STM_STMAUXCR 0x3E94
72 
73 #define mmDCORE0_TPC0_EML_STM_STMFEAT1R 0x3EA0
74 
75 #define mmDCORE0_TPC0_EML_STM_STMFEAT2R 0x3EA4
76 
77 #define mmDCORE0_TPC0_EML_STM_STMFEAT3R 0x3EA8
78 
79 #define mmDCORE0_TPC0_EML_STM_STMITTRIGGER 0x3EE8
80 
81 #define mmDCORE0_TPC0_EML_STM_STMITATBDATA0 0x3EEC
82 
83 #define mmDCORE0_TPC0_EML_STM_STMITATBCTR2 0x3EF0
84 
85 #define mmDCORE0_TPC0_EML_STM_STMITATBID 0x3EF4
86 
87 #define mmDCORE0_TPC0_EML_STM_STMITATBCTR0 0x3EF8
88 
89 #define mmDCORE0_TPC0_EML_STM_STMITCTRL 0x3F00
90 
91 #define mmDCORE0_TPC0_EML_STM_STMCLAIMSET 0x3FA0
92 
93 #define mmDCORE0_TPC0_EML_STM_STMCLAIMCLR 0x3FA4
94 
95 #define mmDCORE0_TPC0_EML_STM_STMLAR 0x3FB0
96 
97 #define mmDCORE0_TPC0_EML_STM_STMLSR 0x3FB4
98 
99 #define mmDCORE0_TPC0_EML_STM_STMAUTHSTATUS 0x3FB8
100 
101 #define mmDCORE0_TPC0_EML_STM_STMDEVARCH 0x3FBC
102 
103 #define mmDCORE0_TPC0_EML_STM_STMDEVID 0x3FC8
104 
105 #define mmDCORE0_TPC0_EML_STM_STMDEVTYPE 0x3FCC
106 
107 #define mmDCORE0_TPC0_EML_STM_STMPIDR4 0x3FD0
108 
109 #define mmDCORE0_TPC0_EML_STM_STMPIDR5 0x3FD4
110 
111 #define mmDCORE0_TPC0_EML_STM_STMPIDR6 0x3FD8
112 
113 #define mmDCORE0_TPC0_EML_STM_STMPIDR7 0x3FDC
114 
115 #define mmDCORE0_TPC0_EML_STM_STMPIDR0 0x3FE0
116 
117 #define mmDCORE0_TPC0_EML_STM_STMPIDR1 0x3FE4
118 
119 #define mmDCORE0_TPC0_EML_STM_STMPIDR2 0x3FE8
120 
121 #define mmDCORE0_TPC0_EML_STM_STMPIDR3 0x3FEC
122 
123 #define mmDCORE0_TPC0_EML_STM_STMCIDR0 0x3FF0
124 
125 #define mmDCORE0_TPC0_EML_STM_STMCIDR1 0x3FF4
126 
127 #define mmDCORE0_TPC0_EML_STM_STMCIDR2 0x3FF8
128 
129 #define mmDCORE0_TPC0_EML_STM_STMCIDR3 0x3FFC
130 
131 #endif /* ASIC_REG_DCORE0_TPC0_EML_STM_REGS_H_ */
132