1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2018 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_TPC5_CMDQ_REGS_H_
14 #define ASIC_REG_TPC5_CMDQ_REGS_H_
15 
16 /*
17  *****************************************
18  *   TPC5_CMDQ (Prototype: CMDQ)
19  *****************************************
20  */
21 
22 #define mmTPC5_CMDQ_GLBL_CFG0                                        0xF49000
23 
24 #define mmTPC5_CMDQ_GLBL_CFG1                                        0xF49004
25 
26 #define mmTPC5_CMDQ_GLBL_PROT                                        0xF49008
27 
28 #define mmTPC5_CMDQ_GLBL_ERR_CFG                                     0xF4900C
29 
30 #define mmTPC5_CMDQ_GLBL_ERR_ADDR_LO                                 0xF49010
31 
32 #define mmTPC5_CMDQ_GLBL_ERR_ADDR_HI                                 0xF49014
33 
34 #define mmTPC5_CMDQ_GLBL_ERR_WDATA                                   0xF49018
35 
36 #define mmTPC5_CMDQ_GLBL_SECURE_PROPS                                0xF4901C
37 
38 #define mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS                            0xF49020
39 
40 #define mmTPC5_CMDQ_GLBL_STS0                                        0xF49024
41 
42 #define mmTPC5_CMDQ_GLBL_STS1                                        0xF49028
43 
44 #define mmTPC5_CMDQ_CQ_CFG0                                          0xF490B0
45 
46 #define mmTPC5_CMDQ_CQ_CFG1                                          0xF490B4
47 
48 #define mmTPC5_CMDQ_CQ_ARUSER                                        0xF490B8
49 
50 #define mmTPC5_CMDQ_CQ_PTR_LO                                        0xF490C0
51 
52 #define mmTPC5_CMDQ_CQ_PTR_HI                                        0xF490C4
53 
54 #define mmTPC5_CMDQ_CQ_TSIZE                                         0xF490C8
55 
56 #define mmTPC5_CMDQ_CQ_CTL                                           0xF490CC
57 
58 #define mmTPC5_CMDQ_CQ_PTR_LO_STS                                    0xF490D4
59 
60 #define mmTPC5_CMDQ_CQ_PTR_HI_STS                                    0xF490D8
61 
62 #define mmTPC5_CMDQ_CQ_TSIZE_STS                                     0xF490DC
63 
64 #define mmTPC5_CMDQ_CQ_CTL_STS                                       0xF490E0
65 
66 #define mmTPC5_CMDQ_CQ_STS0                                          0xF490E4
67 
68 #define mmTPC5_CMDQ_CQ_STS1                                          0xF490E8
69 
70 #define mmTPC5_CMDQ_CQ_RD_RATE_LIM_EN                                0xF490F0
71 
72 #define mmTPC5_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN                         0xF490F4
73 
74 #define mmTPC5_CMDQ_CQ_RD_RATE_LIM_SAT                               0xF490F8
75 
76 #define mmTPC5_CMDQ_CQ_RD_RATE_LIM_TOUT                              0xF490FC
77 
78 #define mmTPC5_CMDQ_CQ_IFIFO_CNT                                     0xF49108
79 
80 #define mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_LO                             0xF49120
81 
82 #define mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_HI                             0xF49124
83 
84 #define mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_LO                             0xF49128
85 
86 #define mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_HI                             0xF4912C
87 
88 #define mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_LO                             0xF49130
89 
90 #define mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_HI                             0xF49134
91 
92 #define mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_LO                             0xF49138
93 
94 #define mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_HI                             0xF4913C
95 
96 #define mmTPC5_CMDQ_CP_LDMA_TSIZE_OFFSET                             0xF49140
97 
98 #define mmTPC5_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET                       0xF49144
99 
100 #define mmTPC5_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET                       0xF49148
101 
102 #define mmTPC5_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET                       0xF4914C
103 
104 #define mmTPC5_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET                       0xF49150
105 
106 #define mmTPC5_CMDQ_CP_LDMA_COMMIT_OFFSET                            0xF49154
107 
108 #define mmTPC5_CMDQ_CP_FENCE0_RDATA                                  0xF49158
109 
110 #define mmTPC5_CMDQ_CP_FENCE1_RDATA                                  0xF4915C
111 
112 #define mmTPC5_CMDQ_CP_FENCE2_RDATA                                  0xF49160
113 
114 #define mmTPC5_CMDQ_CP_FENCE3_RDATA                                  0xF49164
115 
116 #define mmTPC5_CMDQ_CP_FENCE0_CNT                                    0xF49168
117 
118 #define mmTPC5_CMDQ_CP_FENCE1_CNT                                    0xF4916C
119 
120 #define mmTPC5_CMDQ_CP_FENCE2_CNT                                    0xF49170
121 
122 #define mmTPC5_CMDQ_CP_FENCE3_CNT                                    0xF49174
123 
124 #define mmTPC5_CMDQ_CP_STS                                           0xF49178
125 
126 #define mmTPC5_CMDQ_CP_CURRENT_INST_LO                               0xF4917C
127 
128 #define mmTPC5_CMDQ_CP_CURRENT_INST_HI                               0xF49180
129 
130 #define mmTPC5_CMDQ_CP_BARRIER_CFG                                   0xF49184
131 
132 #define mmTPC5_CMDQ_CP_DBG_0                                         0xF49188
133 
134 #define mmTPC5_CMDQ_CQ_BUF_ADDR                                      0xF49308
135 
136 #define mmTPC5_CMDQ_CQ_BUF_RDATA                                     0xF4930C
137 
138 #endif /* ASIC_REG_TPC5_CMDQ_REGS_H_ */
139