1 // SPDX-License-Identifier: GPL-2.0-or-later 2 3 /* 4 * acard-ahci.c - ACard AHCI SATA support 5 * 6 * Maintained by: Tejun Heo <tj@kernel.org> 7 * Please ALWAYS copy linux-ide@vger.kernel.org 8 * on emails. 9 * 10 * Copyright 2010 Red Hat, Inc. 11 * 12 * libata documentation is available via 'make {ps|pdf}docs', 13 * as Documentation/driver-api/libata.rst 14 * 15 * AHCI hardware documentation: 16 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 17 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/pci.h> 23 #include <linux/blkdev.h> 24 #include <linux/delay.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/device.h> 28 #include <linux/dmi.h> 29 #include <linux/gfp.h> 30 #include <scsi/scsi_host.h> 31 #include <scsi/scsi_cmnd.h> 32 #include <linux/libata.h> 33 #include "ahci.h" 34 35 #define DRV_NAME "acard-ahci" 36 #define DRV_VERSION "1.0" 37 38 /* 39 Received FIS structure limited to 80h. 40 */ 41 42 #define ACARD_AHCI_RX_FIS_SZ 128 43 44 enum { 45 AHCI_PCI_BAR = 5, 46 }; 47 48 enum board_ids { 49 board_acard_ahci, 50 }; 51 52 struct acard_sg { 53 __le32 addr; 54 __le32 addr_hi; 55 __le32 reserved; 56 __le32 size; /* bit 31 (EOT) max==0x10000 (64k) */ 57 }; 58 59 static enum ata_completion_errors acard_ahci_qc_prep(struct ata_queued_cmd *qc); 60 static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc); 61 static int acard_ahci_port_start(struct ata_port *ap); 62 static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 63 64 #ifdef CONFIG_PM_SLEEP 65 static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); 66 static int acard_ahci_pci_device_resume(struct pci_dev *pdev); 67 #endif 68 69 static struct scsi_host_template acard_ahci_sht = { 70 AHCI_SHT("acard-ahci"), 71 }; 72 73 static struct ata_port_operations acard_ops = { 74 .inherits = &ahci_ops, 75 .qc_prep = acard_ahci_qc_prep, 76 .qc_fill_rtf = acard_ahci_qc_fill_rtf, 77 .port_start = acard_ahci_port_start, 78 }; 79 80 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) 81 82 static const struct ata_port_info acard_ahci_port_info[] = { 83 [board_acard_ahci] = 84 { 85 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), 86 .flags = AHCI_FLAG_COMMON, 87 .pio_mask = ATA_PIO4, 88 .udma_mask = ATA_UDMA6, 89 .port_ops = &acard_ops, 90 }, 91 }; 92 93 static const struct pci_device_id acard_ahci_pci_tbl[] = { 94 /* ACard */ 95 { PCI_VDEVICE(ARTOP, 0x000d), board_acard_ahci }, /* ATP8620 */ 96 97 { } /* terminate list */ 98 }; 99 100 static struct pci_driver acard_ahci_pci_driver = { 101 .name = DRV_NAME, 102 .id_table = acard_ahci_pci_tbl, 103 .probe = acard_ahci_init_one, 104 .remove = ata_pci_remove_one, 105 #ifdef CONFIG_PM_SLEEP 106 .suspend = acard_ahci_pci_device_suspend, 107 .resume = acard_ahci_pci_device_resume, 108 #endif 109 }; 110 111 #ifdef CONFIG_PM_SLEEP 112 static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 113 { 114 struct ata_host *host = pci_get_drvdata(pdev); 115 struct ahci_host_priv *hpriv = host->private_data; 116 void __iomem *mmio = hpriv->mmio; 117 u32 ctl; 118 119 if (mesg.event & PM_EVENT_SUSPEND && 120 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 121 dev_err(&pdev->dev, 122 "BIOS update required for suspend/resume\n"); 123 return -EIO; 124 } 125 126 if (mesg.event & PM_EVENT_SLEEP) { 127 /* AHCI spec rev1.1 section 8.3.3: 128 * Software must disable interrupts prior to requesting a 129 * transition of the HBA to D3 state. 130 */ 131 ctl = readl(mmio + HOST_CTL); 132 ctl &= ~HOST_IRQ_EN; 133 writel(ctl, mmio + HOST_CTL); 134 readl(mmio + HOST_CTL); /* flush */ 135 } 136 137 return ata_pci_device_suspend(pdev, mesg); 138 } 139 140 static int acard_ahci_pci_device_resume(struct pci_dev *pdev) 141 { 142 struct ata_host *host = pci_get_drvdata(pdev); 143 int rc; 144 145 rc = ata_pci_device_do_resume(pdev); 146 if (rc) 147 return rc; 148 149 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 150 rc = ahci_reset_controller(host); 151 if (rc) 152 return rc; 153 154 ahci_init_controller(host); 155 } 156 157 ata_host_resume(host); 158 159 return 0; 160 } 161 #endif 162 163 static void acard_ahci_pci_print_info(struct ata_host *host) 164 { 165 struct pci_dev *pdev = to_pci_dev(host->dev); 166 u16 cc; 167 const char *scc_s; 168 169 pci_read_config_word(pdev, 0x0a, &cc); 170 if (cc == PCI_CLASS_STORAGE_IDE) 171 scc_s = "IDE"; 172 else if (cc == PCI_CLASS_STORAGE_SATA) 173 scc_s = "SATA"; 174 else if (cc == PCI_CLASS_STORAGE_RAID) 175 scc_s = "RAID"; 176 else 177 scc_s = "unknown"; 178 179 ahci_print_info(host, scc_s); 180 } 181 182 static unsigned int acard_ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 183 { 184 struct scatterlist *sg; 185 struct acard_sg *acard_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 186 unsigned int si, last_si = 0; 187 188 VPRINTK("ENTER\n"); 189 190 /* 191 * Next, the S/G list. 192 */ 193 for_each_sg(qc->sg, sg, qc->n_elem, si) { 194 dma_addr_t addr = sg_dma_address(sg); 195 u32 sg_len = sg_dma_len(sg); 196 197 /* 198 * ACard note: 199 * We must set an end-of-table (EOT) bit, 200 * and the segment cannot exceed 64k (0x10000) 201 */ 202 acard_sg[si].addr = cpu_to_le32(addr & 0xffffffff); 203 acard_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); 204 acard_sg[si].size = cpu_to_le32(sg_len); 205 last_si = si; 206 } 207 208 acard_sg[last_si].size |= cpu_to_le32(1 << 31); /* set EOT */ 209 210 return si; 211 } 212 213 static enum ata_completion_errors acard_ahci_qc_prep(struct ata_queued_cmd *qc) 214 { 215 struct ata_port *ap = qc->ap; 216 struct ahci_port_priv *pp = ap->private_data; 217 int is_atapi = ata_is_atapi(qc->tf.protocol); 218 void *cmd_tbl; 219 u32 opts; 220 const u32 cmd_fis_len = 5; /* five dwords */ 221 unsigned int n_elem; 222 223 /* 224 * Fill in command table information. First, the header, 225 * a SATA Register - Host to Device command FIS. 226 */ 227 cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ; 228 229 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 230 if (is_atapi) { 231 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 232 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 233 } 234 235 n_elem = 0; 236 if (qc->flags & ATA_QCFLAG_DMAMAP) 237 n_elem = acard_ahci_fill_sg(qc, cmd_tbl); 238 239 /* 240 * Fill in command slot information. 241 * 242 * ACard note: prd table length not filled in 243 */ 244 opts = cmd_fis_len | (qc->dev->link->pmp << 12); 245 if (qc->tf.flags & ATA_TFLAG_WRITE) 246 opts |= AHCI_CMD_WRITE; 247 if (is_atapi) 248 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 249 250 ahci_fill_cmd_slot(pp, qc->hw_tag, opts); 251 252 return AC_ERR_OK; 253 } 254 255 static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc) 256 { 257 struct ahci_port_priv *pp = qc->ap->private_data; 258 u8 *rx_fis = pp->rx_fis; 259 260 if (pp->fbs_enabled) 261 rx_fis += qc->dev->link->pmp * ACARD_AHCI_RX_FIS_SZ; 262 263 /* 264 * After a successful execution of an ATA PIO data-in command, 265 * the device doesn't send D2H Reg FIS to update the TF and 266 * the host should take TF and E_Status from the preceding PIO 267 * Setup FIS. 268 */ 269 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && 270 !(qc->flags & ATA_QCFLAG_FAILED)) { 271 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); 272 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15]; 273 } else 274 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); 275 276 return true; 277 } 278 279 static int acard_ahci_port_start(struct ata_port *ap) 280 { 281 struct ahci_host_priv *hpriv = ap->host->private_data; 282 struct device *dev = ap->host->dev; 283 struct ahci_port_priv *pp; 284 void *mem; 285 dma_addr_t mem_dma; 286 size_t dma_sz, rx_fis_sz; 287 288 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 289 if (!pp) 290 return -ENOMEM; 291 292 /* check FBS capability */ 293 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { 294 void __iomem *port_mmio = ahci_port_base(ap); 295 u32 cmd = readl(port_mmio + PORT_CMD); 296 if (cmd & PORT_CMD_FBSCP) 297 pp->fbs_supported = true; 298 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { 299 dev_info(dev, "port %d can do FBS, forcing FBSCP\n", 300 ap->port_no); 301 pp->fbs_supported = true; 302 } else 303 dev_warn(dev, "port %d is not capable of FBS\n", 304 ap->port_no); 305 } 306 307 if (pp->fbs_supported) { 308 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; 309 rx_fis_sz = ACARD_AHCI_RX_FIS_SZ * 16; 310 } else { 311 dma_sz = AHCI_PORT_PRIV_DMA_SZ; 312 rx_fis_sz = ACARD_AHCI_RX_FIS_SZ; 313 } 314 315 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); 316 if (!mem) 317 return -ENOMEM; 318 319 /* 320 * First item in chunk of DMA memory: 32-slot command table, 321 * 32 bytes each in size 322 */ 323 pp->cmd_slot = mem; 324 pp->cmd_slot_dma = mem_dma; 325 326 mem += AHCI_CMD_SLOT_SZ; 327 mem_dma += AHCI_CMD_SLOT_SZ; 328 329 /* 330 * Second item: Received-FIS area 331 */ 332 pp->rx_fis = mem; 333 pp->rx_fis_dma = mem_dma; 334 335 mem += rx_fis_sz; 336 mem_dma += rx_fis_sz; 337 338 /* 339 * Third item: data area for storing a single command 340 * and its scatter-gather table 341 */ 342 pp->cmd_tbl = mem; 343 pp->cmd_tbl_dma = mem_dma; 344 345 /* 346 * Save off initial list of interrupts to be enabled. 347 * This could be changed later 348 */ 349 pp->intr_mask = DEF_PORT_IRQ; 350 351 ap->private_data = pp; 352 353 /* engage engines, captain */ 354 return ahci_port_resume(ap); 355 } 356 357 static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 358 { 359 unsigned int board_id = ent->driver_data; 360 struct ata_port_info pi = acard_ahci_port_info[board_id]; 361 const struct ata_port_info *ppi[] = { &pi, NULL }; 362 struct device *dev = &pdev->dev; 363 struct ahci_host_priv *hpriv; 364 struct ata_host *host; 365 int n_ports, i, rc; 366 367 VPRINTK("ENTER\n"); 368 369 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); 370 371 ata_print_version_once(&pdev->dev, DRV_VERSION); 372 373 /* acquire resources */ 374 rc = pcim_enable_device(pdev); 375 if (rc) 376 return rc; 377 378 /* AHCI controllers often implement SFF compatible interface. 379 * Grab all PCI BARs just in case. 380 */ 381 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); 382 if (rc == -EBUSY) 383 pcim_pin_device(pdev); 384 if (rc) 385 return rc; 386 387 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 388 if (!hpriv) 389 return -ENOMEM; 390 391 hpriv->irq = pdev->irq; 392 hpriv->flags |= (unsigned long)pi.private_data; 393 394 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) 395 pci_enable_msi(pdev); 396 397 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; 398 399 /* save initial config */ 400 ahci_save_initial_config(&pdev->dev, hpriv); 401 402 /* prepare host */ 403 if (hpriv->cap & HOST_CAP_NCQ) 404 pi.flags |= ATA_FLAG_NCQ; 405 406 if (hpriv->cap & HOST_CAP_PMP) 407 pi.flags |= ATA_FLAG_PMP; 408 409 ahci_set_em_messages(hpriv, &pi); 410 411 /* CAP.NP sometimes indicate the index of the last enabled 412 * port, at other times, that of the last possible port, so 413 * determining the maximum port number requires looking at 414 * both CAP.NP and port_map. 415 */ 416 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 417 418 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 419 if (!host) 420 return -ENOMEM; 421 host->private_data = hpriv; 422 423 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 424 host->flags |= ATA_HOST_PARALLEL_SCAN; 425 else 426 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n"); 427 428 for (i = 0; i < host->n_ports; i++) { 429 struct ata_port *ap = host->ports[i]; 430 431 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar"); 432 ata_port_pbar_desc(ap, AHCI_PCI_BAR, 433 0x100 + ap->port_no * 0x80, "port"); 434 435 /* set initial link pm policy */ 436 /* 437 ap->pm_policy = NOT_AVAILABLE; 438 */ 439 /* disabled/not-implemented port */ 440 if (!(hpriv->port_map & (1 << i))) 441 ap->ops = &ata_dummy_port_ops; 442 } 443 444 /* initialize adapter */ 445 rc = dma_set_mask_and_coherent(&pdev->dev, 446 DMA_BIT_MASK((hpriv->cap & HOST_CAP_64) ? 64 : 32)); 447 if (rc) { 448 dev_err(&pdev->dev, "DMA enable failed\n"); 449 return rc; 450 } 451 452 rc = ahci_reset_controller(host); 453 if (rc) 454 return rc; 455 456 ahci_init_controller(host); 457 acard_ahci_pci_print_info(host); 458 459 pci_set_master(pdev); 460 return ahci_host_activate(host, &acard_ahci_sht); 461 } 462 463 module_pci_driver(acard_ahci_pci_driver); 464 465 MODULE_AUTHOR("Jeff Garzik"); 466 MODULE_DESCRIPTION("ACard AHCI SATA low-level driver"); 467 MODULE_LICENSE("GPL"); 468 MODULE_DEVICE_TABLE(pci, acard_ahci_pci_tbl); 469 MODULE_VERSION(DRV_VERSION); 470