1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Libata driver for the HighPoint 371N, 372N, and 302N UDMA66 ATA controllers. 4 * 5 * This driver is heavily based upon: 6 * 7 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 8 * 9 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> 10 * Portions Copyright (C) 2001 Sun Microsystems, Inc. 11 * Portions Copyright (C) 2003 Red Hat Inc 12 * Portions Copyright (C) 2005-2010 MontaVista Software, Inc. 13 * 14 * 15 * TODO 16 * Work out best PLL policy 17 */ 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/pci.h> 21 #include <linux/blkdev.h> 22 #include <linux/delay.h> 23 #include <scsi/scsi_host.h> 24 #include <linux/libata.h> 25 26 #define DRV_NAME "pata_hpt3x2n" 27 #define DRV_VERSION "0.3.17" 28 29 enum { 30 PCI66 = (1 << 1), 31 USE_DPLL = (1 << 0) 32 }; 33 34 struct hpt_clock { 35 u8 xfer_speed; 36 u32 timing; 37 }; 38 39 struct hpt_chip { 40 const char *name; 41 struct hpt_clock *clocks[3]; 42 }; 43 44 /* key for bus clock timings 45 * bit 46 * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. 47 * cycles = value + 1 48 * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. 49 * cycles = value + 1 50 * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file 51 * register access. 52 * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file 53 * register access. 54 * 18:20 udma_cycle_time. Clock cycles for UDMA xfer. 55 * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock. 56 * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer. 57 * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file 58 * register access. 59 * 28 UDMA enable. 60 * 29 DMA enable. 61 * 30 PIO_MST enable. If set, the chip is in bus master mode during 62 * PIO xfer. 63 * 31 FIFO enable. Only for PIO. 64 */ 65 66 /* 66MHz DPLL clocks */ 67 68 static struct hpt_clock hpt3x2n_clocks[] = { 69 { XFER_UDMA_7, 0x1c869c62 }, 70 { XFER_UDMA_6, 0x1c869c62 }, 71 { XFER_UDMA_5, 0x1c8a9c62 }, 72 { XFER_UDMA_4, 0x1c8a9c62 }, 73 { XFER_UDMA_3, 0x1c8e9c62 }, 74 { XFER_UDMA_2, 0x1c929c62 }, 75 { XFER_UDMA_1, 0x1c9a9c62 }, 76 { XFER_UDMA_0, 0x1c829c62 }, 77 78 { XFER_MW_DMA_2, 0x2c829c62 }, 79 { XFER_MW_DMA_1, 0x2c829c66 }, 80 { XFER_MW_DMA_0, 0x2c829d2e }, 81 82 { XFER_PIO_4, 0x0c829c62 }, 83 { XFER_PIO_3, 0x0c829c84 }, 84 { XFER_PIO_2, 0x0c829ca6 }, 85 { XFER_PIO_1, 0x0d029d26 }, 86 { XFER_PIO_0, 0x0d029d5e }, 87 }; 88 89 /** 90 * hpt3x2n_find_mode - reset the hpt3x2n bus 91 * @ap: ATA port 92 * @speed: transfer mode 93 * 94 * Return the 32bit register programming information for this channel 95 * that matches the speed provided. For the moment the clocks table 96 * is hard coded but easy to change. This will be needed if we use 97 * different DPLLs 98 */ 99 100 static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed) 101 { 102 struct hpt_clock *clocks = hpt3x2n_clocks; 103 104 while (clocks->xfer_speed) { 105 if (clocks->xfer_speed == speed) 106 return clocks->timing; 107 clocks++; 108 } 109 BUG(); 110 return 0xffffffffU; /* silence compiler warning */ 111 } 112 113 /** 114 * hpt372n_filter - mode selection filter 115 * @adev: ATA device 116 * @mask: mode mask 117 * 118 * The Marvell bridge chips used on the HighPoint SATA cards do not seem 119 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes... 120 */ 121 static unsigned long hpt372n_filter(struct ata_device *adev, unsigned long mask) 122 { 123 if (ata_id_is_sata(adev->id)) 124 mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA); 125 126 return mask; 127 } 128 129 /** 130 * hpt3x2n_cable_detect - Detect the cable type 131 * @ap: ATA port to detect on 132 * 133 * Return the cable type attached to this port 134 */ 135 136 static int hpt3x2n_cable_detect(struct ata_port *ap) 137 { 138 u8 scr2, ata66; 139 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 140 141 pci_read_config_byte(pdev, 0x5B, &scr2); 142 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); 143 144 udelay(10); /* debounce */ 145 146 /* Cable register now active */ 147 pci_read_config_byte(pdev, 0x5A, &ata66); 148 /* Restore state */ 149 pci_write_config_byte(pdev, 0x5B, scr2); 150 151 if (ata66 & (2 >> ap->port_no)) 152 return ATA_CBL_PATA40; 153 else 154 return ATA_CBL_PATA80; 155 } 156 157 /** 158 * hpt3x2n_pre_reset - reset the hpt3x2n bus 159 * @link: ATA link to reset 160 * @deadline: deadline jiffies for the operation 161 * 162 * Perform the initial reset handling for the 3x2n series controllers. 163 * Reset the hardware and state machine, 164 */ 165 166 static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline) 167 { 168 struct ata_port *ap = link->ap; 169 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 170 static const struct pci_bits hpt3x2n_enable_bits[] = { 171 { 0x50, 1, 0x04, 0x04 }, 172 { 0x54, 1, 0x04, 0x04 } 173 }; 174 175 if (!pci_test_config_bits(pdev, &hpt3x2n_enable_bits[ap->port_no])) 176 return -ENOENT; 177 178 /* Reset the state machine */ 179 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); 180 udelay(100); 181 182 return ata_sff_prereset(link, deadline); 183 } 184 185 static void hpt3x2n_set_mode(struct ata_port *ap, struct ata_device *adev, 186 u8 mode) 187 { 188 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 189 u32 addr1, addr2; 190 u32 reg, timing, mask; 191 u8 fast; 192 193 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); 194 addr2 = 0x51 + 4 * ap->port_no; 195 196 /* Fast interrupt prediction disable, hold off interrupt disable */ 197 pci_read_config_byte(pdev, addr2, &fast); 198 fast &= ~0x07; 199 pci_write_config_byte(pdev, addr2, fast); 200 201 /* Determine timing mask and find matching mode entry */ 202 if (mode < XFER_MW_DMA_0) 203 mask = 0xcfc3ffff; 204 else if (mode < XFER_UDMA_0) 205 mask = 0x31c001ff; 206 else 207 mask = 0x303c0000; 208 209 timing = hpt3x2n_find_mode(ap, mode); 210 211 pci_read_config_dword(pdev, addr1, ®); 212 reg = (reg & ~mask) | (timing & mask); 213 pci_write_config_dword(pdev, addr1, reg); 214 } 215 216 /** 217 * hpt3x2n_set_piomode - PIO setup 218 * @ap: ATA interface 219 * @adev: device on the interface 220 * 221 * Perform PIO mode setup. 222 */ 223 224 static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev) 225 { 226 hpt3x2n_set_mode(ap, adev, adev->pio_mode); 227 } 228 229 /** 230 * hpt3x2n_set_dmamode - DMA timing setup 231 * @ap: ATA interface 232 * @adev: Device being configured 233 * 234 * Set up the channel for MWDMA or UDMA modes. 235 */ 236 237 static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev) 238 { 239 hpt3x2n_set_mode(ap, adev, adev->dma_mode); 240 } 241 242 /** 243 * hpt3x2n_bmdma_stop - DMA engine stop 244 * @qc: ATA command 245 * 246 * Clean up after the HPT3x2n and later DMA engine 247 */ 248 249 static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc) 250 { 251 struct ata_port *ap = qc->ap; 252 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 253 int mscreg = 0x50 + 4 * ap->port_no; 254 u8 bwsr_stat, msc_stat; 255 256 pci_read_config_byte(pdev, 0x6A, &bwsr_stat); 257 pci_read_config_byte(pdev, mscreg, &msc_stat); 258 if (bwsr_stat & (1 << ap->port_no)) 259 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); 260 ata_bmdma_stop(qc); 261 } 262 263 /** 264 * hpt3x2n_set_clock - clock control 265 * @ap: ATA port 266 * @source: 0x21 or 0x23 for PLL or PCI sourced clock 267 * 268 * Switch the ATA bus clock between the PLL and PCI clock sources 269 * while correctly isolating the bus and resetting internal logic 270 * 271 * We must use the DPLL for 272 * - writing 273 * - second channel UDMA7 (SATA ports) or higher 274 * - 66MHz PCI 275 * 276 * or we will underclock the device and get reduced performance. 277 */ 278 279 static void hpt3x2n_set_clock(struct ata_port *ap, int source) 280 { 281 void __iomem *bmdma = ap->ioaddr.bmdma_addr - ap->port_no * 8; 282 283 /* Tristate the bus */ 284 iowrite8(0x80, bmdma+0x73); 285 iowrite8(0x80, bmdma+0x77); 286 287 /* Switch clock and reset channels */ 288 iowrite8(source, bmdma+0x7B); 289 iowrite8(0xC0, bmdma+0x79); 290 291 /* Reset state machines, avoid enabling the disabled channels */ 292 iowrite8(ioread8(bmdma+0x70) | 0x32, bmdma+0x70); 293 iowrite8(ioread8(bmdma+0x74) | 0x32, bmdma+0x74); 294 295 /* Complete reset */ 296 iowrite8(0x00, bmdma+0x79); 297 298 /* Reconnect channels to bus */ 299 iowrite8(0x00, bmdma+0x73); 300 iowrite8(0x00, bmdma+0x77); 301 } 302 303 static int hpt3x2n_use_dpll(struct ata_port *ap, int writing) 304 { 305 long flags = (long)ap->host->private_data; 306 307 /* See if we should use the DPLL */ 308 if (writing) 309 return USE_DPLL; /* Needed for write */ 310 if (flags & PCI66) 311 return USE_DPLL; /* Needed at 66Mhz */ 312 return 0; 313 } 314 315 static int hpt3x2n_qc_defer(struct ata_queued_cmd *qc) 316 { 317 struct ata_port *ap = qc->ap; 318 struct ata_port *alt = ap->host->ports[ap->port_no ^ 1]; 319 int rc, flags = (long)ap->host->private_data; 320 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); 321 322 /* First apply the usual rules */ 323 rc = ata_std_qc_defer(qc); 324 if (rc != 0) 325 return rc; 326 327 if ((flags & USE_DPLL) != dpll && alt->qc_active) 328 return ATA_DEFER_PORT; 329 return 0; 330 } 331 332 static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc) 333 { 334 struct ata_port *ap = qc->ap; 335 int flags = (long)ap->host->private_data; 336 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); 337 338 if ((flags & USE_DPLL) != dpll) { 339 flags &= ~USE_DPLL; 340 flags |= dpll; 341 ap->host->private_data = (void *)(long)flags; 342 343 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); 344 } 345 return ata_bmdma_qc_issue(qc); 346 } 347 348 static struct scsi_host_template hpt3x2n_sht = { 349 ATA_BMDMA_SHT(DRV_NAME), 350 }; 351 352 /* 353 * Configuration for HPT302N/371N. 354 */ 355 356 static struct ata_port_operations hpt3xxn_port_ops = { 357 .inherits = &ata_bmdma_port_ops, 358 359 .bmdma_stop = hpt3x2n_bmdma_stop, 360 361 .qc_defer = hpt3x2n_qc_defer, 362 .qc_issue = hpt3x2n_qc_issue, 363 364 .cable_detect = hpt3x2n_cable_detect, 365 .set_piomode = hpt3x2n_set_piomode, 366 .set_dmamode = hpt3x2n_set_dmamode, 367 .prereset = hpt3x2n_pre_reset, 368 }; 369 370 /* 371 * Configuration for HPT372N. Same as 302N/371N but we have a mode filter. 372 */ 373 374 static struct ata_port_operations hpt372n_port_ops = { 375 .inherits = &hpt3xxn_port_ops, 376 .mode_filter = &hpt372n_filter, 377 }; 378 379 /** 380 * hpt3xn_calibrate_dpll - Calibrate the DPLL loop 381 * @dev: PCI device 382 * 383 * Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this 384 * succeeds 385 */ 386 387 static int hpt3xn_calibrate_dpll(struct pci_dev *dev) 388 { 389 u8 reg5b; 390 u32 reg5c; 391 int tries; 392 393 for (tries = 0; tries < 0x5000; tries++) { 394 udelay(50); 395 pci_read_config_byte(dev, 0x5b, ®5b); 396 if (reg5b & 0x80) { 397 /* See if it stays set */ 398 for (tries = 0; tries < 0x1000; tries++) { 399 pci_read_config_byte(dev, 0x5b, ®5b); 400 /* Failed ? */ 401 if ((reg5b & 0x80) == 0) 402 return 0; 403 } 404 /* Turn off tuning, we have the DPLL set */ 405 pci_read_config_dword(dev, 0x5c, ®5c); 406 pci_write_config_dword(dev, 0x5c, reg5c & ~0x100); 407 return 1; 408 } 409 } 410 /* Never went stable */ 411 return 0; 412 } 413 414 static int hpt3x2n_pci_clock(struct pci_dev *pdev) 415 { 416 unsigned long freq; 417 u32 fcnt; 418 unsigned long iobase = pci_resource_start(pdev, 4); 419 420 fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */ 421 if ((fcnt >> 12) != 0xABCDE) { 422 int i; 423 u16 sr; 424 u32 total = 0; 425 426 dev_warn(&pdev->dev, "BIOS clock data not set\n"); 427 428 /* This is the process the HPT371 BIOS is reported to use */ 429 for (i = 0; i < 128; i++) { 430 pci_read_config_word(pdev, 0x78, &sr); 431 total += sr & 0x1FF; 432 udelay(15); 433 } 434 fcnt = total / 128; 435 } 436 fcnt &= 0x1FF; 437 438 freq = (fcnt * 77) / 192; 439 440 /* Clamp to bands */ 441 if (freq < 40) 442 return 33; 443 if (freq < 45) 444 return 40; 445 if (freq < 55) 446 return 50; 447 return 66; 448 } 449 450 /** 451 * hpt3x2n_init_one - Initialise an HPT37X/302 452 * @dev: PCI device 453 * @id: Entry in match table 454 * 455 * Initialise an HPT3x2n device. There are some interesting complications 456 * here. Firstly the chip may report 366 and be one of several variants. 457 * Secondly all the timings depend on the clock for the chip which we must 458 * detect and look up 459 * 460 * This is the known chip mappings. It may be missing a couple of later 461 * releases. 462 * 463 * Chip version PCI Rev Notes 464 * HPT372 4 (HPT366) 5 Other driver 465 * HPT372N 4 (HPT366) 6 UDMA133 466 * HPT372 5 (HPT372) 1 Other driver 467 * HPT372N 5 (HPT372) 2 UDMA133 468 * HPT302 6 (HPT302) * Other driver 469 * HPT302N 6 (HPT302) > 1 UDMA133 470 * HPT371 7 (HPT371) * Other driver 471 * HPT371N 7 (HPT371) > 1 UDMA133 472 * HPT374 8 (HPT374) * Other driver 473 * HPT372N 9 (HPT372N) * UDMA133 474 * 475 * (1) UDMA133 support depends on the bus clock 476 */ 477 478 static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id) 479 { 480 /* HPT372N - UDMA133 */ 481 static const struct ata_port_info info_hpt372n = { 482 .flags = ATA_FLAG_SLAVE_POSS, 483 .pio_mask = ATA_PIO4, 484 .mwdma_mask = ATA_MWDMA2, 485 .udma_mask = ATA_UDMA6, 486 .port_ops = &hpt372n_port_ops 487 }; 488 /* HPT302N and HPT371N - UDMA133 */ 489 static const struct ata_port_info info_hpt3xxn = { 490 .flags = ATA_FLAG_SLAVE_POSS, 491 .pio_mask = ATA_PIO4, 492 .mwdma_mask = ATA_MWDMA2, 493 .udma_mask = ATA_UDMA6, 494 .port_ops = &hpt3xxn_port_ops 495 }; 496 const struct ata_port_info *ppi[] = { &info_hpt3xxn, NULL }; 497 u8 rev = dev->revision; 498 u8 irqmask; 499 unsigned int pci_mhz; 500 unsigned int f_low, f_high; 501 int adjust; 502 unsigned long iobase = pci_resource_start(dev, 4); 503 void *hpriv = (void *)USE_DPLL; 504 int rc; 505 506 rc = pcim_enable_device(dev); 507 if (rc) 508 return rc; 509 510 switch (dev->device) { 511 case PCI_DEVICE_ID_TTI_HPT366: 512 /* 372N if rev >= 6 */ 513 if (rev < 6) 514 return -ENODEV; 515 goto hpt372n; 516 case PCI_DEVICE_ID_TTI_HPT371: 517 /* 371N if rev >= 2 */ 518 if (rev < 2) 519 return -ENODEV; 520 break; 521 case PCI_DEVICE_ID_TTI_HPT372: 522 /* 372N if rev >= 2 */ 523 if (rev < 2) 524 return -ENODEV; 525 goto hpt372n; 526 case PCI_DEVICE_ID_TTI_HPT302: 527 /* 302N if rev >= 2 */ 528 if (rev < 2) 529 return -ENODEV; 530 break; 531 case PCI_DEVICE_ID_TTI_HPT372N: 532 hpt372n: 533 ppi[0] = &info_hpt372n; 534 break; 535 default: 536 dev_err(&dev->dev,"PCI table is bogus, please report (%d)\n", 537 dev->device); 538 return -ENODEV; 539 } 540 541 /* Ok so this is a chip we support */ 542 543 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); 544 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); 545 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); 546 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); 547 548 pci_read_config_byte(dev, 0x5A, &irqmask); 549 irqmask &= ~0x10; 550 pci_write_config_byte(dev, 0x5a, irqmask); 551 552 /* 553 * HPT371 chips physically have only one channel, the secondary one, 554 * but the primary channel registers do exist! Go figure... 555 * So, we manually disable the non-existing channel here 556 * (if the BIOS hasn't done this already). 557 */ 558 if (dev->device == PCI_DEVICE_ID_TTI_HPT371) { 559 u8 mcr1; 560 pci_read_config_byte(dev, 0x50, &mcr1); 561 mcr1 &= ~0x04; 562 pci_write_config_byte(dev, 0x50, mcr1); 563 } 564 565 /* 566 * Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or 567 * 50 for UDMA100. Right now we always use 66 568 */ 569 570 pci_mhz = hpt3x2n_pci_clock(dev); 571 572 f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */ 573 f_high = f_low + 2; /* Tolerance */ 574 575 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100); 576 /* PLL clock */ 577 pci_write_config_byte(dev, 0x5B, 0x21); 578 579 /* Unlike the 37x we don't try jiggling the frequency */ 580 for (adjust = 0; adjust < 8; adjust++) { 581 if (hpt3xn_calibrate_dpll(dev)) 582 break; 583 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low); 584 } 585 if (adjust == 8) { 586 dev_err(&dev->dev, "DPLL did not stabilize!\n"); 587 return -ENODEV; 588 } 589 590 dev_info(&dev->dev, "bus clock %dMHz, using 66MHz DPLL\n", pci_mhz); 591 592 /* 593 * Set our private data up. We only need a few flags 594 * so we use it directly. 595 */ 596 if (pci_mhz > 60) 597 hpriv = (void *)(PCI66 | USE_DPLL); 598 599 /* 600 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in 601 * the MISC. register to stretch the UltraDMA Tss timing. 602 * NOTE: This register is only writeable via I/O space. 603 */ 604 if (dev->device == PCI_DEVICE_ID_TTI_HPT371) 605 outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c); 606 607 /* Now kick off ATA set up */ 608 return ata_pci_bmdma_init_one(dev, ppi, &hpt3x2n_sht, hpriv, 0); 609 } 610 611 static const struct pci_device_id hpt3x2n[] = { 612 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, 613 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, 614 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, 615 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, 616 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), }, 617 618 { }, 619 }; 620 621 static struct pci_driver hpt3x2n_pci_driver = { 622 .name = DRV_NAME, 623 .id_table = hpt3x2n, 624 .probe = hpt3x2n_init_one, 625 .remove = ata_pci_remove_one 626 }; 627 628 module_pci_driver(hpt3x2n_pci_driver); 629 630 MODULE_AUTHOR("Alan Cox"); 631 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3xxN"); 632 MODULE_LICENSE("GPL"); 633 MODULE_DEVICE_TABLE(pci, hpt3x2n); 634 MODULE_VERSION(DRV_VERSION); 635