1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ti-sysc.c - Texas Instruments sysc interconnect target driver 4 */ 5 6 #include <linux/io.h> 7 #include <linux/clk.h> 8 #include <linux/clkdev.h> 9 #include <linux/delay.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_domain.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/reset.h> 15 #include <linux/of_address.h> 16 #include <linux/of_platform.h> 17 #include <linux/slab.h> 18 #include <linux/iopoll.h> 19 20 #include <linux/platform_data/ti-sysc.h> 21 22 #include <dt-bindings/bus/ti-sysc.h> 23 24 #define MAX_MODULE_SOFTRESET_WAIT 10000 25 26 static const char * const reg_names[] = { "rev", "sysc", "syss", }; 27 28 enum sysc_clocks { 29 SYSC_FCK, 30 SYSC_ICK, 31 SYSC_OPTFCK0, 32 SYSC_OPTFCK1, 33 SYSC_OPTFCK2, 34 SYSC_OPTFCK3, 35 SYSC_OPTFCK4, 36 SYSC_OPTFCK5, 37 SYSC_OPTFCK6, 38 SYSC_OPTFCK7, 39 SYSC_MAX_CLOCKS, 40 }; 41 42 static const char * const clock_names[SYSC_MAX_CLOCKS] = { 43 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4", 44 "opt5", "opt6", "opt7", 45 }; 46 47 #define SYSC_IDLEMODE_MASK 3 48 #define SYSC_CLOCKACTIVITY_MASK 3 49 50 /** 51 * struct sysc - TI sysc interconnect target module registers and capabilities 52 * @dev: struct device pointer 53 * @module_pa: physical address of the interconnect target module 54 * @module_size: size of the interconnect target module 55 * @module_va: virtual address of the interconnect target module 56 * @offsets: register offsets from module base 57 * @mdata: ti-sysc to hwmod translation data for a module 58 * @clocks: clocks used by the interconnect target module 59 * @clock_roles: clock role names for the found clocks 60 * @nr_clocks: number of clocks used by the interconnect target module 61 * @rsts: resets used by the interconnect target module 62 * @legacy_mode: configured for legacy mode if set 63 * @cap: interconnect target module capabilities 64 * @cfg: interconnect target module configuration 65 * @cookie: data used by legacy platform callbacks 66 * @name: name if available 67 * @revision: interconnect target module revision 68 * @enabled: sysc runtime enabled status 69 * @needs_resume: runtime resume needed on resume from suspend 70 * @child_needs_resume: runtime resume needed for child on resume from suspend 71 * @disable_on_idle: status flag used for disabling modules with resets 72 * @idle_work: work structure used to perform delayed idle on a module 73 * @clk_enable_quirk: module specific clock enable quirk 74 * @clk_disable_quirk: module specific clock disable quirk 75 * @reset_done_quirk: module specific reset done quirk 76 * @module_enable_quirk: module specific enable quirk 77 * @module_disable_quirk: module specific disable quirk 78 */ 79 struct sysc { 80 struct device *dev; 81 u64 module_pa; 82 u32 module_size; 83 void __iomem *module_va; 84 int offsets[SYSC_MAX_REGS]; 85 struct ti_sysc_module_data *mdata; 86 struct clk **clocks; 87 const char **clock_roles; 88 int nr_clocks; 89 struct reset_control *rsts; 90 const char *legacy_mode; 91 const struct sysc_capabilities *cap; 92 struct sysc_config cfg; 93 struct ti_sysc_cookie cookie; 94 const char *name; 95 u32 revision; 96 unsigned int enabled:1; 97 unsigned int needs_resume:1; 98 unsigned int child_needs_resume:1; 99 struct delayed_work idle_work; 100 void (*clk_enable_quirk)(struct sysc *sysc); 101 void (*clk_disable_quirk)(struct sysc *sysc); 102 void (*reset_done_quirk)(struct sysc *sysc); 103 void (*module_enable_quirk)(struct sysc *sysc); 104 void (*module_disable_quirk)(struct sysc *sysc); 105 }; 106 107 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, 108 bool is_child); 109 110 static void sysc_write(struct sysc *ddata, int offset, u32 value) 111 { 112 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { 113 writew_relaxed(value & 0xffff, ddata->module_va + offset); 114 115 /* Only i2c revision has LO and HI register with stride of 4 */ 116 if (ddata->offsets[SYSC_REVISION] >= 0 && 117 offset == ddata->offsets[SYSC_REVISION]) { 118 u16 hi = value >> 16; 119 120 writew_relaxed(hi, ddata->module_va + offset + 4); 121 } 122 123 return; 124 } 125 126 writel_relaxed(value, ddata->module_va + offset); 127 } 128 129 static u32 sysc_read(struct sysc *ddata, int offset) 130 { 131 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { 132 u32 val; 133 134 val = readw_relaxed(ddata->module_va + offset); 135 136 /* Only i2c revision has LO and HI register with stride of 4 */ 137 if (ddata->offsets[SYSC_REVISION] >= 0 && 138 offset == ddata->offsets[SYSC_REVISION]) { 139 u16 tmp = readw_relaxed(ddata->module_va + offset + 4); 140 141 val |= tmp << 16; 142 } 143 144 return val; 145 } 146 147 return readl_relaxed(ddata->module_va + offset); 148 } 149 150 static bool sysc_opt_clks_needed(struct sysc *ddata) 151 { 152 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED); 153 } 154 155 static u32 sysc_read_revision(struct sysc *ddata) 156 { 157 int offset = ddata->offsets[SYSC_REVISION]; 158 159 if (offset < 0) 160 return 0; 161 162 return sysc_read(ddata, offset); 163 } 164 165 static u32 sysc_read_sysconfig(struct sysc *ddata) 166 { 167 int offset = ddata->offsets[SYSC_SYSCONFIG]; 168 169 if (offset < 0) 170 return 0; 171 172 return sysc_read(ddata, offset); 173 } 174 175 static u32 sysc_read_sysstatus(struct sysc *ddata) 176 { 177 int offset = ddata->offsets[SYSC_SYSSTATUS]; 178 179 if (offset < 0) 180 return 0; 181 182 return sysc_read(ddata, offset); 183 } 184 185 static int sysc_add_named_clock_from_child(struct sysc *ddata, 186 const char *name, 187 const char *optfck_name) 188 { 189 struct device_node *np = ddata->dev->of_node; 190 struct device_node *child; 191 struct clk_lookup *cl; 192 struct clk *clock; 193 const char *n; 194 195 if (name) 196 n = name; 197 else 198 n = optfck_name; 199 200 /* Does the clock alias already exist? */ 201 clock = of_clk_get_by_name(np, n); 202 if (!IS_ERR(clock)) { 203 clk_put(clock); 204 205 return 0; 206 } 207 208 child = of_get_next_available_child(np, NULL); 209 if (!child) 210 return -ENODEV; 211 212 clock = devm_get_clk_from_child(ddata->dev, child, name); 213 if (IS_ERR(clock)) 214 return PTR_ERR(clock); 215 216 /* 217 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID 218 * limit for clk_get(). If cl ever needs to be freed, it should be done 219 * with clkdev_drop(). 220 */ 221 cl = kcalloc(1, sizeof(*cl), GFP_KERNEL); 222 if (!cl) 223 return -ENOMEM; 224 225 cl->con_id = n; 226 cl->dev_id = dev_name(ddata->dev); 227 cl->clk = clock; 228 clkdev_add(cl); 229 230 clk_put(clock); 231 232 return 0; 233 } 234 235 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name) 236 { 237 const char *optfck_name; 238 int error, index; 239 240 if (ddata->nr_clocks < SYSC_OPTFCK0) 241 index = SYSC_OPTFCK0; 242 else 243 index = ddata->nr_clocks; 244 245 if (name) 246 optfck_name = name; 247 else 248 optfck_name = clock_names[index]; 249 250 error = sysc_add_named_clock_from_child(ddata, name, optfck_name); 251 if (error) 252 return error; 253 254 ddata->clock_roles[index] = optfck_name; 255 ddata->nr_clocks++; 256 257 return 0; 258 } 259 260 static int sysc_get_one_clock(struct sysc *ddata, const char *name) 261 { 262 int error, i, index = -ENODEV; 263 264 if (!strncmp(clock_names[SYSC_FCK], name, 3)) 265 index = SYSC_FCK; 266 else if (!strncmp(clock_names[SYSC_ICK], name, 3)) 267 index = SYSC_ICK; 268 269 if (index < 0) { 270 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 271 if (!ddata->clocks[i]) { 272 index = i; 273 break; 274 } 275 } 276 } 277 278 if (index < 0) { 279 dev_err(ddata->dev, "clock %s not added\n", name); 280 return index; 281 } 282 283 ddata->clocks[index] = devm_clk_get(ddata->dev, name); 284 if (IS_ERR(ddata->clocks[index])) { 285 dev_err(ddata->dev, "clock get error for %s: %li\n", 286 name, PTR_ERR(ddata->clocks[index])); 287 288 return PTR_ERR(ddata->clocks[index]); 289 } 290 291 error = clk_prepare(ddata->clocks[index]); 292 if (error) { 293 dev_err(ddata->dev, "clock prepare error for %s: %i\n", 294 name, error); 295 296 return error; 297 } 298 299 return 0; 300 } 301 302 static int sysc_get_clocks(struct sysc *ddata) 303 { 304 struct device_node *np = ddata->dev->of_node; 305 struct property *prop; 306 const char *name; 307 int nr_fck = 0, nr_ick = 0, i, error = 0; 308 309 ddata->clock_roles = devm_kcalloc(ddata->dev, 310 SYSC_MAX_CLOCKS, 311 sizeof(*ddata->clock_roles), 312 GFP_KERNEL); 313 if (!ddata->clock_roles) 314 return -ENOMEM; 315 316 of_property_for_each_string(np, "clock-names", prop, name) { 317 if (!strncmp(clock_names[SYSC_FCK], name, 3)) 318 nr_fck++; 319 if (!strncmp(clock_names[SYSC_ICK], name, 3)) 320 nr_ick++; 321 ddata->clock_roles[ddata->nr_clocks] = name; 322 ddata->nr_clocks++; 323 } 324 325 if (ddata->nr_clocks < 1) 326 return 0; 327 328 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) { 329 error = sysc_init_ext_opt_clock(ddata, NULL); 330 if (error) 331 return error; 332 } 333 334 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) { 335 dev_err(ddata->dev, "too many clocks for %pOF\n", np); 336 337 return -EINVAL; 338 } 339 340 if (nr_fck > 1 || nr_ick > 1) { 341 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np); 342 343 return -EINVAL; 344 } 345 346 ddata->clocks = devm_kcalloc(ddata->dev, 347 ddata->nr_clocks, sizeof(*ddata->clocks), 348 GFP_KERNEL); 349 if (!ddata->clocks) 350 return -ENOMEM; 351 352 for (i = 0; i < SYSC_MAX_CLOCKS; i++) { 353 const char *name = ddata->clock_roles[i]; 354 355 if (!name) 356 continue; 357 358 error = sysc_get_one_clock(ddata, name); 359 if (error) 360 return error; 361 } 362 363 return 0; 364 } 365 366 static int sysc_enable_main_clocks(struct sysc *ddata) 367 { 368 struct clk *clock; 369 int i, error; 370 371 if (!ddata->clocks) 372 return 0; 373 374 for (i = 0; i < SYSC_OPTFCK0; i++) { 375 clock = ddata->clocks[i]; 376 377 /* Main clocks may not have ick */ 378 if (IS_ERR_OR_NULL(clock)) 379 continue; 380 381 error = clk_enable(clock); 382 if (error) 383 goto err_disable; 384 } 385 386 return 0; 387 388 err_disable: 389 for (i--; i >= 0; i--) { 390 clock = ddata->clocks[i]; 391 392 /* Main clocks may not have ick */ 393 if (IS_ERR_OR_NULL(clock)) 394 continue; 395 396 clk_disable(clock); 397 } 398 399 return error; 400 } 401 402 static void sysc_disable_main_clocks(struct sysc *ddata) 403 { 404 struct clk *clock; 405 int i; 406 407 if (!ddata->clocks) 408 return; 409 410 for (i = 0; i < SYSC_OPTFCK0; i++) { 411 clock = ddata->clocks[i]; 412 if (IS_ERR_OR_NULL(clock)) 413 continue; 414 415 clk_disable(clock); 416 } 417 } 418 419 static int sysc_enable_opt_clocks(struct sysc *ddata) 420 { 421 struct clk *clock; 422 int i, error; 423 424 if (!ddata->clocks) 425 return 0; 426 427 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 428 clock = ddata->clocks[i]; 429 430 /* Assume no holes for opt clocks */ 431 if (IS_ERR_OR_NULL(clock)) 432 return 0; 433 434 error = clk_enable(clock); 435 if (error) 436 goto err_disable; 437 } 438 439 return 0; 440 441 err_disable: 442 for (i--; i >= 0; i--) { 443 clock = ddata->clocks[i]; 444 if (IS_ERR_OR_NULL(clock)) 445 continue; 446 447 clk_disable(clock); 448 } 449 450 return error; 451 } 452 453 static void sysc_disable_opt_clocks(struct sysc *ddata) 454 { 455 struct clk *clock; 456 int i; 457 458 if (!ddata->clocks) 459 return; 460 461 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 462 clock = ddata->clocks[i]; 463 464 /* Assume no holes for opt clocks */ 465 if (IS_ERR_OR_NULL(clock)) 466 return; 467 468 clk_disable(clock); 469 } 470 } 471 472 static void sysc_clkdm_deny_idle(struct sysc *ddata) 473 { 474 struct ti_sysc_platform_data *pdata; 475 476 if (ddata->legacy_mode) 477 return; 478 479 pdata = dev_get_platdata(ddata->dev); 480 if (pdata && pdata->clkdm_deny_idle) 481 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie); 482 } 483 484 static void sysc_clkdm_allow_idle(struct sysc *ddata) 485 { 486 struct ti_sysc_platform_data *pdata; 487 488 if (ddata->legacy_mode) 489 return; 490 491 pdata = dev_get_platdata(ddata->dev); 492 if (pdata && pdata->clkdm_allow_idle) 493 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie); 494 } 495 496 /** 497 * sysc_init_resets - init rstctrl reset line if configured 498 * @ddata: device driver data 499 * 500 * See sysc_rstctrl_reset_deassert(). 501 */ 502 static int sysc_init_resets(struct sysc *ddata) 503 { 504 ddata->rsts = 505 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl"); 506 if (IS_ERR(ddata->rsts)) 507 return PTR_ERR(ddata->rsts); 508 509 return 0; 510 } 511 512 /** 513 * sysc_parse_and_check_child_range - parses module IO region from ranges 514 * @ddata: device driver data 515 * 516 * In general we only need rev, syss, and sysc registers and not the whole 517 * module range. But we do want the offsets for these registers from the 518 * module base. This allows us to check them against the legacy hwmod 519 * platform data. Let's also check the ranges are configured properly. 520 */ 521 static int sysc_parse_and_check_child_range(struct sysc *ddata) 522 { 523 struct device_node *np = ddata->dev->of_node; 524 const __be32 *ranges; 525 u32 nr_addr, nr_size; 526 int len, error; 527 528 ranges = of_get_property(np, "ranges", &len); 529 if (!ranges) { 530 dev_err(ddata->dev, "missing ranges for %pOF\n", np); 531 532 return -ENOENT; 533 } 534 535 len /= sizeof(*ranges); 536 537 if (len < 3) { 538 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np); 539 540 return -EINVAL; 541 } 542 543 error = of_property_read_u32(np, "#address-cells", &nr_addr); 544 if (error) 545 return -ENOENT; 546 547 error = of_property_read_u32(np, "#size-cells", &nr_size); 548 if (error) 549 return -ENOENT; 550 551 if (nr_addr != 1 || nr_size != 1) { 552 dev_err(ddata->dev, "invalid ranges for %pOF\n", np); 553 554 return -EINVAL; 555 } 556 557 ranges++; 558 ddata->module_pa = of_translate_address(np, ranges++); 559 ddata->module_size = be32_to_cpup(ranges); 560 561 return 0; 562 } 563 564 static struct device_node *stdout_path; 565 566 static void sysc_init_stdout_path(struct sysc *ddata) 567 { 568 struct device_node *np = NULL; 569 const char *uart; 570 571 if (IS_ERR(stdout_path)) 572 return; 573 574 if (stdout_path) 575 return; 576 577 np = of_find_node_by_path("/chosen"); 578 if (!np) 579 goto err; 580 581 uart = of_get_property(np, "stdout-path", NULL); 582 if (!uart) 583 goto err; 584 585 np = of_find_node_by_path(uart); 586 if (!np) 587 goto err; 588 589 stdout_path = np; 590 591 return; 592 593 err: 594 stdout_path = ERR_PTR(-ENODEV); 595 } 596 597 static void sysc_check_quirk_stdout(struct sysc *ddata, 598 struct device_node *np) 599 { 600 sysc_init_stdout_path(ddata); 601 if (np != stdout_path) 602 return; 603 604 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT | 605 SYSC_QUIRK_NO_RESET_ON_INIT; 606 } 607 608 /** 609 * sysc_check_one_child - check child configuration 610 * @ddata: device driver data 611 * @np: child device node 612 * 613 * Let's avoid messy situations where we have new interconnect target 614 * node but children have "ti,hwmods". These belong to the interconnect 615 * target node and are managed by this driver. 616 */ 617 static void sysc_check_one_child(struct sysc *ddata, 618 struct device_node *np) 619 { 620 const char *name; 621 622 name = of_get_property(np, "ti,hwmods", NULL); 623 if (name) 624 dev_warn(ddata->dev, "really a child ti,hwmods property?"); 625 626 sysc_check_quirk_stdout(ddata, np); 627 sysc_parse_dts_quirks(ddata, np, true); 628 } 629 630 static void sysc_check_children(struct sysc *ddata) 631 { 632 struct device_node *child; 633 634 for_each_child_of_node(ddata->dev->of_node, child) 635 sysc_check_one_child(ddata, child); 636 } 637 638 /* 639 * So far only I2C uses 16-bit read access with clockactivity with revision 640 * in two registers with stride of 4. We can detect this based on the rev 641 * register size to configure things far enough to be able to properly read 642 * the revision register. 643 */ 644 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res) 645 { 646 if (resource_size(res) == 8) 647 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT; 648 } 649 650 /** 651 * sysc_parse_one - parses the interconnect target module registers 652 * @ddata: device driver data 653 * @reg: register to parse 654 */ 655 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg) 656 { 657 struct resource *res; 658 const char *name; 659 660 switch (reg) { 661 case SYSC_REVISION: 662 case SYSC_SYSCONFIG: 663 case SYSC_SYSSTATUS: 664 name = reg_names[reg]; 665 break; 666 default: 667 return -EINVAL; 668 } 669 670 res = platform_get_resource_byname(to_platform_device(ddata->dev), 671 IORESOURCE_MEM, name); 672 if (!res) { 673 ddata->offsets[reg] = -ENODEV; 674 675 return 0; 676 } 677 678 ddata->offsets[reg] = res->start - ddata->module_pa; 679 if (reg == SYSC_REVISION) 680 sysc_check_quirk_16bit(ddata, res); 681 682 return 0; 683 } 684 685 static int sysc_parse_registers(struct sysc *ddata) 686 { 687 int i, error; 688 689 for (i = 0; i < SYSC_MAX_REGS; i++) { 690 error = sysc_parse_one(ddata, i); 691 if (error) 692 return error; 693 } 694 695 return 0; 696 } 697 698 /** 699 * sysc_check_registers - check for misconfigured register overlaps 700 * @ddata: device driver data 701 */ 702 static int sysc_check_registers(struct sysc *ddata) 703 { 704 int i, j, nr_regs = 0, nr_matches = 0; 705 706 for (i = 0; i < SYSC_MAX_REGS; i++) { 707 if (ddata->offsets[i] < 0) 708 continue; 709 710 if (ddata->offsets[i] > (ddata->module_size - 4)) { 711 dev_err(ddata->dev, "register outside module range"); 712 713 return -EINVAL; 714 } 715 716 for (j = 0; j < SYSC_MAX_REGS; j++) { 717 if (ddata->offsets[j] < 0) 718 continue; 719 720 if (ddata->offsets[i] == ddata->offsets[j]) 721 nr_matches++; 722 } 723 nr_regs++; 724 } 725 726 if (nr_matches > nr_regs) { 727 dev_err(ddata->dev, "overlapping registers: (%i/%i)", 728 nr_regs, nr_matches); 729 730 return -EINVAL; 731 } 732 733 return 0; 734 } 735 736 /** 737 * syc_ioremap - ioremap register space for the interconnect target module 738 * @ddata: device driver data 739 * 740 * Note that the interconnect target module registers can be anywhere 741 * within the interconnect target module range. For example, SGX has 742 * them at offset 0x1fc00 in the 32MB module address space. And cpsw 743 * has them at offset 0x1200 in the CPSW_WR child. Usually the 744 * the interconnect target module registers are at the beginning of 745 * the module range though. 746 */ 747 static int sysc_ioremap(struct sysc *ddata) 748 { 749 int size; 750 751 if (ddata->offsets[SYSC_REVISION] < 0 && 752 ddata->offsets[SYSC_SYSCONFIG] < 0 && 753 ddata->offsets[SYSC_SYSSTATUS] < 0) { 754 size = ddata->module_size; 755 } else { 756 size = max3(ddata->offsets[SYSC_REVISION], 757 ddata->offsets[SYSC_SYSCONFIG], 758 ddata->offsets[SYSC_SYSSTATUS]); 759 760 if (size < SZ_1K) 761 size = SZ_1K; 762 763 if ((size + sizeof(u32)) > ddata->module_size) 764 size = ddata->module_size; 765 } 766 767 ddata->module_va = devm_ioremap(ddata->dev, 768 ddata->module_pa, 769 size + sizeof(u32)); 770 if (!ddata->module_va) 771 return -EIO; 772 773 return 0; 774 } 775 776 /** 777 * sysc_map_and_check_registers - ioremap and check device registers 778 * @ddata: device driver data 779 */ 780 static int sysc_map_and_check_registers(struct sysc *ddata) 781 { 782 int error; 783 784 error = sysc_parse_and_check_child_range(ddata); 785 if (error) 786 return error; 787 788 sysc_check_children(ddata); 789 790 error = sysc_parse_registers(ddata); 791 if (error) 792 return error; 793 794 error = sysc_ioremap(ddata); 795 if (error) 796 return error; 797 798 error = sysc_check_registers(ddata); 799 if (error) 800 return error; 801 802 return 0; 803 } 804 805 /** 806 * sysc_show_rev - read and show interconnect target module revision 807 * @bufp: buffer to print the information to 808 * @ddata: device driver data 809 */ 810 static int sysc_show_rev(char *bufp, struct sysc *ddata) 811 { 812 int len; 813 814 if (ddata->offsets[SYSC_REVISION] < 0) 815 return sprintf(bufp, ":NA"); 816 817 len = sprintf(bufp, ":%08x", ddata->revision); 818 819 return len; 820 } 821 822 static int sysc_show_reg(struct sysc *ddata, 823 char *bufp, enum sysc_registers reg) 824 { 825 if (ddata->offsets[reg] < 0) 826 return sprintf(bufp, ":NA"); 827 828 return sprintf(bufp, ":%x", ddata->offsets[reg]); 829 } 830 831 static int sysc_show_name(char *bufp, struct sysc *ddata) 832 { 833 if (!ddata->name) 834 return 0; 835 836 return sprintf(bufp, ":%s", ddata->name); 837 } 838 839 /** 840 * sysc_show_registers - show information about interconnect target module 841 * @ddata: device driver data 842 */ 843 static void sysc_show_registers(struct sysc *ddata) 844 { 845 char buf[128]; 846 char *bufp = buf; 847 int i; 848 849 for (i = 0; i < SYSC_MAX_REGS; i++) 850 bufp += sysc_show_reg(ddata, bufp, i); 851 852 bufp += sysc_show_rev(bufp, ddata); 853 bufp += sysc_show_name(bufp, ddata); 854 855 dev_dbg(ddata->dev, "%llx:%x%s\n", 856 ddata->module_pa, ddata->module_size, 857 buf); 858 } 859 860 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1) 861 #define SYSC_CLOCACT_ICK 2 862 863 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ 864 static int sysc_enable_module(struct device *dev) 865 { 866 struct sysc *ddata; 867 const struct sysc_regbits *regbits; 868 u32 reg, idlemodes, best_mode; 869 870 ddata = dev_get_drvdata(dev); 871 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) 872 return 0; 873 874 regbits = ddata->cap->regbits; 875 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 876 877 /* Set CLOCKACTIVITY, we only use it for ick */ 878 if (regbits->clkact_shift >= 0 && 879 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT || 880 ddata->cfg.sysc_val & BIT(regbits->clkact_shift))) 881 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift; 882 883 /* Set SIDLE mode */ 884 idlemodes = ddata->cfg.sidlemodes; 885 if (!idlemodes || regbits->sidle_shift < 0) 886 goto set_midle; 887 888 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE | 889 SYSC_QUIRK_SWSUP_SIDLE_ACT)) { 890 best_mode = SYSC_IDLE_NO; 891 } else { 892 best_mode = fls(ddata->cfg.sidlemodes) - 1; 893 if (best_mode > SYSC_IDLE_MASK) { 894 dev_err(dev, "%s: invalid sidlemode\n", __func__); 895 return -EINVAL; 896 } 897 898 /* Set WAKEUP */ 899 if (regbits->enwkup_shift >= 0 && 900 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift)) 901 reg |= BIT(regbits->enwkup_shift); 902 } 903 904 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); 905 reg |= best_mode << regbits->sidle_shift; 906 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 907 908 set_midle: 909 /* Set MIDLE mode */ 910 idlemodes = ddata->cfg.midlemodes; 911 if (!idlemodes || regbits->midle_shift < 0) 912 goto set_autoidle; 913 914 best_mode = fls(ddata->cfg.midlemodes) - 1; 915 if (best_mode > SYSC_IDLE_MASK) { 916 dev_err(dev, "%s: invalid midlemode\n", __func__); 917 return -EINVAL; 918 } 919 920 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY) 921 best_mode = SYSC_IDLE_NO; 922 923 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); 924 reg |= best_mode << regbits->midle_shift; 925 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 926 927 set_autoidle: 928 /* Autoidle bit must enabled separately if available */ 929 if (regbits->autoidle_shift >= 0 && 930 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) { 931 reg |= 1 << regbits->autoidle_shift; 932 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 933 } 934 935 if (ddata->module_enable_quirk) 936 ddata->module_enable_quirk(ddata); 937 938 return 0; 939 } 940 941 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode) 942 { 943 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP)) 944 *best_mode = SYSC_IDLE_SMART_WKUP; 945 else if (idlemodes & BIT(SYSC_IDLE_SMART)) 946 *best_mode = SYSC_IDLE_SMART; 947 else if (idlemodes & BIT(SYSC_IDLE_FORCE)) 948 *best_mode = SYSC_IDLE_FORCE; 949 else 950 return -EINVAL; 951 952 return 0; 953 } 954 955 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ 956 static int sysc_disable_module(struct device *dev) 957 { 958 struct sysc *ddata; 959 const struct sysc_regbits *regbits; 960 u32 reg, idlemodes, best_mode; 961 int ret; 962 963 ddata = dev_get_drvdata(dev); 964 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) 965 return 0; 966 967 if (ddata->module_disable_quirk) 968 ddata->module_disable_quirk(ddata); 969 970 regbits = ddata->cap->regbits; 971 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 972 973 /* Set MIDLE mode */ 974 idlemodes = ddata->cfg.midlemodes; 975 if (!idlemodes || regbits->midle_shift < 0) 976 goto set_sidle; 977 978 ret = sysc_best_idle_mode(idlemodes, &best_mode); 979 if (ret) { 980 dev_err(dev, "%s: invalid midlemode\n", __func__); 981 return ret; 982 } 983 984 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) || 985 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY)) 986 best_mode = SYSC_IDLE_FORCE; 987 988 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); 989 reg |= best_mode << regbits->midle_shift; 990 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 991 992 set_sidle: 993 /* Set SIDLE mode */ 994 idlemodes = ddata->cfg.sidlemodes; 995 if (!idlemodes || regbits->sidle_shift < 0) 996 return 0; 997 998 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) { 999 best_mode = SYSC_IDLE_FORCE; 1000 } else { 1001 ret = sysc_best_idle_mode(idlemodes, &best_mode); 1002 if (ret) { 1003 dev_err(dev, "%s: invalid sidlemode\n", __func__); 1004 return ret; 1005 } 1006 } 1007 1008 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); 1009 reg |= best_mode << regbits->sidle_shift; 1010 if (regbits->autoidle_shift >= 0 && 1011 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) 1012 reg |= 1 << regbits->autoidle_shift; 1013 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 1014 1015 return 0; 1016 } 1017 1018 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev, 1019 struct sysc *ddata) 1020 { 1021 struct ti_sysc_platform_data *pdata; 1022 int error; 1023 1024 pdata = dev_get_platdata(ddata->dev); 1025 if (!pdata) 1026 return 0; 1027 1028 if (!pdata->idle_module) 1029 return -ENODEV; 1030 1031 error = pdata->idle_module(dev, &ddata->cookie); 1032 if (error) 1033 dev_err(dev, "%s: could not idle: %i\n", 1034 __func__, error); 1035 1036 reset_control_assert(ddata->rsts); 1037 1038 return 0; 1039 } 1040 1041 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev, 1042 struct sysc *ddata) 1043 { 1044 struct ti_sysc_platform_data *pdata; 1045 int error; 1046 1047 pdata = dev_get_platdata(ddata->dev); 1048 if (!pdata) 1049 return 0; 1050 1051 if (!pdata->enable_module) 1052 return -ENODEV; 1053 1054 error = pdata->enable_module(dev, &ddata->cookie); 1055 if (error) 1056 dev_err(dev, "%s: could not enable: %i\n", 1057 __func__, error); 1058 1059 reset_control_deassert(ddata->rsts); 1060 1061 return 0; 1062 } 1063 1064 static int __maybe_unused sysc_runtime_suspend(struct device *dev) 1065 { 1066 struct sysc *ddata; 1067 int error = 0; 1068 1069 ddata = dev_get_drvdata(dev); 1070 1071 if (!ddata->enabled) 1072 return 0; 1073 1074 sysc_clkdm_deny_idle(ddata); 1075 1076 if (ddata->legacy_mode) { 1077 error = sysc_runtime_suspend_legacy(dev, ddata); 1078 if (error) 1079 goto err_allow_idle; 1080 } else { 1081 error = sysc_disable_module(dev); 1082 if (error) 1083 goto err_allow_idle; 1084 } 1085 1086 sysc_disable_main_clocks(ddata); 1087 1088 if (sysc_opt_clks_needed(ddata)) 1089 sysc_disable_opt_clocks(ddata); 1090 1091 ddata->enabled = false; 1092 1093 err_allow_idle: 1094 reset_control_assert(ddata->rsts); 1095 1096 sysc_clkdm_allow_idle(ddata); 1097 1098 return error; 1099 } 1100 1101 static int __maybe_unused sysc_runtime_resume(struct device *dev) 1102 { 1103 struct sysc *ddata; 1104 int error = 0; 1105 1106 ddata = dev_get_drvdata(dev); 1107 1108 if (ddata->enabled) 1109 return 0; 1110 1111 1112 sysc_clkdm_deny_idle(ddata); 1113 1114 if (sysc_opt_clks_needed(ddata)) { 1115 error = sysc_enable_opt_clocks(ddata); 1116 if (error) 1117 goto err_allow_idle; 1118 } 1119 1120 error = sysc_enable_main_clocks(ddata); 1121 if (error) 1122 goto err_opt_clocks; 1123 1124 reset_control_deassert(ddata->rsts); 1125 1126 if (ddata->legacy_mode) { 1127 error = sysc_runtime_resume_legacy(dev, ddata); 1128 if (error) 1129 goto err_main_clocks; 1130 } else { 1131 error = sysc_enable_module(dev); 1132 if (error) 1133 goto err_main_clocks; 1134 } 1135 1136 ddata->enabled = true; 1137 1138 sysc_clkdm_allow_idle(ddata); 1139 1140 return 0; 1141 1142 err_main_clocks: 1143 sysc_disable_main_clocks(ddata); 1144 err_opt_clocks: 1145 if (sysc_opt_clks_needed(ddata)) 1146 sysc_disable_opt_clocks(ddata); 1147 err_allow_idle: 1148 sysc_clkdm_allow_idle(ddata); 1149 1150 return error; 1151 } 1152 1153 static int __maybe_unused sysc_noirq_suspend(struct device *dev) 1154 { 1155 struct sysc *ddata; 1156 1157 ddata = dev_get_drvdata(dev); 1158 1159 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) 1160 return 0; 1161 1162 return pm_runtime_force_suspend(dev); 1163 } 1164 1165 static int __maybe_unused sysc_noirq_resume(struct device *dev) 1166 { 1167 struct sysc *ddata; 1168 1169 ddata = dev_get_drvdata(dev); 1170 1171 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) 1172 return 0; 1173 1174 return pm_runtime_force_resume(dev); 1175 } 1176 1177 static const struct dev_pm_ops sysc_pm_ops = { 1178 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume) 1179 SET_RUNTIME_PM_OPS(sysc_runtime_suspend, 1180 sysc_runtime_resume, 1181 NULL) 1182 }; 1183 1184 /* Module revision register based quirks */ 1185 struct sysc_revision_quirk { 1186 const char *name; 1187 u32 base; 1188 int rev_offset; 1189 int sysc_offset; 1190 int syss_offset; 1191 u32 revision; 1192 u32 revision_mask; 1193 u32 quirks; 1194 }; 1195 1196 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \ 1197 optrev_val, optrevmask, optquirkmask) \ 1198 { \ 1199 .name = (optname), \ 1200 .base = (optbase), \ 1201 .rev_offset = (optrev), \ 1202 .sysc_offset = (optsysc), \ 1203 .syss_offset = (optsyss), \ 1204 .revision = (optrev_val), \ 1205 .revision_mask = (optrevmask), \ 1206 .quirks = (optquirkmask), \ 1207 } 1208 1209 static const struct sysc_revision_quirk sysc_revision_quirks[] = { 1210 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */ 1211 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff, 1212 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET), 1213 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 1214 SYSC_QUIRK_LEGACY_IDLE), 1215 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 1216 SYSC_QUIRK_LEGACY_IDLE), 1217 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, 1218 SYSC_QUIRK_LEGACY_IDLE), 1219 SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff, 1220 SYSC_QUIRK_LEGACY_IDLE), 1221 SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff, 1222 SYSC_QUIRK_LEGACY_IDLE), 1223 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 1224 0), 1225 /* Some timers on omap4 and later */ 1226 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff, 1227 0), 1228 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff, 1229 0), 1230 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff, 1231 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1232 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, 1233 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1234 /* Uarts on omap4 and later */ 1235 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff, 1236 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), 1237 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff, 1238 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), 1239 1240 /* Quirks that need to be set based on the module address */ 1241 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -1, 0x50000800, 0xffffffff, 1242 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT | 1243 SYSC_QUIRK_SWSUP_SIDLE), 1244 1245 /* Quirks that need to be set based on detected module */ 1246 SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff, 1247 SYSC_MODULE_QUIRK_AESS), 1248 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 1249 SYSC_MODULE_QUIRK_HDQ1W), 1250 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, 1251 SYSC_MODULE_QUIRK_HDQ1W), 1252 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff, 1253 SYSC_MODULE_QUIRK_I2C), 1254 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff, 1255 SYSC_MODULE_QUIRK_I2C), 1256 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff, 1257 SYSC_MODULE_QUIRK_I2C), 1258 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, 1259 SYSC_MODULE_QUIRK_I2C), 1260 SYSC_QUIRK("gpu", 0x50000000, 0x14, -1, -1, 0x00010201, 0xffffffff, 0), 1261 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff, 1262 SYSC_MODULE_QUIRK_SGX), 1263 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050, 1264 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1265 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -1, 0x4ea2080d, 0xffffffff, 1266 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1267 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 1268 SYSC_MODULE_QUIRK_WDT), 1269 /* Watchdog on am3 and am4 */ 1270 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 1271 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE), 1272 1273 #ifdef DEBUG 1274 SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0), 1275 SYSC_QUIRK("atl", 0, 0, -1, -1, 0x0a070100, 0xffffffff, 0), 1276 SYSC_QUIRK("cm", 0, 0, -1, -1, 0x40000301, 0xffffffff, 0), 1277 SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0), 1278 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902, 1279 0xffff00f0, 0), 1280 SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0xa3170504, 0xffffffff, 0), 1281 SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0x4edb1902, 0xffffffff, 0), 1282 SYSC_QUIRK("dmic", 0, 0, 0x10, -1, 0x50010000, 0xffffffff, 0), 1283 SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0), 1284 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1285 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1286 SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0), 1287 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0), 1288 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff, 0), 1289 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0), 1290 SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0), 1291 SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0), 1292 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0), 1293 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44307b02, 0xffffffff, 0), 1294 SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0), 1295 SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffff00ff, 0), 1296 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0), 1297 SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0), 1298 SYSC_QUIRK("m3", 0, 0, -1, -1, 0x5f580105, 0x0fff0f00, 0), 1299 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0), 1300 SYSC_QUIRK("ocp2scp", 0, 0, -1, -1, 0x50060007, 0xffffffff, 0), 1301 SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff, 0), 1302 SYSC_QUIRK("padconf", 0, 0, -1, -1, 0x40001100, 0xffffffff, 0), 1303 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff, 0), 1304 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x00004102, 0xffffffff, 0), 1305 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000400, 0xffffffff, 0), 1306 SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0), 1307 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4e8b0100, 0xffffffff, 0), 1308 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4f000100, 0xffffffff, 0), 1309 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x40000900, 0xffffffff, 0), 1310 SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff, 0), 1311 SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffff0ff0, 0), 1312 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0), 1313 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0), 1314 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0), 1315 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0), 1316 SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0), 1317 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -1, 0x00000020, 0xffffffff, 0), 1318 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -1, 0x4eb01908, 0xffff00f0, 0), 1319 SYSC_QUIRK("timer32k", 0, 0, 0x4, -1, 0x00000060, 0xffffffff, 0), 1320 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0), 1321 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0), 1322 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0), 1323 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -1, 0x50700101, 0xffffffff, 0), 1324 SYSC_QUIRK("vfpe", 0, 0, 0x104, -1, 0x4d001200, 0xffffffff, 0), 1325 #endif 1326 }; 1327 1328 /* 1329 * Early quirks based on module base and register offsets only that are 1330 * needed before the module revision can be read 1331 */ 1332 static void sysc_init_early_quirks(struct sysc *ddata) 1333 { 1334 const struct sysc_revision_quirk *q; 1335 int i; 1336 1337 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { 1338 q = &sysc_revision_quirks[i]; 1339 1340 if (!q->base) 1341 continue; 1342 1343 if (q->base != ddata->module_pa) 1344 continue; 1345 1346 if (q->rev_offset >= 0 && 1347 q->rev_offset != ddata->offsets[SYSC_REVISION]) 1348 continue; 1349 1350 if (q->sysc_offset >= 0 && 1351 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) 1352 continue; 1353 1354 if (q->syss_offset >= 0 && 1355 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) 1356 continue; 1357 1358 ddata->name = q->name; 1359 ddata->cfg.quirks |= q->quirks; 1360 } 1361 } 1362 1363 /* Quirks that also consider the revision register value */ 1364 static void sysc_init_revision_quirks(struct sysc *ddata) 1365 { 1366 const struct sysc_revision_quirk *q; 1367 int i; 1368 1369 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { 1370 q = &sysc_revision_quirks[i]; 1371 1372 if (q->base && q->base != ddata->module_pa) 1373 continue; 1374 1375 if (q->rev_offset >= 0 && 1376 q->rev_offset != ddata->offsets[SYSC_REVISION]) 1377 continue; 1378 1379 if (q->sysc_offset >= 0 && 1380 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) 1381 continue; 1382 1383 if (q->syss_offset >= 0 && 1384 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) 1385 continue; 1386 1387 if (q->revision == ddata->revision || 1388 (q->revision & q->revision_mask) == 1389 (ddata->revision & q->revision_mask)) { 1390 ddata->name = q->name; 1391 ddata->cfg.quirks |= q->quirks; 1392 } 1393 } 1394 } 1395 1396 /* 1-wire needs module's internal clocks enabled for reset */ 1397 static void sysc_clk_enable_quirk_hdq1w(struct sysc *ddata) 1398 { 1399 int offset = 0x0c; /* HDQ_CTRL_STATUS */ 1400 u16 val; 1401 1402 val = sysc_read(ddata, offset); 1403 val |= BIT(5); 1404 sysc_write(ddata, offset, val); 1405 } 1406 1407 /* AESS (Audio Engine SubSystem) needs autogating set after enable */ 1408 static void sysc_module_enable_quirk_aess(struct sysc *ddata) 1409 { 1410 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */ 1411 1412 sysc_write(ddata, offset, 1); 1413 } 1414 1415 /* I2C needs extra enable bit toggling for reset */ 1416 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable) 1417 { 1418 int offset; 1419 u16 val; 1420 1421 /* I2C_CON, omap2/3 is different from omap4 and later */ 1422 if ((ddata->revision & 0xffffff00) == 0x001f0000) 1423 offset = 0x24; 1424 else 1425 offset = 0xa4; 1426 1427 /* I2C_EN */ 1428 val = sysc_read(ddata, offset); 1429 if (enable) 1430 val |= BIT(15); 1431 else 1432 val &= ~BIT(15); 1433 sysc_write(ddata, offset, val); 1434 } 1435 1436 static void sysc_clk_enable_quirk_i2c(struct sysc *ddata) 1437 { 1438 sysc_clk_quirk_i2c(ddata, true); 1439 } 1440 1441 static void sysc_clk_disable_quirk_i2c(struct sysc *ddata) 1442 { 1443 sysc_clk_quirk_i2c(ddata, false); 1444 } 1445 1446 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */ 1447 static void sysc_module_enable_quirk_sgx(struct sysc *ddata) 1448 { 1449 int offset = 0xff08; /* OCP_DEBUG_CONFIG */ 1450 u32 val = BIT(31); /* THALIA_INT_BYPASS */ 1451 1452 sysc_write(ddata, offset, val); 1453 } 1454 1455 /* Watchdog timer needs a disable sequence after reset */ 1456 static void sysc_reset_done_quirk_wdt(struct sysc *ddata) 1457 { 1458 int wps, spr, error; 1459 u32 val; 1460 1461 wps = 0x34; 1462 spr = 0x48; 1463 1464 sysc_write(ddata, spr, 0xaaaa); 1465 error = readl_poll_timeout(ddata->module_va + wps, val, 1466 !(val & 0x10), 100, 1467 MAX_MODULE_SOFTRESET_WAIT); 1468 if (error) 1469 dev_warn(ddata->dev, "wdt disable step1 failed\n"); 1470 1471 sysc_write(ddata, spr, 0x5555); 1472 error = readl_poll_timeout(ddata->module_va + wps, val, 1473 !(val & 0x10), 100, 1474 MAX_MODULE_SOFTRESET_WAIT); 1475 if (error) 1476 dev_warn(ddata->dev, "wdt disable step2 failed\n"); 1477 } 1478 1479 static void sysc_init_module_quirks(struct sysc *ddata) 1480 { 1481 if (ddata->legacy_mode || !ddata->name) 1482 return; 1483 1484 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) { 1485 ddata->clk_enable_quirk = sysc_clk_enable_quirk_hdq1w; 1486 1487 return; 1488 } 1489 1490 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) { 1491 ddata->clk_enable_quirk = sysc_clk_enable_quirk_i2c; 1492 ddata->clk_disable_quirk = sysc_clk_disable_quirk_i2c; 1493 1494 return; 1495 } 1496 1497 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS) 1498 ddata->module_enable_quirk = sysc_module_enable_quirk_aess; 1499 1500 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX) 1501 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx; 1502 1503 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) { 1504 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt; 1505 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt; 1506 } 1507 } 1508 1509 static int sysc_clockdomain_init(struct sysc *ddata) 1510 { 1511 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 1512 struct clk *fck = NULL, *ick = NULL; 1513 int error; 1514 1515 if (!pdata || !pdata->init_clockdomain) 1516 return 0; 1517 1518 switch (ddata->nr_clocks) { 1519 case 2: 1520 ick = ddata->clocks[SYSC_ICK]; 1521 /* fallthrough */ 1522 case 1: 1523 fck = ddata->clocks[SYSC_FCK]; 1524 break; 1525 case 0: 1526 return 0; 1527 } 1528 1529 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie); 1530 if (!error || error == -ENODEV) 1531 return 0; 1532 1533 return error; 1534 } 1535 1536 /* 1537 * Note that pdata->init_module() typically does a reset first. After 1538 * pdata->init_module() is done, PM runtime can be used for the interconnect 1539 * target module. 1540 */ 1541 static int sysc_legacy_init(struct sysc *ddata) 1542 { 1543 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 1544 int error; 1545 1546 if (!pdata || !pdata->init_module) 1547 return 0; 1548 1549 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie); 1550 if (error == -EEXIST) 1551 error = 0; 1552 1553 return error; 1554 } 1555 1556 /* 1557 * Note that the caller must ensure the interconnect target module is enabled 1558 * before calling reset. Otherwise reset will not complete. 1559 */ 1560 static int sysc_reset(struct sysc *ddata) 1561 { 1562 int sysc_offset, syss_offset, sysc_val, rstval, error = 0; 1563 u32 sysc_mask, syss_done; 1564 1565 sysc_offset = ddata->offsets[SYSC_SYSCONFIG]; 1566 syss_offset = ddata->offsets[SYSC_SYSSTATUS]; 1567 1568 if (ddata->legacy_mode || sysc_offset < 0 || 1569 ddata->cap->regbits->srst_shift < 0 || 1570 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) 1571 return 0; 1572 1573 sysc_mask = BIT(ddata->cap->regbits->srst_shift); 1574 1575 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED) 1576 syss_done = 0; 1577 else 1578 syss_done = ddata->cfg.syss_mask; 1579 1580 if (ddata->clk_disable_quirk) 1581 ddata->clk_disable_quirk(ddata); 1582 1583 sysc_val = sysc_read_sysconfig(ddata); 1584 sysc_val |= sysc_mask; 1585 sysc_write(ddata, sysc_offset, sysc_val); 1586 1587 if (ddata->cfg.srst_udelay) 1588 usleep_range(ddata->cfg.srst_udelay, 1589 ddata->cfg.srst_udelay * 2); 1590 1591 if (ddata->clk_enable_quirk) 1592 ddata->clk_enable_quirk(ddata); 1593 1594 /* Poll on reset status */ 1595 if (syss_offset >= 0) { 1596 error = readx_poll_timeout(sysc_read_sysstatus, ddata, rstval, 1597 (rstval & ddata->cfg.syss_mask) == 1598 syss_done, 1599 100, MAX_MODULE_SOFTRESET_WAIT); 1600 1601 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) { 1602 error = readx_poll_timeout(sysc_read_sysconfig, ddata, rstval, 1603 !(rstval & sysc_mask), 1604 100, MAX_MODULE_SOFTRESET_WAIT); 1605 } 1606 1607 if (ddata->reset_done_quirk) 1608 ddata->reset_done_quirk(ddata); 1609 1610 return error; 1611 } 1612 1613 /* 1614 * At this point the module is configured enough to read the revision but 1615 * module may not be completely configured yet to use PM runtime. Enable 1616 * all clocks directly during init to configure the quirks needed for PM 1617 * runtime based on the revision register. 1618 */ 1619 static int sysc_init_module(struct sysc *ddata) 1620 { 1621 int error = 0; 1622 1623 error = sysc_clockdomain_init(ddata); 1624 if (error) 1625 return error; 1626 1627 sysc_clkdm_deny_idle(ddata); 1628 1629 /* 1630 * Always enable clocks. The bootloader may or may not have enabled 1631 * the related clocks. 1632 */ 1633 error = sysc_enable_opt_clocks(ddata); 1634 if (error) 1635 return error; 1636 1637 error = sysc_enable_main_clocks(ddata); 1638 if (error) 1639 goto err_opt_clocks; 1640 1641 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) { 1642 error = reset_control_deassert(ddata->rsts); 1643 if (error) 1644 goto err_main_clocks; 1645 } 1646 1647 ddata->revision = sysc_read_revision(ddata); 1648 sysc_init_revision_quirks(ddata); 1649 sysc_init_module_quirks(ddata); 1650 1651 if (ddata->legacy_mode) { 1652 error = sysc_legacy_init(ddata); 1653 if (error) 1654 goto err_reset; 1655 } 1656 1657 if (!ddata->legacy_mode) { 1658 error = sysc_enable_module(ddata->dev); 1659 if (error) 1660 goto err_reset; 1661 } 1662 1663 error = sysc_reset(ddata); 1664 if (error) 1665 dev_err(ddata->dev, "Reset failed with %d\n", error); 1666 1667 if (error && !ddata->legacy_mode) 1668 sysc_disable_module(ddata->dev); 1669 1670 err_reset: 1671 if (error && !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) 1672 reset_control_assert(ddata->rsts); 1673 1674 err_main_clocks: 1675 if (error) 1676 sysc_disable_main_clocks(ddata); 1677 err_opt_clocks: 1678 /* No re-enable of clockdomain autoidle to prevent module autoidle */ 1679 if (error) { 1680 sysc_disable_opt_clocks(ddata); 1681 sysc_clkdm_allow_idle(ddata); 1682 } 1683 1684 return error; 1685 } 1686 1687 static int sysc_init_sysc_mask(struct sysc *ddata) 1688 { 1689 struct device_node *np = ddata->dev->of_node; 1690 int error; 1691 u32 val; 1692 1693 error = of_property_read_u32(np, "ti,sysc-mask", &val); 1694 if (error) 1695 return 0; 1696 1697 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask; 1698 1699 return 0; 1700 } 1701 1702 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes, 1703 const char *name) 1704 { 1705 struct device_node *np = ddata->dev->of_node; 1706 struct property *prop; 1707 const __be32 *p; 1708 u32 val; 1709 1710 of_property_for_each_u32(np, name, prop, p, val) { 1711 if (val >= SYSC_NR_IDLEMODES) { 1712 dev_err(ddata->dev, "invalid idlemode: %i\n", val); 1713 return -EINVAL; 1714 } 1715 *idlemodes |= (1 << val); 1716 } 1717 1718 return 0; 1719 } 1720 1721 static int sysc_init_idlemodes(struct sysc *ddata) 1722 { 1723 int error; 1724 1725 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes, 1726 "ti,sysc-midle"); 1727 if (error) 1728 return error; 1729 1730 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes, 1731 "ti,sysc-sidle"); 1732 if (error) 1733 return error; 1734 1735 return 0; 1736 } 1737 1738 /* 1739 * Only some devices on omap4 and later have SYSCONFIG reset done 1740 * bit. We can detect this if there is no SYSSTATUS at all, or the 1741 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers 1742 * have multiple bits for the child devices like OHCI and EHCI. 1743 * Depends on SYSC being parsed first. 1744 */ 1745 static int sysc_init_syss_mask(struct sysc *ddata) 1746 { 1747 struct device_node *np = ddata->dev->of_node; 1748 int error; 1749 u32 val; 1750 1751 error = of_property_read_u32(np, "ti,syss-mask", &val); 1752 if (error) { 1753 if ((ddata->cap->type == TI_SYSC_OMAP4 || 1754 ddata->cap->type == TI_SYSC_OMAP4_TIMER) && 1755 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) 1756 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; 1757 1758 return 0; 1759 } 1760 1761 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) 1762 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; 1763 1764 ddata->cfg.syss_mask = val; 1765 1766 return 0; 1767 } 1768 1769 /* 1770 * Many child device drivers need to have fck and opt clocks available 1771 * to get the clock rate for device internal configuration etc. 1772 */ 1773 static int sysc_child_add_named_clock(struct sysc *ddata, 1774 struct device *child, 1775 const char *name) 1776 { 1777 struct clk *clk; 1778 struct clk_lookup *l; 1779 int error = 0; 1780 1781 if (!name) 1782 return 0; 1783 1784 clk = clk_get(child, name); 1785 if (!IS_ERR(clk)) { 1786 error = -EEXIST; 1787 goto put_clk; 1788 } 1789 1790 clk = clk_get(ddata->dev, name); 1791 if (IS_ERR(clk)) 1792 return -ENODEV; 1793 1794 l = clkdev_create(clk, name, dev_name(child)); 1795 if (!l) 1796 error = -ENOMEM; 1797 put_clk: 1798 clk_put(clk); 1799 1800 return error; 1801 } 1802 1803 static int sysc_child_add_clocks(struct sysc *ddata, 1804 struct device *child) 1805 { 1806 int i, error; 1807 1808 for (i = 0; i < ddata->nr_clocks; i++) { 1809 error = sysc_child_add_named_clock(ddata, 1810 child, 1811 ddata->clock_roles[i]); 1812 if (error && error != -EEXIST) { 1813 dev_err(ddata->dev, "could not add child clock %s: %i\n", 1814 ddata->clock_roles[i], error); 1815 1816 return error; 1817 } 1818 } 1819 1820 return 0; 1821 } 1822 1823 static struct device_type sysc_device_type = { 1824 }; 1825 1826 static struct sysc *sysc_child_to_parent(struct device *dev) 1827 { 1828 struct device *parent = dev->parent; 1829 1830 if (!parent || parent->type != &sysc_device_type) 1831 return NULL; 1832 1833 return dev_get_drvdata(parent); 1834 } 1835 1836 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev) 1837 { 1838 struct sysc *ddata; 1839 int error; 1840 1841 ddata = sysc_child_to_parent(dev); 1842 1843 error = pm_generic_runtime_suspend(dev); 1844 if (error) 1845 return error; 1846 1847 if (!ddata->enabled) 1848 return 0; 1849 1850 return sysc_runtime_suspend(ddata->dev); 1851 } 1852 1853 static int __maybe_unused sysc_child_runtime_resume(struct device *dev) 1854 { 1855 struct sysc *ddata; 1856 int error; 1857 1858 ddata = sysc_child_to_parent(dev); 1859 1860 if (!ddata->enabled) { 1861 error = sysc_runtime_resume(ddata->dev); 1862 if (error < 0) 1863 dev_err(ddata->dev, 1864 "%s error: %i\n", __func__, error); 1865 } 1866 1867 return pm_generic_runtime_resume(dev); 1868 } 1869 1870 #ifdef CONFIG_PM_SLEEP 1871 static int sysc_child_suspend_noirq(struct device *dev) 1872 { 1873 struct sysc *ddata; 1874 int error; 1875 1876 ddata = sysc_child_to_parent(dev); 1877 1878 dev_dbg(ddata->dev, "%s %s\n", __func__, 1879 ddata->name ? ddata->name : ""); 1880 1881 error = pm_generic_suspend_noirq(dev); 1882 if (error) { 1883 dev_err(dev, "%s error at %i: %i\n", 1884 __func__, __LINE__, error); 1885 1886 return error; 1887 } 1888 1889 if (!pm_runtime_status_suspended(dev)) { 1890 error = pm_generic_runtime_suspend(dev); 1891 if (error) { 1892 dev_dbg(dev, "%s busy at %i: %i\n", 1893 __func__, __LINE__, error); 1894 1895 return 0; 1896 } 1897 1898 error = sysc_runtime_suspend(ddata->dev); 1899 if (error) { 1900 dev_err(dev, "%s error at %i: %i\n", 1901 __func__, __LINE__, error); 1902 1903 return error; 1904 } 1905 1906 ddata->child_needs_resume = true; 1907 } 1908 1909 return 0; 1910 } 1911 1912 static int sysc_child_resume_noirq(struct device *dev) 1913 { 1914 struct sysc *ddata; 1915 int error; 1916 1917 ddata = sysc_child_to_parent(dev); 1918 1919 dev_dbg(ddata->dev, "%s %s\n", __func__, 1920 ddata->name ? ddata->name : ""); 1921 1922 if (ddata->child_needs_resume) { 1923 ddata->child_needs_resume = false; 1924 1925 error = sysc_runtime_resume(ddata->dev); 1926 if (error) 1927 dev_err(ddata->dev, 1928 "%s runtime resume error: %i\n", 1929 __func__, error); 1930 1931 error = pm_generic_runtime_resume(dev); 1932 if (error) 1933 dev_err(ddata->dev, 1934 "%s generic runtime resume: %i\n", 1935 __func__, error); 1936 } 1937 1938 return pm_generic_resume_noirq(dev); 1939 } 1940 #endif 1941 1942 static struct dev_pm_domain sysc_child_pm_domain = { 1943 .ops = { 1944 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend, 1945 sysc_child_runtime_resume, 1946 NULL) 1947 USE_PLATFORM_PM_SLEEP_OPS 1948 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq, 1949 sysc_child_resume_noirq) 1950 } 1951 }; 1952 1953 /** 1954 * sysc_legacy_idle_quirk - handle children in omap_device compatible way 1955 * @ddata: device driver data 1956 * @child: child device driver 1957 * 1958 * Allow idle for child devices as done with _od_runtime_suspend(). 1959 * Otherwise many child devices will not idle because of the permanent 1960 * parent usecount set in pm_runtime_irq_safe(). 1961 * 1962 * Note that the long term solution is to just modify the child device 1963 * drivers to not set pm_runtime_irq_safe() and then this can be just 1964 * dropped. 1965 */ 1966 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child) 1967 { 1968 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) 1969 dev_pm_domain_set(child, &sysc_child_pm_domain); 1970 } 1971 1972 static int sysc_notifier_call(struct notifier_block *nb, 1973 unsigned long event, void *device) 1974 { 1975 struct device *dev = device; 1976 struct sysc *ddata; 1977 int error; 1978 1979 ddata = sysc_child_to_parent(dev); 1980 if (!ddata) 1981 return NOTIFY_DONE; 1982 1983 switch (event) { 1984 case BUS_NOTIFY_ADD_DEVICE: 1985 error = sysc_child_add_clocks(ddata, dev); 1986 if (error) 1987 return error; 1988 sysc_legacy_idle_quirk(ddata, dev); 1989 break; 1990 default: 1991 break; 1992 } 1993 1994 return NOTIFY_DONE; 1995 } 1996 1997 static struct notifier_block sysc_nb = { 1998 .notifier_call = sysc_notifier_call, 1999 }; 2000 2001 /* Device tree configured quirks */ 2002 struct sysc_dts_quirk { 2003 const char *name; 2004 u32 mask; 2005 }; 2006 2007 static const struct sysc_dts_quirk sysc_dts_quirks[] = { 2008 { .name = "ti,no-idle-on-init", 2009 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, }, 2010 { .name = "ti,no-reset-on-init", 2011 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, }, 2012 { .name = "ti,no-idle", 2013 .mask = SYSC_QUIRK_NO_IDLE, }, 2014 }; 2015 2016 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, 2017 bool is_child) 2018 { 2019 const struct property *prop; 2020 int i, len; 2021 2022 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) { 2023 const char *name = sysc_dts_quirks[i].name; 2024 2025 prop = of_get_property(np, name, &len); 2026 if (!prop) 2027 continue; 2028 2029 ddata->cfg.quirks |= sysc_dts_quirks[i].mask; 2030 if (is_child) { 2031 dev_warn(ddata->dev, 2032 "dts flag should be at module level for %s\n", 2033 name); 2034 } 2035 } 2036 } 2037 2038 static int sysc_init_dts_quirks(struct sysc *ddata) 2039 { 2040 struct device_node *np = ddata->dev->of_node; 2041 int error; 2042 u32 val; 2043 2044 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL); 2045 2046 sysc_parse_dts_quirks(ddata, np, false); 2047 error = of_property_read_u32(np, "ti,sysc-delay-us", &val); 2048 if (!error) { 2049 if (val > 255) { 2050 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n", 2051 val); 2052 } 2053 2054 ddata->cfg.srst_udelay = (u8)val; 2055 } 2056 2057 return 0; 2058 } 2059 2060 static void sysc_unprepare(struct sysc *ddata) 2061 { 2062 int i; 2063 2064 if (!ddata->clocks) 2065 return; 2066 2067 for (i = 0; i < SYSC_MAX_CLOCKS; i++) { 2068 if (!IS_ERR_OR_NULL(ddata->clocks[i])) 2069 clk_unprepare(ddata->clocks[i]); 2070 } 2071 } 2072 2073 /* 2074 * Common sysc register bits found on omap2, also known as type1 2075 */ 2076 static const struct sysc_regbits sysc_regbits_omap2 = { 2077 .dmadisable_shift = -ENODEV, 2078 .midle_shift = 12, 2079 .sidle_shift = 3, 2080 .clkact_shift = 8, 2081 .emufree_shift = 5, 2082 .enwkup_shift = 2, 2083 .srst_shift = 1, 2084 .autoidle_shift = 0, 2085 }; 2086 2087 static const struct sysc_capabilities sysc_omap2 = { 2088 .type = TI_SYSC_OMAP2, 2089 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | 2090 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | 2091 SYSC_OMAP2_AUTOIDLE, 2092 .regbits = &sysc_regbits_omap2, 2093 }; 2094 2095 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */ 2096 static const struct sysc_capabilities sysc_omap2_timer = { 2097 .type = TI_SYSC_OMAP2_TIMER, 2098 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | 2099 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | 2100 SYSC_OMAP2_AUTOIDLE, 2101 .regbits = &sysc_regbits_omap2, 2102 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT, 2103 }; 2104 2105 /* 2106 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2 2107 * with different sidle position 2108 */ 2109 static const struct sysc_regbits sysc_regbits_omap3_sham = { 2110 .dmadisable_shift = -ENODEV, 2111 .midle_shift = -ENODEV, 2112 .sidle_shift = 4, 2113 .clkact_shift = -ENODEV, 2114 .enwkup_shift = -ENODEV, 2115 .srst_shift = 1, 2116 .autoidle_shift = 0, 2117 .emufree_shift = -ENODEV, 2118 }; 2119 2120 static const struct sysc_capabilities sysc_omap3_sham = { 2121 .type = TI_SYSC_OMAP3_SHAM, 2122 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, 2123 .regbits = &sysc_regbits_omap3_sham, 2124 }; 2125 2126 /* 2127 * AES register bits found on omap3 and later, a variant of 2128 * sysc_regbits_omap2 with different sidle position 2129 */ 2130 static const struct sysc_regbits sysc_regbits_omap3_aes = { 2131 .dmadisable_shift = -ENODEV, 2132 .midle_shift = -ENODEV, 2133 .sidle_shift = 6, 2134 .clkact_shift = -ENODEV, 2135 .enwkup_shift = -ENODEV, 2136 .srst_shift = 1, 2137 .autoidle_shift = 0, 2138 .emufree_shift = -ENODEV, 2139 }; 2140 2141 static const struct sysc_capabilities sysc_omap3_aes = { 2142 .type = TI_SYSC_OMAP3_AES, 2143 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, 2144 .regbits = &sysc_regbits_omap3_aes, 2145 }; 2146 2147 /* 2148 * Common sysc register bits found on omap4, also known as type2 2149 */ 2150 static const struct sysc_regbits sysc_regbits_omap4 = { 2151 .dmadisable_shift = 16, 2152 .midle_shift = 4, 2153 .sidle_shift = 2, 2154 .clkact_shift = -ENODEV, 2155 .enwkup_shift = -ENODEV, 2156 .emufree_shift = 1, 2157 .srst_shift = 0, 2158 .autoidle_shift = -ENODEV, 2159 }; 2160 2161 static const struct sysc_capabilities sysc_omap4 = { 2162 .type = TI_SYSC_OMAP4, 2163 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | 2164 SYSC_OMAP4_SOFTRESET, 2165 .regbits = &sysc_regbits_omap4, 2166 }; 2167 2168 static const struct sysc_capabilities sysc_omap4_timer = { 2169 .type = TI_SYSC_OMAP4_TIMER, 2170 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | 2171 SYSC_OMAP4_SOFTRESET, 2172 .regbits = &sysc_regbits_omap4, 2173 }; 2174 2175 /* 2176 * Common sysc register bits found on omap4, also known as type3 2177 */ 2178 static const struct sysc_regbits sysc_regbits_omap4_simple = { 2179 .dmadisable_shift = -ENODEV, 2180 .midle_shift = 2, 2181 .sidle_shift = 0, 2182 .clkact_shift = -ENODEV, 2183 .enwkup_shift = -ENODEV, 2184 .srst_shift = -ENODEV, 2185 .emufree_shift = -ENODEV, 2186 .autoidle_shift = -ENODEV, 2187 }; 2188 2189 static const struct sysc_capabilities sysc_omap4_simple = { 2190 .type = TI_SYSC_OMAP4_SIMPLE, 2191 .regbits = &sysc_regbits_omap4_simple, 2192 }; 2193 2194 /* 2195 * SmartReflex sysc found on omap34xx 2196 */ 2197 static const struct sysc_regbits sysc_regbits_omap34xx_sr = { 2198 .dmadisable_shift = -ENODEV, 2199 .midle_shift = -ENODEV, 2200 .sidle_shift = -ENODEV, 2201 .clkact_shift = 20, 2202 .enwkup_shift = -ENODEV, 2203 .srst_shift = -ENODEV, 2204 .emufree_shift = -ENODEV, 2205 .autoidle_shift = -ENODEV, 2206 }; 2207 2208 static const struct sysc_capabilities sysc_34xx_sr = { 2209 .type = TI_SYSC_OMAP34XX_SR, 2210 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY, 2211 .regbits = &sysc_regbits_omap34xx_sr, 2212 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED | 2213 SYSC_QUIRK_LEGACY_IDLE, 2214 }; 2215 2216 /* 2217 * SmartReflex sysc found on omap36xx and later 2218 */ 2219 static const struct sysc_regbits sysc_regbits_omap36xx_sr = { 2220 .dmadisable_shift = -ENODEV, 2221 .midle_shift = -ENODEV, 2222 .sidle_shift = 24, 2223 .clkact_shift = -ENODEV, 2224 .enwkup_shift = 26, 2225 .srst_shift = -ENODEV, 2226 .emufree_shift = -ENODEV, 2227 .autoidle_shift = -ENODEV, 2228 }; 2229 2230 static const struct sysc_capabilities sysc_36xx_sr = { 2231 .type = TI_SYSC_OMAP36XX_SR, 2232 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP, 2233 .regbits = &sysc_regbits_omap36xx_sr, 2234 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE, 2235 }; 2236 2237 static const struct sysc_capabilities sysc_omap4_sr = { 2238 .type = TI_SYSC_OMAP4_SR, 2239 .regbits = &sysc_regbits_omap36xx_sr, 2240 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE, 2241 }; 2242 2243 /* 2244 * McASP register bits found on omap4 and later 2245 */ 2246 static const struct sysc_regbits sysc_regbits_omap4_mcasp = { 2247 .dmadisable_shift = -ENODEV, 2248 .midle_shift = -ENODEV, 2249 .sidle_shift = 0, 2250 .clkact_shift = -ENODEV, 2251 .enwkup_shift = -ENODEV, 2252 .srst_shift = -ENODEV, 2253 .emufree_shift = -ENODEV, 2254 .autoidle_shift = -ENODEV, 2255 }; 2256 2257 static const struct sysc_capabilities sysc_omap4_mcasp = { 2258 .type = TI_SYSC_OMAP4_MCASP, 2259 .regbits = &sysc_regbits_omap4_mcasp, 2260 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, 2261 }; 2262 2263 /* 2264 * McASP found on dra7 and later 2265 */ 2266 static const struct sysc_capabilities sysc_dra7_mcasp = { 2267 .type = TI_SYSC_OMAP4_SIMPLE, 2268 .regbits = &sysc_regbits_omap4_simple, 2269 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, 2270 }; 2271 2272 /* 2273 * FS USB host found on omap4 and later 2274 */ 2275 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = { 2276 .dmadisable_shift = -ENODEV, 2277 .midle_shift = -ENODEV, 2278 .sidle_shift = 24, 2279 .clkact_shift = -ENODEV, 2280 .enwkup_shift = 26, 2281 .srst_shift = -ENODEV, 2282 .emufree_shift = -ENODEV, 2283 .autoidle_shift = -ENODEV, 2284 }; 2285 2286 static const struct sysc_capabilities sysc_omap4_usb_host_fs = { 2287 .type = TI_SYSC_OMAP4_USB_HOST_FS, 2288 .sysc_mask = SYSC_OMAP2_ENAWAKEUP, 2289 .regbits = &sysc_regbits_omap4_usb_host_fs, 2290 }; 2291 2292 static const struct sysc_regbits sysc_regbits_dra7_mcan = { 2293 .dmadisable_shift = -ENODEV, 2294 .midle_shift = -ENODEV, 2295 .sidle_shift = -ENODEV, 2296 .clkact_shift = -ENODEV, 2297 .enwkup_shift = 4, 2298 .srst_shift = 0, 2299 .emufree_shift = -ENODEV, 2300 .autoidle_shift = -ENODEV, 2301 }; 2302 2303 static const struct sysc_capabilities sysc_dra7_mcan = { 2304 .type = TI_SYSC_DRA7_MCAN, 2305 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET, 2306 .regbits = &sysc_regbits_dra7_mcan, 2307 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED, 2308 }; 2309 2310 static int sysc_init_pdata(struct sysc *ddata) 2311 { 2312 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 2313 struct ti_sysc_module_data *mdata; 2314 2315 if (!pdata) 2316 return 0; 2317 2318 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL); 2319 if (!mdata) 2320 return -ENOMEM; 2321 2322 if (ddata->legacy_mode) { 2323 mdata->name = ddata->legacy_mode; 2324 mdata->module_pa = ddata->module_pa; 2325 mdata->module_size = ddata->module_size; 2326 mdata->offsets = ddata->offsets; 2327 mdata->nr_offsets = SYSC_MAX_REGS; 2328 mdata->cap = ddata->cap; 2329 mdata->cfg = &ddata->cfg; 2330 } 2331 2332 ddata->mdata = mdata; 2333 2334 return 0; 2335 } 2336 2337 static int sysc_init_match(struct sysc *ddata) 2338 { 2339 const struct sysc_capabilities *cap; 2340 2341 cap = of_device_get_match_data(ddata->dev); 2342 if (!cap) 2343 return -EINVAL; 2344 2345 ddata->cap = cap; 2346 if (ddata->cap) 2347 ddata->cfg.quirks |= ddata->cap->mod_quirks; 2348 2349 return 0; 2350 } 2351 2352 static void ti_sysc_idle(struct work_struct *work) 2353 { 2354 struct sysc *ddata; 2355 2356 ddata = container_of(work, struct sysc, idle_work.work); 2357 2358 /* 2359 * One time decrement of clock usage counts if left on from init. 2360 * Note that we disable opt clocks unconditionally in this case 2361 * as they are enabled unconditionally during init without 2362 * considering sysc_opt_clks_needed() at that point. 2363 */ 2364 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | 2365 SYSC_QUIRK_NO_IDLE_ON_INIT)) { 2366 sysc_disable_main_clocks(ddata); 2367 sysc_disable_opt_clocks(ddata); 2368 sysc_clkdm_allow_idle(ddata); 2369 } 2370 2371 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */ 2372 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE) 2373 return; 2374 2375 /* 2376 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT 2377 * and SYSC_QUIRK_NO_RESET_ON_INIT 2378 */ 2379 if (pm_runtime_active(ddata->dev)) 2380 pm_runtime_put_sync(ddata->dev); 2381 } 2382 2383 static const struct of_device_id sysc_match_table[] = { 2384 { .compatible = "simple-bus", }, 2385 { /* sentinel */ }, 2386 }; 2387 2388 static int sysc_probe(struct platform_device *pdev) 2389 { 2390 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev); 2391 struct sysc *ddata; 2392 int error; 2393 2394 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); 2395 if (!ddata) 2396 return -ENOMEM; 2397 2398 ddata->dev = &pdev->dev; 2399 platform_set_drvdata(pdev, ddata); 2400 2401 error = sysc_init_match(ddata); 2402 if (error) 2403 return error; 2404 2405 error = sysc_init_dts_quirks(ddata); 2406 if (error) 2407 return error; 2408 2409 error = sysc_map_and_check_registers(ddata); 2410 if (error) 2411 return error; 2412 2413 error = sysc_init_sysc_mask(ddata); 2414 if (error) 2415 return error; 2416 2417 error = sysc_init_idlemodes(ddata); 2418 if (error) 2419 return error; 2420 2421 error = sysc_init_syss_mask(ddata); 2422 if (error) 2423 return error; 2424 2425 error = sysc_init_pdata(ddata); 2426 if (error) 2427 return error; 2428 2429 sysc_init_early_quirks(ddata); 2430 2431 error = sysc_get_clocks(ddata); 2432 if (error) 2433 return error; 2434 2435 error = sysc_init_resets(ddata); 2436 if (error) 2437 goto unprepare; 2438 2439 error = sysc_init_module(ddata); 2440 if (error) 2441 goto unprepare; 2442 2443 pm_runtime_enable(ddata->dev); 2444 error = pm_runtime_get_sync(ddata->dev); 2445 if (error < 0) { 2446 pm_runtime_put_noidle(ddata->dev); 2447 pm_runtime_disable(ddata->dev); 2448 goto unprepare; 2449 } 2450 2451 /* Balance use counts as PM runtime should have enabled these all */ 2452 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) 2453 reset_control_assert(ddata->rsts); 2454 2455 if (!(ddata->cfg.quirks & 2456 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) { 2457 sysc_disable_main_clocks(ddata); 2458 sysc_disable_opt_clocks(ddata); 2459 sysc_clkdm_allow_idle(ddata); 2460 } 2461 2462 sysc_show_registers(ddata); 2463 2464 ddata->dev->type = &sysc_device_type; 2465 error = of_platform_populate(ddata->dev->of_node, sysc_match_table, 2466 pdata ? pdata->auxdata : NULL, 2467 ddata->dev); 2468 if (error) 2469 goto err; 2470 2471 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle); 2472 2473 /* At least earlycon won't survive without deferred idle */ 2474 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | 2475 SYSC_QUIRK_NO_IDLE_ON_INIT | 2476 SYSC_QUIRK_NO_RESET_ON_INIT)) { 2477 schedule_delayed_work(&ddata->idle_work, 3000); 2478 } else { 2479 pm_runtime_put(&pdev->dev); 2480 } 2481 2482 return 0; 2483 2484 err: 2485 pm_runtime_put_sync(&pdev->dev); 2486 pm_runtime_disable(&pdev->dev); 2487 unprepare: 2488 sysc_unprepare(ddata); 2489 2490 return error; 2491 } 2492 2493 static int sysc_remove(struct platform_device *pdev) 2494 { 2495 struct sysc *ddata = platform_get_drvdata(pdev); 2496 int error; 2497 2498 cancel_delayed_work_sync(&ddata->idle_work); 2499 2500 error = pm_runtime_get_sync(ddata->dev); 2501 if (error < 0) { 2502 pm_runtime_put_noidle(ddata->dev); 2503 pm_runtime_disable(ddata->dev); 2504 goto unprepare; 2505 } 2506 2507 of_platform_depopulate(&pdev->dev); 2508 2509 pm_runtime_put_sync(&pdev->dev); 2510 pm_runtime_disable(&pdev->dev); 2511 reset_control_assert(ddata->rsts); 2512 2513 unprepare: 2514 sysc_unprepare(ddata); 2515 2516 return 0; 2517 } 2518 2519 static const struct of_device_id sysc_match[] = { 2520 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, }, 2521 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, }, 2522 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, }, 2523 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, }, 2524 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, }, 2525 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, }, 2526 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, }, 2527 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, }, 2528 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, }, 2529 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, }, 2530 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, }, 2531 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, }, 2532 { .compatible = "ti,sysc-usb-host-fs", 2533 .data = &sysc_omap4_usb_host_fs, }, 2534 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, }, 2535 { }, 2536 }; 2537 MODULE_DEVICE_TABLE(of, sysc_match); 2538 2539 static struct platform_driver sysc_driver = { 2540 .probe = sysc_probe, 2541 .remove = sysc_remove, 2542 .driver = { 2543 .name = "ti-sysc", 2544 .of_match_table = sysc_match, 2545 .pm = &sysc_pm_ops, 2546 }, 2547 }; 2548 2549 static int __init sysc_init(void) 2550 { 2551 bus_register_notifier(&platform_bus_type, &sysc_nb); 2552 2553 return platform_driver_register(&sysc_driver); 2554 } 2555 module_init(sysc_init); 2556 2557 static void __exit sysc_exit(void) 2558 { 2559 bus_unregister_notifier(&platform_bus_type, &sysc_nb); 2560 platform_driver_unregister(&sysc_driver); 2561 } 2562 module_exit(sysc_exit); 2563 2564 MODULE_DESCRIPTION("TI sysc interconnect target driver"); 2565 MODULE_LICENSE("GPL v2"); 2566