12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
21a748d2bSBoris BREZILLON /*
31a748d2bSBoris BREZILLON * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
41a748d2bSBoris BREZILLON */
51a748d2bSBoris BREZILLON
61a748d2bSBoris BREZILLON #include <linux/clk-provider.h>
71a748d2bSBoris BREZILLON #include <linux/clkdev.h>
81a748d2bSBoris BREZILLON #include <linux/clk/at91_pmc.h>
91a748d2bSBoris BREZILLON #include <linux/of.h>
101bdf0232SBoris Brezillon #include <linux/mfd/syscon.h>
111bdf0232SBoris Brezillon #include <linux/regmap.h>
121a748d2bSBoris BREZILLON
131a748d2bSBoris BREZILLON #include "pmc.h"
141a748d2bSBoris BREZILLON
151a748d2bSBoris BREZILLON #define PLL_STATUS_MASK(id) (1 << (1 + (id)))
161a748d2bSBoris BREZILLON #define PLL_REG(id) (AT91_CKGR_PLLAR + ((id) * 4))
171a748d2bSBoris BREZILLON #define PLL_DIV_MASK 0xff
181a748d2bSBoris BREZILLON #define PLL_DIV_MAX PLL_DIV_MASK
191a748d2bSBoris BREZILLON #define PLL_DIV(reg) ((reg) & PLL_DIV_MASK)
201a748d2bSBoris BREZILLON #define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \
211a748d2bSBoris BREZILLON (layout)->mul_mask)
223ef9dd2bSBoris BREZILLON #define PLL_MUL_MIN 2
233ef9dd2bSBoris BREZILLON #define PLL_MUL_MASK(layout) ((layout)->mul_mask)
243ef9dd2bSBoris BREZILLON #define PLL_MUL_MAX(layout) (PLL_MUL_MASK(layout) + 1)
251a748d2bSBoris BREZILLON #define PLL_ICPR_SHIFT(id) ((id) * 16)
261a748d2bSBoris BREZILLON #define PLL_ICPR_MASK(id) (0xffff << PLL_ICPR_SHIFT(id))
27078a3eb5SBoris BREZILLON #define PLL_MAX_COUNT 0x3f
281a748d2bSBoris BREZILLON #define PLL_COUNT_SHIFT 8
291a748d2bSBoris BREZILLON #define PLL_OUT_SHIFT 14
301a748d2bSBoris BREZILLON #define PLL_MAX_ID 1
311a748d2bSBoris BREZILLON
321a748d2bSBoris BREZILLON #define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)
331a748d2bSBoris BREZILLON
341a748d2bSBoris BREZILLON struct clk_pll {
351a748d2bSBoris BREZILLON struct clk_hw hw;
361bdf0232SBoris Brezillon struct regmap *regmap;
371a748d2bSBoris BREZILLON u8 id;
381a748d2bSBoris BREZILLON u8 div;
391a748d2bSBoris BREZILLON u8 range;
401a748d2bSBoris BREZILLON u16 mul;
411a748d2bSBoris BREZILLON const struct clk_pll_layout *layout;
421a748d2bSBoris BREZILLON const struct clk_pll_characteristics *characteristics;
43*36971566SClaudiu Beznea struct at91_clk_pms pms;
441a748d2bSBoris BREZILLON };
451a748d2bSBoris BREZILLON
clk_pll_ready(struct regmap * regmap,int id)461bdf0232SBoris Brezillon static inline bool clk_pll_ready(struct regmap *regmap, int id)
471bdf0232SBoris Brezillon {
481bdf0232SBoris Brezillon unsigned int status;
491bdf0232SBoris Brezillon
501bdf0232SBoris Brezillon regmap_read(regmap, AT91_PMC_SR, &status);
511bdf0232SBoris Brezillon
521bdf0232SBoris Brezillon return status & PLL_STATUS_MASK(id) ? 1 : 0;
531bdf0232SBoris Brezillon }
541bdf0232SBoris Brezillon
clk_pll_prepare(struct clk_hw * hw)551a748d2bSBoris BREZILLON static int clk_pll_prepare(struct clk_hw *hw)
561a748d2bSBoris BREZILLON {
571a748d2bSBoris BREZILLON struct clk_pll *pll = to_clk_pll(hw);
581bdf0232SBoris Brezillon struct regmap *regmap = pll->regmap;
591a748d2bSBoris BREZILLON const struct clk_pll_layout *layout = pll->layout;
60e442d234SBoris BREZILLON const struct clk_pll_characteristics *characteristics =
61e442d234SBoris BREZILLON pll->characteristics;
621a748d2bSBoris BREZILLON u8 id = pll->id;
631a748d2bSBoris BREZILLON u32 mask = PLL_STATUS_MASK(id);
641a748d2bSBoris BREZILLON int offset = PLL_REG(id);
651a748d2bSBoris BREZILLON u8 out = 0;
661bdf0232SBoris Brezillon unsigned int pllr;
671bdf0232SBoris Brezillon unsigned int status;
681a748d2bSBoris BREZILLON u8 div;
691a748d2bSBoris BREZILLON u16 mul;
701a748d2bSBoris BREZILLON
711bdf0232SBoris Brezillon regmap_read(regmap, offset, &pllr);
721a748d2bSBoris BREZILLON div = PLL_DIV(pllr);
731a748d2bSBoris BREZILLON mul = PLL_MUL(pllr, layout);
741a748d2bSBoris BREZILLON
751bdf0232SBoris Brezillon regmap_read(regmap, AT91_PMC_SR, &status);
761bdf0232SBoris Brezillon if ((status & mask) &&
771a748d2bSBoris BREZILLON (div == pll->div && mul == pll->mul))
781a748d2bSBoris BREZILLON return 0;
791a748d2bSBoris BREZILLON
801a748d2bSBoris BREZILLON if (characteristics->out)
811a748d2bSBoris BREZILLON out = characteristics->out[pll->range];
821a748d2bSBoris BREZILLON
831bdf0232SBoris Brezillon if (characteristics->icpll)
841bdf0232SBoris Brezillon regmap_update_bits(regmap, AT91_PMC_PLLICPR, PLL_ICPR_MASK(id),
851bdf0232SBoris Brezillon characteristics->icpll[pll->range] << PLL_ICPR_SHIFT(id));
861bdf0232SBoris Brezillon
871bdf0232SBoris Brezillon regmap_update_bits(regmap, offset, layout->pllr_mask,
881bdf0232SBoris Brezillon pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) |
891a748d2bSBoris BREZILLON (out << PLL_OUT_SHIFT) |
901a748d2bSBoris BREZILLON ((pll->mul & layout->mul_mask) << layout->mul_shift));
911a748d2bSBoris BREZILLON
9299a81706SAlexandre Belloni while (!clk_pll_ready(regmap, pll->id))
9399a81706SAlexandre Belloni cpu_relax();
941a748d2bSBoris BREZILLON
951a748d2bSBoris BREZILLON return 0;
961a748d2bSBoris BREZILLON }
971a748d2bSBoris BREZILLON
clk_pll_is_prepared(struct clk_hw * hw)981a748d2bSBoris BREZILLON static int clk_pll_is_prepared(struct clk_hw *hw)
991a748d2bSBoris BREZILLON {
1001a748d2bSBoris BREZILLON struct clk_pll *pll = to_clk_pll(hw);
1011a748d2bSBoris BREZILLON
1021bdf0232SBoris Brezillon return clk_pll_ready(pll->regmap, pll->id);
1031a748d2bSBoris BREZILLON }
1041a748d2bSBoris BREZILLON
clk_pll_unprepare(struct clk_hw * hw)1051a748d2bSBoris BREZILLON static void clk_pll_unprepare(struct clk_hw *hw)
1061a748d2bSBoris BREZILLON {
1071a748d2bSBoris BREZILLON struct clk_pll *pll = to_clk_pll(hw);
1081bdf0232SBoris Brezillon unsigned int mask = pll->layout->pllr_mask;
1091a748d2bSBoris BREZILLON
1101bdf0232SBoris Brezillon regmap_update_bits(pll->regmap, PLL_REG(pll->id), mask, ~mask);
1111a748d2bSBoris BREZILLON }
1121a748d2bSBoris BREZILLON
clk_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1131a748d2bSBoris BREZILLON static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
1141a748d2bSBoris BREZILLON unsigned long parent_rate)
1151a748d2bSBoris BREZILLON {
1161a748d2bSBoris BREZILLON struct clk_pll *pll = to_clk_pll(hw);
11787e2ed33SBoris BREZILLON
1180f5cb0e6SRonald Wahl if (!pll->div || !pll->mul)
1190f5cb0e6SRonald Wahl return 0;
1200f5cb0e6SRonald Wahl
121a982e45dSMarcin Ziemianowicz return (parent_rate / pll->div) * (pll->mul + 1);
1221a748d2bSBoris BREZILLON }
1231a748d2bSBoris BREZILLON
clk_pll_get_best_div_mul(struct clk_pll * pll,unsigned long rate,unsigned long parent_rate,u32 * div,u32 * mul,u32 * index)1241a748d2bSBoris BREZILLON static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
1251a748d2bSBoris BREZILLON unsigned long parent_rate,
1261a748d2bSBoris BREZILLON u32 *div, u32 *mul,
1271a748d2bSBoris BREZILLON u32 *index) {
1281a748d2bSBoris BREZILLON const struct clk_pll_layout *layout = pll->layout;
1291a748d2bSBoris BREZILLON const struct clk_pll_characteristics *characteristics =
1301a748d2bSBoris BREZILLON pll->characteristics;
1313ef9dd2bSBoris BREZILLON unsigned long bestremainder = ULONG_MAX;
1323ef9dd2bSBoris BREZILLON unsigned long maxdiv, mindiv, tmpdiv;
1333ef9dd2bSBoris BREZILLON long bestrate = -ERANGE;
1343ef9dd2bSBoris BREZILLON unsigned long bestdiv;
1353ef9dd2bSBoris BREZILLON unsigned long bestmul;
1363ef9dd2bSBoris BREZILLON int i = 0;
1371a748d2bSBoris BREZILLON
1383ef9dd2bSBoris BREZILLON /* Check if parent_rate is a valid input rate */
1396c7b03e1SBoris Brezillon if (parent_rate < characteristics->input.min)
1401a748d2bSBoris BREZILLON return -ERANGE;
1411a748d2bSBoris BREZILLON
1423ef9dd2bSBoris BREZILLON /*
1433ef9dd2bSBoris BREZILLON * Calculate minimum divider based on the minimum multiplier, the
1443ef9dd2bSBoris BREZILLON * parent_rate and the requested rate.
1453ef9dd2bSBoris BREZILLON * Should always be 2 according to the input and output characteristics
1463ef9dd2bSBoris BREZILLON * of the PLL blocks.
1473ef9dd2bSBoris BREZILLON */
1483ef9dd2bSBoris BREZILLON mindiv = (parent_rate * PLL_MUL_MIN) / rate;
1493ef9dd2bSBoris BREZILLON if (!mindiv)
1503ef9dd2bSBoris BREZILLON mindiv = 1;
1511a748d2bSBoris BREZILLON
1526c7b03e1SBoris Brezillon if (parent_rate > characteristics->input.max) {
1536c7b03e1SBoris Brezillon tmpdiv = DIV_ROUND_UP(parent_rate, characteristics->input.max);
1546c7b03e1SBoris Brezillon if (tmpdiv > PLL_DIV_MAX)
1556c7b03e1SBoris Brezillon return -ERANGE;
1566c7b03e1SBoris Brezillon
1576c7b03e1SBoris Brezillon if (tmpdiv > mindiv)
1586c7b03e1SBoris Brezillon mindiv = tmpdiv;
1596c7b03e1SBoris Brezillon }
1606c7b03e1SBoris Brezillon
1613ef9dd2bSBoris BREZILLON /*
1623ef9dd2bSBoris BREZILLON * Calculate the maximum divider which is limited by PLL register
1633ef9dd2bSBoris BREZILLON * layout (limited by the MUL or DIV field size).
1643ef9dd2bSBoris BREZILLON */
1653ef9dd2bSBoris BREZILLON maxdiv = DIV_ROUND_UP(parent_rate * PLL_MUL_MAX(layout), rate);
1663ef9dd2bSBoris BREZILLON if (maxdiv > PLL_DIV_MAX)
1673ef9dd2bSBoris BREZILLON maxdiv = PLL_DIV_MAX;
1683ef9dd2bSBoris BREZILLON
1693ef9dd2bSBoris BREZILLON /*
1703ef9dd2bSBoris BREZILLON * Iterate over the acceptable divider values to find the best
1713ef9dd2bSBoris BREZILLON * divider/multiplier pair (the one that generates the closest
1723ef9dd2bSBoris BREZILLON * rate to the requested one).
1733ef9dd2bSBoris BREZILLON */
1743ef9dd2bSBoris BREZILLON for (tmpdiv = mindiv; tmpdiv <= maxdiv; tmpdiv++) {
1753ef9dd2bSBoris BREZILLON unsigned long remainder;
1763ef9dd2bSBoris BREZILLON unsigned long tmprate;
1773ef9dd2bSBoris BREZILLON unsigned long tmpmul;
1783ef9dd2bSBoris BREZILLON
1793ef9dd2bSBoris BREZILLON /*
1803ef9dd2bSBoris BREZILLON * Calculate the multiplier associated with the current
1813ef9dd2bSBoris BREZILLON * divider that provide the closest rate to the requested one.
1823ef9dd2bSBoris BREZILLON */
1833ef9dd2bSBoris BREZILLON tmpmul = DIV_ROUND_CLOSEST(rate, parent_rate / tmpdiv);
1843ef9dd2bSBoris BREZILLON tmprate = (parent_rate / tmpdiv) * tmpmul;
1853ef9dd2bSBoris BREZILLON if (tmprate > rate)
1863ef9dd2bSBoris BREZILLON remainder = tmprate - rate;
1873ef9dd2bSBoris BREZILLON else
1883ef9dd2bSBoris BREZILLON remainder = rate - tmprate;
1893ef9dd2bSBoris BREZILLON
1903ef9dd2bSBoris BREZILLON /*
1913ef9dd2bSBoris BREZILLON * Compare the remainder with the best remainder found until
1923ef9dd2bSBoris BREZILLON * now and elect a new best multiplier/divider pair if the
1933ef9dd2bSBoris BREZILLON * current remainder is smaller than the best one.
1943ef9dd2bSBoris BREZILLON */
1953ef9dd2bSBoris BREZILLON if (remainder < bestremainder) {
1963ef9dd2bSBoris BREZILLON bestremainder = remainder;
1973ef9dd2bSBoris BREZILLON bestdiv = tmpdiv;
1983ef9dd2bSBoris BREZILLON bestmul = tmpmul;
1993ef9dd2bSBoris BREZILLON bestrate = tmprate;
2003ef9dd2bSBoris BREZILLON }
2013ef9dd2bSBoris BREZILLON
2023ef9dd2bSBoris BREZILLON /*
2033ef9dd2bSBoris BREZILLON * We've found a perfect match!
2043ef9dd2bSBoris BREZILLON * Stop searching now and use this multiplier/divider pair.
2053ef9dd2bSBoris BREZILLON */
2063ef9dd2bSBoris BREZILLON if (!remainder)
2073ef9dd2bSBoris BREZILLON break;
2083ef9dd2bSBoris BREZILLON }
2093ef9dd2bSBoris BREZILLON
2103ef9dd2bSBoris BREZILLON /* We haven't found any multiplier/divider pair => return -ERANGE */
2113ef9dd2bSBoris BREZILLON if (bestrate < 0)
2123ef9dd2bSBoris BREZILLON return bestrate;
2133ef9dd2bSBoris BREZILLON
2143ef9dd2bSBoris BREZILLON /* Check if bestrate is a valid output rate */
2151a748d2bSBoris BREZILLON for (i = 0; i < characteristics->num_output; i++) {
2163ef9dd2bSBoris BREZILLON if (bestrate >= characteristics->output[i].min &&
2173ef9dd2bSBoris BREZILLON bestrate <= characteristics->output[i].max)
2181a748d2bSBoris BREZILLON break;
2191a748d2bSBoris BREZILLON }
2201a748d2bSBoris BREZILLON
2211a748d2bSBoris BREZILLON if (i >= characteristics->num_output)
2221a748d2bSBoris BREZILLON return -ERANGE;
2231a748d2bSBoris BREZILLON
2241a748d2bSBoris BREZILLON if (div)
2251a748d2bSBoris BREZILLON *div = bestdiv;
2261a748d2bSBoris BREZILLON if (mul)
2273ef9dd2bSBoris BREZILLON *mul = bestmul - 1;
2281a748d2bSBoris BREZILLON if (index)
2291a748d2bSBoris BREZILLON *index = i;
2301a748d2bSBoris BREZILLON
2313ef9dd2bSBoris BREZILLON return bestrate;
2321a748d2bSBoris BREZILLON }
2331a748d2bSBoris BREZILLON
clk_pll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)2341a748d2bSBoris BREZILLON static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
2351a748d2bSBoris BREZILLON unsigned long *parent_rate)
2361a748d2bSBoris BREZILLON {
2371a748d2bSBoris BREZILLON struct clk_pll *pll = to_clk_pll(hw);
2381a748d2bSBoris BREZILLON
2391a748d2bSBoris BREZILLON return clk_pll_get_best_div_mul(pll, rate, *parent_rate,
2401a748d2bSBoris BREZILLON NULL, NULL, NULL);
2411a748d2bSBoris BREZILLON }
2421a748d2bSBoris BREZILLON
clk_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2431a748d2bSBoris BREZILLON static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
2441a748d2bSBoris BREZILLON unsigned long parent_rate)
2451a748d2bSBoris BREZILLON {
2461a748d2bSBoris BREZILLON struct clk_pll *pll = to_clk_pll(hw);
2471a748d2bSBoris BREZILLON long ret;
2481a748d2bSBoris BREZILLON u32 div;
2491a748d2bSBoris BREZILLON u32 mul;
2501a748d2bSBoris BREZILLON u32 index;
2511a748d2bSBoris BREZILLON
2521a748d2bSBoris BREZILLON ret = clk_pll_get_best_div_mul(pll, rate, parent_rate,
2531a748d2bSBoris BREZILLON &div, &mul, &index);
2541a748d2bSBoris BREZILLON if (ret < 0)
2551a748d2bSBoris BREZILLON return ret;
2561a748d2bSBoris BREZILLON
2571a748d2bSBoris BREZILLON pll->range = index;
2581a748d2bSBoris BREZILLON pll->div = div;
2591a748d2bSBoris BREZILLON pll->mul = mul;
2601a748d2bSBoris BREZILLON
2611a748d2bSBoris BREZILLON return 0;
2621a748d2bSBoris BREZILLON }
2631a748d2bSBoris BREZILLON
clk_pll_save_context(struct clk_hw * hw)264*36971566SClaudiu Beznea static int clk_pll_save_context(struct clk_hw *hw)
265*36971566SClaudiu Beznea {
266*36971566SClaudiu Beznea struct clk_pll *pll = to_clk_pll(hw);
267*36971566SClaudiu Beznea struct clk_hw *parent_hw = clk_hw_get_parent(hw);
268*36971566SClaudiu Beznea
269*36971566SClaudiu Beznea pll->pms.parent_rate = clk_hw_get_rate(parent_hw);
270*36971566SClaudiu Beznea pll->pms.rate = clk_pll_recalc_rate(&pll->hw, pll->pms.parent_rate);
271*36971566SClaudiu Beznea pll->pms.status = clk_pll_ready(pll->regmap, PLL_REG(pll->id));
272*36971566SClaudiu Beznea
273*36971566SClaudiu Beznea return 0;
274*36971566SClaudiu Beznea }
275*36971566SClaudiu Beznea
clk_pll_restore_context(struct clk_hw * hw)276*36971566SClaudiu Beznea static void clk_pll_restore_context(struct clk_hw *hw)
277*36971566SClaudiu Beznea {
278*36971566SClaudiu Beznea struct clk_pll *pll = to_clk_pll(hw);
279*36971566SClaudiu Beznea unsigned long calc_rate;
280*36971566SClaudiu Beznea unsigned int pllr, pllr_out, pllr_count;
281*36971566SClaudiu Beznea u8 out = 0;
282*36971566SClaudiu Beznea
283*36971566SClaudiu Beznea if (pll->characteristics->out)
284*36971566SClaudiu Beznea out = pll->characteristics->out[pll->range];
285*36971566SClaudiu Beznea
286*36971566SClaudiu Beznea regmap_read(pll->regmap, PLL_REG(pll->id), &pllr);
287*36971566SClaudiu Beznea
288*36971566SClaudiu Beznea calc_rate = (pll->pms.parent_rate / PLL_DIV(pllr)) *
289*36971566SClaudiu Beznea (PLL_MUL(pllr, pll->layout) + 1);
290*36971566SClaudiu Beznea pllr_count = (pllr >> PLL_COUNT_SHIFT) & PLL_MAX_COUNT;
291*36971566SClaudiu Beznea pllr_out = (pllr >> PLL_OUT_SHIFT) & out;
292*36971566SClaudiu Beznea
293*36971566SClaudiu Beznea if (pll->pms.rate != calc_rate ||
294*36971566SClaudiu Beznea pll->pms.status != clk_pll_ready(pll->regmap, PLL_REG(pll->id)) ||
295*36971566SClaudiu Beznea pllr_count != PLL_MAX_COUNT ||
296*36971566SClaudiu Beznea (out && pllr_out != out))
297*36971566SClaudiu Beznea pr_warn("PLLAR was not configured properly by firmware\n");
298*36971566SClaudiu Beznea }
299*36971566SClaudiu Beznea
3001a748d2bSBoris BREZILLON static const struct clk_ops pll_ops = {
3011a748d2bSBoris BREZILLON .prepare = clk_pll_prepare,
3021a748d2bSBoris BREZILLON .unprepare = clk_pll_unprepare,
3031a748d2bSBoris BREZILLON .is_prepared = clk_pll_is_prepared,
3041a748d2bSBoris BREZILLON .recalc_rate = clk_pll_recalc_rate,
3051a748d2bSBoris BREZILLON .round_rate = clk_pll_round_rate,
3061a748d2bSBoris BREZILLON .set_rate = clk_pll_set_rate,
307*36971566SClaudiu Beznea .save_context = clk_pll_save_context,
308*36971566SClaudiu Beznea .restore_context = clk_pll_restore_context,
3091a748d2bSBoris BREZILLON };
3101a748d2bSBoris BREZILLON
311b2e39dc0SAlexandre Belloni struct clk_hw * __init
at91_clk_register_pll(struct regmap * regmap,const char * name,const char * parent_name,u8 id,const struct clk_pll_layout * layout,const struct clk_pll_characteristics * characteristics)31299a81706SAlexandre Belloni at91_clk_register_pll(struct regmap *regmap, const char *name,
3131a748d2bSBoris BREZILLON const char *parent_name, u8 id,
3141a748d2bSBoris BREZILLON const struct clk_pll_layout *layout,
3151a748d2bSBoris BREZILLON const struct clk_pll_characteristics *characteristics)
3161a748d2bSBoris BREZILLON {
3171a748d2bSBoris BREZILLON struct clk_pll *pll;
318f5644f10SStephen Boyd struct clk_hw *hw;
3191a748d2bSBoris BREZILLON struct clk_init_data init;
3201a748d2bSBoris BREZILLON int offset = PLL_REG(id);
3211bdf0232SBoris Brezillon unsigned int pllr;
322f5644f10SStephen Boyd int ret;
3231a748d2bSBoris BREZILLON
3241a748d2bSBoris BREZILLON if (id > PLL_MAX_ID)
3251a748d2bSBoris BREZILLON return ERR_PTR(-EINVAL);
3261a748d2bSBoris BREZILLON
3271a748d2bSBoris BREZILLON pll = kzalloc(sizeof(*pll), GFP_KERNEL);
3281a748d2bSBoris BREZILLON if (!pll)
3291a748d2bSBoris BREZILLON return ERR_PTR(-ENOMEM);
3301a748d2bSBoris BREZILLON
3311a748d2bSBoris BREZILLON init.name = name;
3321a748d2bSBoris BREZILLON init.ops = &pll_ops;
3331a748d2bSBoris BREZILLON init.parent_names = &parent_name;
3341a748d2bSBoris BREZILLON init.num_parents = 1;
3351a748d2bSBoris BREZILLON init.flags = CLK_SET_RATE_GATE;
3361a748d2bSBoris BREZILLON
3371a748d2bSBoris BREZILLON pll->id = id;
3381a748d2bSBoris BREZILLON pll->hw.init = &init;
3391a748d2bSBoris BREZILLON pll->layout = layout;
3401a748d2bSBoris BREZILLON pll->characteristics = characteristics;
3411bdf0232SBoris Brezillon pll->regmap = regmap;
3421bdf0232SBoris Brezillon regmap_read(regmap, offset, &pllr);
3431bdf0232SBoris Brezillon pll->div = PLL_DIV(pllr);
3441bdf0232SBoris Brezillon pll->mul = PLL_MUL(pllr, layout);
3451a748d2bSBoris BREZILLON
346f5644f10SStephen Boyd hw = &pll->hw;
347f5644f10SStephen Boyd ret = clk_hw_register(NULL, &pll->hw);
348f5644f10SStephen Boyd if (ret) {
3491a748d2bSBoris BREZILLON kfree(pll);
350f5644f10SStephen Boyd hw = ERR_PTR(ret);
351c76a024eSDavid Dueck }
3521a748d2bSBoris BREZILLON
353f5644f10SStephen Boyd return hw;
3541a748d2bSBoris BREZILLON }
3551a748d2bSBoris BREZILLON
3561a748d2bSBoris BREZILLON
357b2e39dc0SAlexandre Belloni const struct clk_pll_layout at91rm9200_pll_layout = {
3581a748d2bSBoris BREZILLON .pllr_mask = 0x7FFFFFF,
3591a748d2bSBoris BREZILLON .mul_shift = 16,
3601a748d2bSBoris BREZILLON .mul_mask = 0x7FF,
3611a748d2bSBoris BREZILLON };
3621a748d2bSBoris BREZILLON
363b2e39dc0SAlexandre Belloni const struct clk_pll_layout at91sam9g45_pll_layout = {
3641a748d2bSBoris BREZILLON .pllr_mask = 0xFFFFFF,
3651a748d2bSBoris BREZILLON .mul_shift = 16,
3661a748d2bSBoris BREZILLON .mul_mask = 0xFF,
3671a748d2bSBoris BREZILLON };
3681a748d2bSBoris BREZILLON
369b2e39dc0SAlexandre Belloni const struct clk_pll_layout at91sam9g20_pllb_layout = {
3701a748d2bSBoris BREZILLON .pllr_mask = 0x3FFFFF,
3711a748d2bSBoris BREZILLON .mul_shift = 16,
3721a748d2bSBoris BREZILLON .mul_mask = 0x3F,
3731a748d2bSBoris BREZILLON };
3741a748d2bSBoris BREZILLON
375b2e39dc0SAlexandre Belloni const struct clk_pll_layout sama5d3_pll_layout = {
3761a748d2bSBoris BREZILLON .pllr_mask = 0x1FFFFFF,
3771a748d2bSBoris BREZILLON .mul_shift = 18,
3781a748d2bSBoris BREZILLON .mul_mask = 0x7F,
3791a748d2bSBoris BREZILLON };
380