1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Sam Shih <sam.shih@mediatek.com> 5 * Author: Wenzhen Yu <wenzhen.yu@mediatek.com> 6 * Author: Jianhui Zhao <zhaojh329@gmail.com> 7 */ 8 9 10 #include <linux/clk-provider.h> 11 #include <linux/of.h> 12 #include <linux/of_address.h> 13 #include <linux/of_device.h> 14 #include <linux/platform_device.h> 15 #include "clk-mtk.h" 16 #include "clk-gate.h" 17 #include "clk-mux.h" 18 19 #include <dt-bindings/clock/mediatek,mt7981-clk.h> 20 #include <linux/clk.h> 21 22 static DEFINE_SPINLOCK(mt7981_clk_lock); 23 24 static const struct mtk_fixed_factor top_divs[] = { 25 FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1), 26 FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1), 27 FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2), 28 FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3), 29 FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2), 30 FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4), 31 FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8), 32 FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16), 33 FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1), 34 FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2), 35 FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3), 36 FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15), 37 FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4), 38 FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6), 39 FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12), 40 FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8), 41 FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1), 42 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2), 43 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), 44 FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1), 45 FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4), 46 FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5), 47 FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10), 48 FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20), 49 FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8), 50 FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16), 51 FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32), 52 FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1), 53 FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2), 54 FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4), 55 FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8), 56 FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16), 57 FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6), 58 FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1), 59 FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1), 60 FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2), 61 FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250), 62 FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220), 63 FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1), 64 FACTOR(CLK_TOP_FAUD, "faud", "aud_sel", 1, 1), 65 FACTOR(CLK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1), 66 FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1), 67 FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1), 68 FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1), 69 FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1), 70 FACTOR(CLK_TOP_SPI, "spi", "spi_sel", 1, 1), 71 FACTOR(CLK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1), 72 FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1), 73 FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1), 74 FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1), 75 FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1), 76 FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1), 77 FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1), 78 FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1), 79 FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1), 80 FACTOR(CLK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1), 81 FACTOR(CLK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1), 82 FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1), 83 FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1), 84 FACTOR(CLK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1), 85 FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1), 86 FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1), 87 FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1), 88 FACTOR(CLK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1), 89 FACTOR(CLK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1), 90 FACTOR(CLK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1), 91 FACTOR(CLK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1), 92 FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1), 93 FACTOR(CLK_TOP_AUD, "aud", "faud", 1, 1), 94 FACTOR(CLK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1), 95 FACTOR(CLK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1), 96 FACTOR(CLK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1), 97 FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1), 98 FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1), 99 FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1), 100 FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1), 101 }; 102 103 static const char * const nfi1x_parents[] __initconst = { 104 "cb_cksq_40m", 105 "cb_mm_d4", 106 "net1_d8_d2", 107 "cb_net2_d6", 108 "cb_m_d4", 109 "cb_mm_d8", 110 "net1_d8_d4", 111 "cb_m_d8" 112 }; 113 114 static const char * const spinfi_parents[] __initconst = { 115 "cksq_40m_d2", 116 "cb_cksq_40m", 117 "net1_d5_d4", 118 "cb_m_d4", 119 "cb_mm_d8", 120 "net1_d8_d4", 121 "mm_d6_d2", 122 "cb_m_d8" 123 }; 124 125 static const char * const spi_parents[] __initconst = { 126 "cb_cksq_40m", 127 "cb_m_d2", 128 "cb_mm_d4", 129 "net1_d8_d2", 130 "cb_net2_d6", 131 "net1_d5_d4", 132 "cb_m_d4", 133 "net1_d8_d4" 134 }; 135 136 static const char * const uart_parents[] __initconst = { 137 "cb_cksq_40m", 138 "cb_m_d8", 139 "m_d8_d2" 140 }; 141 142 static const char * const pwm_parents[] __initconst = { 143 "cb_cksq_40m", 144 "net1_d8_d2", 145 "net1_d5_d4", 146 "cb_m_d4", 147 "m_d8_d2", 148 "cb_rtc_32k" 149 }; 150 151 static const char * const i2c_parents[] __initconst = { 152 "cb_cksq_40m", 153 "net1_d5_d4", 154 "cb_m_d4", 155 "net1_d8_d4" 156 }; 157 158 static const char * const pextp_tl_ck_parents[] __initconst = { 159 "cb_cksq_40m", 160 "net1_d5_d4", 161 "cb_m_d4", 162 "cb_rtc_32k" 163 }; 164 165 static const char * const emmc_208m_parents[] __initconst = { 166 "cb_cksq_40m", 167 "cb_m_d2", 168 "cb_net2_d4", 169 "cb_apll2_196m", 170 "cb_mm_d4", 171 "net1_d8_d2", 172 "cb_mm_d6" 173 }; 174 175 static const char * const emmc_400m_parents[] __initconst = { 176 "cb_cksq_40m", 177 "cb_net2_d2", 178 "cb_mm_d2", 179 "cb_net2_d2" 180 }; 181 182 static const char * const csw_f26m_parents[] __initconst = { 183 "cksq_40m_d2", 184 "m_d8_d2" 185 }; 186 187 static const char * const dramc_md32_parents[] __initconst = { 188 "cb_cksq_40m", 189 "cb_m_d2", 190 "cb_wedmcu_208m" 191 }; 192 193 static const char * const sysaxi_parents[] __initconst = { 194 "cb_cksq_40m", 195 "net1_d8_d2" 196 }; 197 198 static const char * const sysapb_parents[] __initconst = { 199 "cb_cksq_40m", 200 "m_d3_d2" 201 }; 202 203 static const char * const arm_db_main_parents[] __initconst = { 204 "cb_cksq_40m", 205 "cb_net2_d6" 206 }; 207 208 static const char * const ap2cnn_host_parents[] __initconst = { 209 "cb_cksq_40m", 210 "net1_d8_d4" 211 }; 212 213 static const char * const netsys_parents[] __initconst = { 214 "cb_cksq_40m", 215 "cb_mm_d2" 216 }; 217 218 static const char * const netsys_500m_parents[] __initconst = { 219 "cb_cksq_40m", 220 "cb_net1_d5" 221 }; 222 223 static const char * const netsys_mcu_parents[] __initconst = { 224 "cb_cksq_40m", 225 "cb_mm_720m", 226 "cb_net1_d4", 227 "cb_net1_d5", 228 "cb_m_416m" 229 }; 230 231 static const char * const netsys_2x_parents[] __initconst = { 232 "cb_cksq_40m", 233 "cb_net2_800m", 234 "cb_mm_720m" 235 }; 236 237 static const char * const sgm_325m_parents[] __initconst = { 238 "cb_cksq_40m", 239 "cb_sgm_325m" 240 }; 241 242 static const char * const sgm_reg_parents[] __initconst = { 243 "cb_cksq_40m", 244 "cb_net2_d4" 245 }; 246 247 static const char * const eip97b_parents[] __initconst = { 248 "cb_cksq_40m", 249 "cb_net1_d5", 250 "cb_m_416m", 251 "cb_mm_d2", 252 "net1_d5_d2" 253 }; 254 255 static const char * const aud_parents[] __initconst = { 256 "cb_cksq_40m", 257 "cb_apll2_196m" 258 }; 259 260 static const char * const a1sys_parents[] __initconst = { 261 "cb_cksq_40m", 262 "apll2_d4" 263 }; 264 265 static const char * const aud_l_parents[] __initconst = { 266 "cb_cksq_40m", 267 "cb_apll2_196m", 268 "m_d8_d2" 269 }; 270 271 static const char * const a_tuner_parents[] __initconst = { 272 "cb_cksq_40m", 273 "apll2_d4", 274 "m_d8_d2" 275 }; 276 277 static const char * const u2u3_parents[] __initconst = { 278 "cb_cksq_40m", 279 "m_d8_d2" 280 }; 281 282 static const char * const u2u3_sys_parents[] __initconst = { 283 "cb_cksq_40m", 284 "net1_d5_d4" 285 }; 286 287 static const char * const usb_frmcnt_parents[] __initconst = { 288 "cb_cksq_40m", 289 "cb_mm_d3_d5" 290 }; 291 292 static const struct mtk_mux top_muxes[] = { 293 /* CLK_CFG_0 */ 294 MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 295 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0), 296 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 297 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1), 298 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 299 0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2), 300 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 301 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3), 302 /* CLK_CFG_1 */ 303 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 304 0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4), 305 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 306 0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5), 307 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 308 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6), 309 MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", 310 pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31, 311 0x1C0, 7), 312 /* CLK_CFG_2 */ 313 MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel", 314 emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7, 315 0x1C0, 8), 316 MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", 317 emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15, 318 0x1C0, 9), 319 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel", 320 csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23, 321 0x1C0, 10, 322 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 323 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", 324 csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1, 325 31, 0x1C0, 11, 326 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 327 /* CLK_CFG_3 */ 328 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", 329 dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2, 330 7, 0x1C0, 12, 331 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 332 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", 333 sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15, 334 0x1C0, 13, 335 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 336 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", 337 sysapb_parents, 0x030, 0x034, 0x038, 16, 1, 338 23, 0x1C0, 14, 339 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 340 MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", 341 arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31, 342 0x1C0, 15), 343 /* CLK_CFG_4 */ 344 MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", 345 ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7, 346 0x1C0, 16), 347 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 348 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17), 349 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", 350 netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23, 351 0x1C0, 18), 352 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", 353 netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31, 354 0x1C0, 19), 355 /* CLK_CFG_5 */ 356 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", 357 netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7, 358 0x1C0, 20), 359 MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", 360 sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, 361 0x1C0, 21), 362 MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 363 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22), 364 MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, 365 0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23), 366 /* CLK_CFG_6 */ 367 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", 368 csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1, 369 7, 0x1C0, 24), 370 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x060, 371 0x064, 0x068, 8, 1, 15, 0x1C0, 25), 372 MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 373 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26), 374 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 375 0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27), 376 /* CLK_CFG_7 */ 377 MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", 378 a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7, 379 0x1C0, 28), 380 MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x070, 381 0x074, 0x078, 8, 1, 15, 0x1C0, 29), 382 MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", 383 u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23, 384 0x1C0, 30), 385 MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", 386 u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31, 387 0x1C4, 0), 388 /* CLK_CFG_8 */ 389 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", 390 usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7, 391 0x1C4, 1), 392 }; 393 394 static struct mtk_composite top_aud_divs[] = { 395 DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud", 396 0x0420, 0, 0x0420, 8, 8), 397 }; 398 399 static const struct mtk_clk_desc topck_desc = { 400 .factor_clks = top_divs, 401 .num_factor_clks = ARRAY_SIZE(top_divs), 402 .mux_clks = top_muxes, 403 .num_mux_clks = ARRAY_SIZE(top_muxes), 404 .composite_clks = top_aud_divs, 405 .num_composite_clks = ARRAY_SIZE(top_aud_divs), 406 .clk_lock = &mt7981_clk_lock, 407 }; 408 409 static const struct of_device_id of_match_clk_mt7981_topckgen[] = { 410 { .compatible = "mediatek,mt7981-topckgen", .data = &topck_desc }, 411 { /* sentinel */ } 412 }; 413 414 static struct platform_driver clk_mt7981_topckgen_drv = { 415 .probe = mtk_clk_simple_probe, 416 .remove = mtk_clk_simple_remove, 417 .driver = { 418 .name = "clk-mt7981-topckgen", 419 .of_match_table = of_match_clk_mt7981_topckgen, 420 }, 421 }; 422 module_platform_driver(clk_mt7981_topckgen_drv); 423