1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2020 MediaTek Inc.
4  * Copyright (c) 2020 BayLibre, SAS
5  * Author: James Liao <jamesjj.liao@mediatek.com>
6  *         Fabien Parent <fparent@baylibre.com>
7  */
8 
9 #include <linux/clk-provider.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 
15 #include "clk-mtk.h"
16 #include "clk-gate.h"
17 
18 #include <dt-bindings/clock/mt8167-clk.h>
19 
20 static const struct mtk_gate_regs mfg_cg_regs = {
21 	.set_ofs = 0x4,
22 	.clr_ofs = 0x8,
23 	.sta_ofs = 0x0,
24 };
25 
26 #define GATE_MFG(_id, _name, _parent, _shift) {		\
27 		.id = _id,				\
28 		.name = _name,				\
29 		.parent_name = _parent,			\
30 		.regs = &mfg_cg_regs,			\
31 		.shift = _shift,			\
32 		.ops = &mtk_clk_gate_ops_setclr,	\
33 	}
34 
35 static const struct mtk_gate mfg_clks[] __initconst = {
36 	GATE_MFG(CLK_MFG_BAXI, "mfg_baxi", "ahb_infra_sel", 0),
37 	GATE_MFG(CLK_MFG_BMEM, "mfg_bmem", "gfmux_emi1x_sel", 1),
38 	GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_mm", 2),
39 	GATE_MFG(CLK_MFG_B26M, "mfg_b26m", "clk26m_ck", 3),
40 };
41 
42 static void __init mtk_mfgcfg_init(struct device_node *node)
43 {
44 	struct clk_hw_onecell_data *clk_data;
45 	int r;
46 
47 	clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
48 
49 	mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks), clk_data);
50 
51 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
52 
53 	if (r)
54 		pr_err("%s(): could not register clock provider: %d\n",
55 			__func__, r);
56 
57 }
58 CLK_OF_DECLARE(mtk_mfgcfg, "mediatek,mt8167-mfgcfg", mtk_mfgcfg_init);
59