1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (c) 2018 MediaTek Inc. 4 // Author: Weiyi Lu <weiyi.lu@mediatek.com> 5 6 #include <linux/delay.h> 7 #include <linux/mfd/syscon.h> 8 #include <linux/of.h> 9 #include <linux/of_address.h> 10 #include <linux/of_device.h> 11 #include <linux/platform_device.h> 12 #include <linux/slab.h> 13 14 #include "clk-mtk.h" 15 #include "clk-mux.h" 16 #include "clk-gate.h" 17 18 #include <dt-bindings/clock/mt8183-clk.h> 19 20 /* Infra global controller reset set register */ 21 #define INFRA_RST0_SET_OFFSET 0x120 22 23 static DEFINE_SPINLOCK(mt8183_clk_lock); 24 25 static const struct mtk_fixed_clk top_fixed_clks[] = { 26 FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000), 27 FIXED_CLK(CLK_TOP_ULPOSC, "osc", NULL, 250000), 28 FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000), 29 }; 30 31 static const struct mtk_fixed_factor top_early_divs[] = { 32 FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2), 33 }; 34 35 static const struct mtk_fixed_factor top_divs[] = { 36 FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 37 2), 38 FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 39 1), 40 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 41 2), 42 FACTOR(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1, 43 2), 44 FACTOR(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1, 45 4), 46 FACTOR(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1, 47 8), 48 FACTOR(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1, 49 16), 50 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 51 3), 52 FACTOR(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1, 53 2), 54 FACTOR(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1, 55 4), 56 FACTOR(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1, 57 8), 58 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 59 5), 60 FACTOR(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1, 61 2), 62 FACTOR(CLK_TOP_SYSPLL_D5_D4, "syspll_d5_d4", "syspll_d5", 1, 63 4), 64 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 65 7), 66 FACTOR(CLK_TOP_SYSPLL_D7_D2, "syspll_d7_d2", "syspll_d7", 1, 67 2), 68 FACTOR(CLK_TOP_SYSPLL_D7_D4, "syspll_d7_d4", "syspll_d7", 1, 69 4), 70 FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 71 1), 72 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 73 2), 74 FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 75 2), 76 FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 77 4), 78 FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 79 8), 80 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 81 3), 82 FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 83 2), 84 FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 85 4), 86 FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 87 8), 88 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 89 5), 90 FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 91 2), 92 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 93 4), 94 FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 95 8), 96 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 97 7), 98 FACTOR(CLK_TOP_UNIVP_192M_CK, "univ_192m_ck", "univpll_192m", 1, 99 1), 100 FACTOR(CLK_TOP_UNIVP_192M_D2, "univ_192m_d2", "univ_192m_ck", 1, 101 2), 102 FACTOR(CLK_TOP_UNIVP_192M_D4, "univ_192m_d4", "univ_192m_ck", 1, 103 4), 104 FACTOR(CLK_TOP_UNIVP_192M_D8, "univ_192m_d8", "univ_192m_ck", 1, 105 8), 106 FACTOR(CLK_TOP_UNIVP_192M_D16, "univ_192m_d16", "univ_192m_ck", 1, 107 16), 108 FACTOR(CLK_TOP_UNIVP_192M_D32, "univ_192m_d32", "univ_192m_ck", 1, 109 32), 110 FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 111 1), 112 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 113 2), 114 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 115 4), 116 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 117 8), 118 FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 119 1), 120 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 121 2), 122 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 123 4), 124 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 125 8), 126 FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 127 1), 128 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 129 2), 130 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 131 4), 132 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 133 8), 134 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 135 16), 136 FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 137 1), 138 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 139 4), 140 FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 141 2), 142 FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 143 4), 144 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 145 5), 146 FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 147 2), 148 FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 149 4), 150 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 151 6), 152 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 153 7), 154 FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 155 1), 156 FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 157 1), 158 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 159 2), 160 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 161 4), 162 FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 163 8), 164 FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 165 16), 166 FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 167 1), 168 FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 169 2), 170 FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 171 4), 172 FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 173 8), 174 FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 175 16), 176 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 177 2), 178 FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 179 16), 180 }; 181 182 static const char * const axi_parents[] = { 183 "clk26m", 184 "syspll_d2_d4", 185 "syspll_d7", 186 "osc_d4" 187 }; 188 189 static const char * const mm_parents[] = { 190 "clk26m", 191 "mmpll_d7", 192 "syspll_d3", 193 "univpll_d2_d2", 194 "syspll_d2_d2", 195 "syspll_d3_d2" 196 }; 197 198 static const char * const img_parents[] = { 199 "clk26m", 200 "mmpll_d6", 201 "univpll_d3", 202 "syspll_d3", 203 "univpll_d2_d2", 204 "syspll_d2_d2", 205 "univpll_d3_d2", 206 "syspll_d3_d2" 207 }; 208 209 static const char * const cam_parents[] = { 210 "clk26m", 211 "syspll_d2", 212 "mmpll_d6", 213 "syspll_d3", 214 "mmpll_d7", 215 "univpll_d3", 216 "univpll_d2_d2", 217 "syspll_d2_d2", 218 "syspll_d3_d2", 219 "univpll_d3_d2" 220 }; 221 222 static const char * const dsp_parents[] = { 223 "clk26m", 224 "mmpll_d6", 225 "mmpll_d7", 226 "univpll_d3", 227 "syspll_d3", 228 "univpll_d2_d2", 229 "syspll_d2_d2", 230 "univpll_d3_d2", 231 "syspll_d3_d2" 232 }; 233 234 static const char * const dsp1_parents[] = { 235 "clk26m", 236 "mmpll_d6", 237 "mmpll_d7", 238 "univpll_d3", 239 "syspll_d3", 240 "univpll_d2_d2", 241 "syspll_d2_d2", 242 "univpll_d3_d2", 243 "syspll_d3_d2" 244 }; 245 246 static const char * const dsp2_parents[] = { 247 "clk26m", 248 "mmpll_d6", 249 "mmpll_d7", 250 "univpll_d3", 251 "syspll_d3", 252 "univpll_d2_d2", 253 "syspll_d2_d2", 254 "univpll_d3_d2", 255 "syspll_d3_d2" 256 }; 257 258 static const char * const ipu_if_parents[] = { 259 "clk26m", 260 "mmpll_d6", 261 "mmpll_d7", 262 "univpll_d3", 263 "syspll_d3", 264 "univpll_d2_d2", 265 "syspll_d2_d2", 266 "univpll_d3_d2", 267 "syspll_d3_d2" 268 }; 269 270 static const char * const mfg_parents[] = { 271 "clk26m", 272 "mfgpll_ck", 273 "univpll_d3", 274 "syspll_d3" 275 }; 276 277 static const char * const f52m_mfg_parents[] = { 278 "clk26m", 279 "univpll_d3_d2", 280 "univpll_d3_d4", 281 "univpll_d3_d8" 282 }; 283 284 static const char * const camtg_parents[] = { 285 "clk26m", 286 "univ_192m_d8", 287 "univpll_d3_d8", 288 "univ_192m_d4", 289 "univpll_d3_d16", 290 "csw_f26m_ck_d2", 291 "univ_192m_d16", 292 "univ_192m_d32" 293 }; 294 295 static const char * const camtg2_parents[] = { 296 "clk26m", 297 "univ_192m_d8", 298 "univpll_d3_d8", 299 "univ_192m_d4", 300 "univpll_d3_d16", 301 "csw_f26m_ck_d2", 302 "univ_192m_d16", 303 "univ_192m_d32" 304 }; 305 306 static const char * const camtg3_parents[] = { 307 "clk26m", 308 "univ_192m_d8", 309 "univpll_d3_d8", 310 "univ_192m_d4", 311 "univpll_d3_d16", 312 "csw_f26m_ck_d2", 313 "univ_192m_d16", 314 "univ_192m_d32" 315 }; 316 317 static const char * const camtg4_parents[] = { 318 "clk26m", 319 "univ_192m_d8", 320 "univpll_d3_d8", 321 "univ_192m_d4", 322 "univpll_d3_d16", 323 "csw_f26m_ck_d2", 324 "univ_192m_d16", 325 "univ_192m_d32" 326 }; 327 328 static const char * const uart_parents[] = { 329 "clk26m", 330 "univpll_d3_d8" 331 }; 332 333 static const char * const spi_parents[] = { 334 "clk26m", 335 "syspll_d5_d2", 336 "syspll_d3_d4", 337 "msdcpll_d4" 338 }; 339 340 static const char * const msdc50_hclk_parents[] = { 341 "clk26m", 342 "syspll_d2_d2", 343 "syspll_d3_d2" 344 }; 345 346 static const char * const msdc50_0_parents[] = { 347 "clk26m", 348 "msdcpll_ck", 349 "msdcpll_d2", 350 "univpll_d2_d4", 351 "syspll_d3_d2", 352 "univpll_d2_d2" 353 }; 354 355 static const char * const msdc30_1_parents[] = { 356 "clk26m", 357 "univpll_d3_d2", 358 "syspll_d3_d2", 359 "syspll_d7", 360 "msdcpll_d2" 361 }; 362 363 static const char * const msdc30_2_parents[] = { 364 "clk26m", 365 "univpll_d3_d2", 366 "syspll_d3_d2", 367 "syspll_d7", 368 "msdcpll_d2" 369 }; 370 371 static const char * const audio_parents[] = { 372 "clk26m", 373 "syspll_d5_d4", 374 "syspll_d7_d4", 375 "syspll_d2_d16" 376 }; 377 378 static const char * const aud_intbus_parents[] = { 379 "clk26m", 380 "syspll_d2_d4", 381 "syspll_d7_d2" 382 }; 383 384 static const char * const pmicspi_parents[] = { 385 "clk26m", 386 "syspll_d2_d8", 387 "osc_d8" 388 }; 389 390 static const char * const fpwrap_ulposc_parents[] = { 391 "clk26m", 392 "osc_d16", 393 "osc_d4", 394 "osc_d8" 395 }; 396 397 static const char * const atb_parents[] = { 398 "clk26m", 399 "syspll_d2_d2", 400 "syspll_d5" 401 }; 402 403 static const char * const dpi0_parents[] = { 404 "clk26m", 405 "tvdpll_d2", 406 "tvdpll_d4", 407 "tvdpll_d8", 408 "tvdpll_d16", 409 "univpll_d5_d2", 410 "univpll_d3_d4", 411 "syspll_d3_d4", 412 "univpll_d3_d8" 413 }; 414 415 static const char * const scam_parents[] = { 416 "clk26m", 417 "syspll_d5_d2" 418 }; 419 420 static const char * const disppwm_parents[] = { 421 "clk26m", 422 "univpll_d3_d4", 423 "osc_d2", 424 "osc_d4", 425 "osc_d16" 426 }; 427 428 static const char * const usb_top_parents[] = { 429 "clk26m", 430 "univpll_d5_d4", 431 "univpll_d3_d4", 432 "univpll_d5_d2" 433 }; 434 435 436 static const char * const ssusb_top_xhci_parents[] = { 437 "clk26m", 438 "univpll_d5_d4", 439 "univpll_d3_d4", 440 "univpll_d5_d2" 441 }; 442 443 static const char * const spm_parents[] = { 444 "clk26m", 445 "syspll_d2_d8" 446 }; 447 448 static const char * const i2c_parents[] = { 449 "clk26m", 450 "syspll_d2_d8", 451 "univpll_d5_d2" 452 }; 453 454 static const char * const scp_parents[] = { 455 "clk26m", 456 "univpll_d2_d8", 457 "syspll_d5", 458 "syspll_d2_d2", 459 "univpll_d2_d2", 460 "syspll_d3", 461 "univpll_d3" 462 }; 463 464 static const char * const seninf_parents[] = { 465 "clk26m", 466 "univpll_d2_d2", 467 "univpll_d3_d2", 468 "univpll_d2_d4" 469 }; 470 471 static const char * const dxcc_parents[] = { 472 "clk26m", 473 "syspll_d2_d2", 474 "syspll_d2_d4", 475 "syspll_d2_d8" 476 }; 477 478 static const char * const aud_engen1_parents[] = { 479 "clk26m", 480 "apll1_d2", 481 "apll1_d4", 482 "apll1_d8" 483 }; 484 485 static const char * const aud_engen2_parents[] = { 486 "clk26m", 487 "apll2_d2", 488 "apll2_d4", 489 "apll2_d8" 490 }; 491 492 static const char * const faes_ufsfde_parents[] = { 493 "clk26m", 494 "syspll_d2", 495 "syspll_d2_d2", 496 "syspll_d3", 497 "syspll_d2_d4", 498 "univpll_d3" 499 }; 500 501 static const char * const fufs_parents[] = { 502 "clk26m", 503 "syspll_d2_d4", 504 "syspll_d2_d8", 505 "syspll_d2_d16" 506 }; 507 508 static const char * const aud_1_parents[] = { 509 "clk26m", 510 "apll1_ck" 511 }; 512 513 static const char * const aud_2_parents[] = { 514 "clk26m", 515 "apll2_ck" 516 }; 517 518 /* 519 * CRITICAL CLOCK: 520 * axi_sel is the main bus clock of whole SOC. 521 * spm_sel is the clock of the always-on co-processor. 522 */ 523 static const struct mtk_mux top_muxes[] = { 524 /* CLK_CFG_0 */ 525 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel", 526 axi_parents, 0x40, 527 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL), 528 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel", 529 mm_parents, 0x40, 530 0x44, 0x48, 8, 3, 15, 0x004, 1), 531 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel", 532 img_parents, 0x40, 533 0x44, 0x48, 16, 3, 23, 0x004, 2), 534 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel", 535 cam_parents, 0x40, 536 0x44, 0x48, 24, 4, 31, 0x004, 3), 537 /* CLK_CFG_1 */ 538 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel", 539 dsp_parents, 0x50, 540 0x54, 0x58, 0, 4, 7, 0x004, 4), 541 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel", 542 dsp1_parents, 0x50, 543 0x54, 0x58, 8, 4, 15, 0x004, 5), 544 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel", 545 dsp2_parents, 0x50, 546 0x54, 0x58, 16, 4, 23, 0x004, 6), 547 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel", 548 ipu_if_parents, 0x50, 549 0x54, 0x58, 24, 4, 31, 0x004, 7), 550 /* CLK_CFG_2 */ 551 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel", 552 mfg_parents, 0x60, 553 0x64, 0x68, 0, 2, 7, 0x004, 8), 554 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel", 555 f52m_mfg_parents, 0x60, 556 0x64, 0x68, 8, 2, 15, 0x004, 9), 557 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG, "camtg_sel", 558 camtg_parents, 0x60, 559 0x64, 0x68, 16, 3, 23, 0x004, 10), 560 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG2, "camtg2_sel", 561 camtg2_parents, 0x60, 562 0x64, 0x68, 24, 3, 31, 0x004, 11), 563 /* CLK_CFG_3 */ 564 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG3, "camtg3_sel", 565 camtg3_parents, 0x70, 566 0x74, 0x78, 0, 3, 7, 0x004, 12), 567 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG4, "camtg4_sel", 568 camtg4_parents, 0x70, 569 0x74, 0x78, 8, 3, 15, 0x004, 13), 570 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel", 571 uart_parents, 0x70, 572 0x74, 0x78, 16, 1, 23, 0x004, 14), 573 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel", 574 spi_parents, 0x70, 575 0x74, 0x78, 24, 2, 31, 0x004, 15), 576 /* CLK_CFG_4 */ 577 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel", 578 msdc50_hclk_parents, 0x80, 579 0x84, 0x88, 0, 2, 7, 0x004, 16), 580 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", 581 msdc50_0_parents, 0x80, 582 0x84, 0x88, 8, 3, 15, 0x004, 17), 583 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", 584 msdc30_1_parents, 0x80, 585 0x84, 0x88, 16, 3, 23, 0x004, 18), 586 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", 587 msdc30_2_parents, 0x80, 588 0x84, 0x88, 24, 3, 31, 0x004, 19), 589 /* CLK_CFG_5 */ 590 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel", 591 audio_parents, 0x90, 592 0x94, 0x98, 0, 2, 7, 0x004, 20), 593 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", 594 aud_intbus_parents, 0x90, 595 0x94, 0x98, 8, 2, 15, 0x004, 21), 596 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", 597 pmicspi_parents, 0x90, 598 0x94, 0x98, 16, 2, 23, 0x004, 22), 599 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FPWRAP_ULPOSC, "fpwrap_ulposc_sel", 600 fpwrap_ulposc_parents, 0x90, 601 0x94, 0x98, 24, 2, 31, 0x004, 23), 602 /* CLK_CFG_6 */ 603 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel", 604 atb_parents, 0xa0, 605 0xa4, 0xa8, 0, 2, 7, 0x004, 24), 606 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel", 607 dpi0_parents, 0xa0, 608 0xa4, 0xa8, 16, 4, 23, 0x004, 26), 609 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCAM, "scam_sel", 610 scam_parents, 0xa0, 611 0xa4, 0xa8, 24, 1, 31, 0x004, 27), 612 /* CLK_CFG_7 */ 613 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DISP_PWM, "disppwm_sel", 614 disppwm_parents, 0xb0, 615 0xb4, 0xb8, 0, 3, 7, 0x004, 28), 616 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_USB_TOP, "usb_top_sel", 617 usb_top_parents, 0xb0, 618 0xb4, 0xb8, 8, 2, 15, 0x004, 29), 619 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel", 620 ssusb_top_xhci_parents, 0xb0, 621 0xb4, 0xb8, 16, 2, 23, 0x004, 30), 622 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SPM, "spm_sel", 623 spm_parents, 0xb0, 624 0xb4, 0xb8, 24, 1, 31, 0x008, 0, CLK_IS_CRITICAL), 625 /* CLK_CFG_8 */ 626 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel", 627 i2c_parents, 0xc0, 628 0xc4, 0xc8, 0, 2, 7, 0x008, 1), 629 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCP, "scp_sel", 630 scp_parents, 0xc0, 631 0xc4, 0xc8, 8, 3, 15, 0x008, 2), 632 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SENINF, "seninf_sel", 633 seninf_parents, 0xc0, 634 0xc4, 0xc8, 16, 2, 23, 0x008, 3), 635 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DXCC, "dxcc_sel", 636 dxcc_parents, 0xc0, 637 0xc4, 0xc8, 24, 2, 31, 0x008, 4), 638 /* CLK_CFG_9 */ 639 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG1, "aud_eng1_sel", 640 aud_engen1_parents, 0xd0, 641 0xd4, 0xd8, 0, 2, 7, 0x008, 5), 642 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG2, "aud_eng2_sel", 643 aud_engen2_parents, 0xd0, 644 0xd4, 0xd8, 8, 2, 15, 0x008, 6), 645 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FAES_UFSFDE, "faes_ufsfde_sel", 646 faes_ufsfde_parents, 0xd0, 647 0xd4, 0xd8, 16, 3, 23, 0x008, 7), 648 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FUFS, "fufs_sel", 649 fufs_parents, 0xd0, 650 0xd4, 0xd8, 24, 2, 31, 0x008, 8), 651 /* CLK_CFG_10 */ 652 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel", 653 aud_1_parents, 0xe0, 654 0xe4, 0xe8, 0, 1, 7, 0x008, 9), 655 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_2, "aud_2_sel", 656 aud_2_parents, 0xe0, 657 0xe4, 0xe8, 8, 1, 15, 0x008, 10), 658 }; 659 660 static const char * const apll_i2s0_parents[] = { 661 "aud_1_sel", 662 "aud_2_sel" 663 }; 664 665 static const char * const apll_i2s1_parents[] = { 666 "aud_1_sel", 667 "aud_2_sel" 668 }; 669 670 static const char * const apll_i2s2_parents[] = { 671 "aud_1_sel", 672 "aud_2_sel" 673 }; 674 675 static const char * const apll_i2s3_parents[] = { 676 "aud_1_sel", 677 "aud_2_sel" 678 }; 679 680 static const char * const apll_i2s4_parents[] = { 681 "aud_1_sel", 682 "aud_2_sel" 683 }; 684 685 static const char * const apll_i2s5_parents[] = { 686 "aud_1_sel", 687 "aud_2_sel" 688 }; 689 690 static struct mtk_composite top_aud_muxes[] = { 691 MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents, 692 0x320, 8, 1), 693 MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents, 694 0x320, 9, 1), 695 MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents, 696 0x320, 10, 1), 697 MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents, 698 0x320, 11, 1), 699 MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents, 700 0x320, 12, 1), 701 MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents, 702 0x328, 20, 1), 703 }; 704 705 static const char * const mcu_mp0_parents[] = { 706 "clk26m", 707 "armpll_ll", 708 "armpll_div_pll1", 709 "armpll_div_pll2" 710 }; 711 712 static const char * const mcu_mp2_parents[] = { 713 "clk26m", 714 "armpll_l", 715 "armpll_div_pll1", 716 "armpll_div_pll2" 717 }; 718 719 static const char * const mcu_bus_parents[] = { 720 "clk26m", 721 "ccipll", 722 "armpll_div_pll1", 723 "armpll_div_pll2" 724 }; 725 726 static struct mtk_composite mcu_muxes[] = { 727 /* mp0_pll_divider_cfg */ 728 MUX(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 9, 2), 729 /* mp2_pll_divider_cfg */ 730 MUX(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, 9, 2), 731 /* bus_pll_divider_cfg */ 732 MUX(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 9, 2), 733 }; 734 735 static struct mtk_composite top_aud_divs[] = { 736 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel", 737 0x320, 2, 0x324, 8, 0), 738 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel", 739 0x320, 3, 0x324, 8, 8), 740 DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_sel", 741 0x320, 4, 0x324, 8, 16), 742 DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_sel", 743 0x320, 5, 0x324, 8, 24), 744 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel", 745 0x320, 6, 0x328, 8, 0), 746 DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 747 0x320, 7, 0x328, 8, 8), 748 }; 749 750 static const struct mtk_gate_regs top_cg_regs = { 751 .set_ofs = 0x104, 752 .clr_ofs = 0x104, 753 .sta_ofs = 0x104, 754 }; 755 756 #define GATE_TOP(_id, _name, _parent, _shift) \ 757 GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, \ 758 &mtk_clk_gate_ops_no_setclr_inv) 759 760 static const struct mtk_gate top_clks[] = { 761 /* TOP */ 762 GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL1, "armpll_div_pll1", "mainpll", 4), 763 GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL2, "armpll_div_pll2", "univpll", 5), 764 }; 765 766 static const struct mtk_gate_regs infra0_cg_regs = { 767 .set_ofs = 0x80, 768 .clr_ofs = 0x84, 769 .sta_ofs = 0x90, 770 }; 771 772 static const struct mtk_gate_regs infra1_cg_regs = { 773 .set_ofs = 0x88, 774 .clr_ofs = 0x8c, 775 .sta_ofs = 0x94, 776 }; 777 778 static const struct mtk_gate_regs infra2_cg_regs = { 779 .set_ofs = 0xa4, 780 .clr_ofs = 0xa8, 781 .sta_ofs = 0xac, 782 }; 783 784 static const struct mtk_gate_regs infra3_cg_regs = { 785 .set_ofs = 0xc0, 786 .clr_ofs = 0xc4, 787 .sta_ofs = 0xc8, 788 }; 789 790 #define GATE_INFRA0(_id, _name, _parent, _shift) \ 791 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \ 792 &mtk_clk_gate_ops_setclr) 793 794 #define GATE_INFRA1(_id, _name, _parent, _shift) \ 795 GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \ 796 &mtk_clk_gate_ops_setclr) 797 798 #define GATE_INFRA2(_id, _name, _parent, _shift) \ 799 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \ 800 &mtk_clk_gate_ops_setclr) 801 802 #define GATE_INFRA3(_id, _name, _parent, _shift) \ 803 GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \ 804 &mtk_clk_gate_ops_setclr) 805 806 static const struct mtk_gate infra_clks[] = { 807 /* INFRA0 */ 808 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", 809 "axi_sel", 0), 810 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", 811 "axi_sel", 1), 812 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", 813 "axi_sel", 2), 814 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", 815 "axi_sel", 3), 816 GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp", 817 "scp_sel", 4), 818 GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", 819 "f_f26m_ck", 5), 820 GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", 821 "axi_sel", 6), 822 GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb", 823 "axi_sel", 8), 824 GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", 825 "axi_sel", 9), 826 GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", 827 "axi_sel", 10), 828 GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", 829 "i2c_sel", 11), 830 GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1", 831 "i2c_sel", 12), 832 GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", 833 "i2c_sel", 13), 834 GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", 835 "i2c_sel", 14), 836 GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", 837 "axi_sel", 15), 838 GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", 839 "i2c_sel", 16), 840 GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", 841 "i2c_sel", 17), 842 GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", 843 "i2c_sel", 18), 844 GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", 845 "i2c_sel", 19), 846 GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", 847 "i2c_sel", 21), 848 GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", 849 "uart_sel", 22), 850 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", 851 "uart_sel", 23), 852 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", 853 "uart_sel", 24), 854 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", 855 "uart_sel", 25), 856 GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", 857 "axi_sel", 27), 858 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc", 859 "axi_sel", 28), 860 GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", 861 "axi_sel", 31), 862 /* INFRA1 */ 863 GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", 864 "spi_sel", 1), 865 GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", 866 "msdc50_hclk_sel", 2), 867 GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", 868 "axi_sel", 4), 869 GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", 870 "axi_sel", 5), 871 GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck", 872 "msdc50_0_sel", 6), 873 GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc", 874 "f_f26m_ck", 7), 875 GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", 876 "axi_sel", 8), 877 GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", 878 "axi_sel", 9), 879 GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", 880 "f_f26m_ck", 10), 881 GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", 882 "axi_sel", 11), 883 GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", 884 "axi_sel", 12), 885 GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", 886 "axi_sel", 13), 887 GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", 888 "f_f26m_ck", 14), 889 GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck", 890 "msdc30_1_sel", 16), 891 GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck", 892 "msdc30_2_sel", 17), 893 GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma", 894 "axi_sel", 18), 895 GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu", 896 "axi_sel", 19), 897 GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc", 898 "axi_sel", 20), 899 GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", 900 "axi_sel", 23), 901 GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", 902 "axi_sel", 24), 903 GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", 904 "axi_sel", 25), 905 GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", 906 "axi_sel", 26), 907 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", 908 "dxcc_sel", 27), 909 GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", 910 "dxcc_sel", 28), 911 GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk", 912 "axi_sel", 30), 913 GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", 914 "f_f26m_ck", 31), 915 /* INFRA2 */ 916 GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", 917 "f_f26m_ck", 0), 918 GATE_INFRA2(CLK_INFRA_USB, "infra_usb", 919 "usb_top_sel", 1), 920 GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm", 921 "axi_sel", 2), 922 GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, "infra_cldma_bclk", 923 "axi_sel", 3), 924 GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, "infra_audio_26m_bclk", 925 "f_f26m_ck", 4), 926 GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", 927 "spi_sel", 6), 928 GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", 929 "i2c_sel", 7), 930 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share", 931 "f_f26m_ck", 8), 932 GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", 933 "spi_sel", 9), 934 GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", 935 "spi_sel", 10), 936 GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck", 937 "ssusb_top_xhci_sel", 11), 938 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", 939 "fufs_sel", 12), 940 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck", 941 "fufs_sel", 13), 942 GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk", 943 "axi_sel", 14), 944 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", 945 "axi_sel", 16), 946 GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", 947 "i2c_sel", 18), 948 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", 949 "i2c_sel", 19), 950 GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", 951 "i2c_sel", 20), 952 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", 953 "i2c_sel", 21), 954 GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", 955 "i2c_sel", 22), 956 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", 957 "i2c_sel", 23), 958 GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", 959 "i2c_sel", 24), 960 GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", 961 "spi_sel", 25), 962 GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", 963 "spi_sel", 26), 964 GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma", 965 "axi_sel", 27), 966 GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", 967 "fufs_sel", 28), 968 GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", 969 "faes_ufsfde_sel", 29), 970 GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", 971 "fufs_sel", 30), 972 /* INFRA3 */ 973 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", 974 "msdc50_0_sel", 0), 975 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", 976 "msdc50_0_sel", 1), 977 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", 978 "msdc50_0_sel", 2), 979 GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", 980 "axi_sel", 5), 981 GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", 982 "i2c_sel", 6), 983 GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", 984 "msdc50_hclk_sel", 7), 985 GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", 986 "msdc50_hclk_sel", 8), 987 GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", 988 "axi_sel", 16), 989 GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", 990 "axi_sel", 17), 991 GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", 992 "axi_sel", 18), 993 GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", 994 "axi_sel", 19), 995 GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", 996 "f_f26m_ck", 20), 997 GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk", 998 "axi_sel", 21), 999 GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", 1000 "i2c_sel", 22), 1001 GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", 1002 "i2c_sel", 23), 1003 GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", 1004 "msdc50_0_sel", 24), 1005 }; 1006 1007 static const struct mtk_gate_regs peri_cg_regs = { 1008 .set_ofs = 0x20c, 1009 .clr_ofs = 0x20c, 1010 .sta_ofs = 0x20c, 1011 }; 1012 1013 #define GATE_PERI(_id, _name, _parent, _shift) \ 1014 GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, \ 1015 &mtk_clk_gate_ops_no_setclr_inv) 1016 1017 static const struct mtk_gate peri_clks[] = { 1018 GATE_PERI(CLK_PERI_AXI, "peri_axi", "axi_sel", 31), 1019 }; 1020 1021 static const struct mtk_gate_regs apmixed_cg_regs = { 1022 .set_ofs = 0x20, 1023 .clr_ofs = 0x20, 1024 .sta_ofs = 0x20, 1025 }; 1026 1027 #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \ 1028 GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \ 1029 _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags) 1030 1031 #define GATE_APMIXED(_id, _name, _parent, _shift) \ 1032 GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0) 1033 1034 /* 1035 * CRITICAL CLOCK: 1036 * apmixed_appll26m is the toppest clock gate of all PLLs. 1037 */ 1038 static const struct mtk_gate apmixed_clks[] = { 1039 /* AUDIO0 */ 1040 GATE_APMIXED(CLK_APMIXED_SSUSB_26M, "apmixed_ssusb26m", 1041 "f_f26m_ck", 4), 1042 GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL_26M, "apmixed_appll26m", 1043 "f_f26m_ck", 5, CLK_IS_CRITICAL), 1044 GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m", 1045 "f_f26m_ck", 6), 1046 GATE_APMIXED(CLK_APMIXED_MDPLLGP_26M, "apmixed_mdpll26m", 1047 "f_f26m_ck", 7), 1048 GATE_APMIXED(CLK_APMIXED_MMSYS_26M, "apmixed_mmsys26m", 1049 "f_f26m_ck", 8), 1050 GATE_APMIXED(CLK_APMIXED_UFS_26M, "apmixed_ufs26m", 1051 "f_f26m_ck", 9), 1052 GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m", 1053 "f_f26m_ck", 11), 1054 GATE_APMIXED(CLK_APMIXED_MEMPLL_26M, "apmixed_mempll26m", 1055 "f_f26m_ck", 13), 1056 GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m", 1057 "f_f26m_ck", 14), 1058 GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m", 1059 "f_f26m_ck", 16), 1060 GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m", 1061 "f_f26m_ck", 17), 1062 }; 1063 1064 #define MT8183_PLL_FMAX (3800UL * MHZ) 1065 #define MT8183_PLL_FMIN (1500UL * MHZ) 1066 1067 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1068 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1069 _pd_shift, _tuner_reg, _tuner_en_reg, \ 1070 _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1071 _pcw_chg_reg, _div_table) { \ 1072 .id = _id, \ 1073 .name = _name, \ 1074 .reg = _reg, \ 1075 .pwr_reg = _pwr_reg, \ 1076 .en_mask = _en_mask, \ 1077 .flags = _flags, \ 1078 .rst_bar_mask = _rst_bar_mask, \ 1079 .fmax = MT8183_PLL_FMAX, \ 1080 .fmin = MT8183_PLL_FMIN, \ 1081 .pcwbits = _pcwbits, \ 1082 .pcwibits = _pcwibits, \ 1083 .pd_reg = _pd_reg, \ 1084 .pd_shift = _pd_shift, \ 1085 .tuner_reg = _tuner_reg, \ 1086 .tuner_en_reg = _tuner_en_reg, \ 1087 .tuner_en_bit = _tuner_en_bit, \ 1088 .pcw_reg = _pcw_reg, \ 1089 .pcw_shift = _pcw_shift, \ 1090 .pcw_chg_reg = _pcw_chg_reg, \ 1091 .div_table = _div_table, \ 1092 } 1093 1094 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1095 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1096 _pd_shift, _tuner_reg, _tuner_en_reg, \ 1097 _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1098 _pcw_chg_reg) \ 1099 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1100 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1101 _pd_shift, _tuner_reg, _tuner_en_reg, \ 1102 _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1103 _pcw_chg_reg, NULL) 1104 1105 static const struct mtk_pll_div_table armpll_div_table[] = { 1106 { .div = 0, .freq = MT8183_PLL_FMAX }, 1107 { .div = 1, .freq = 1500 * MHZ }, 1108 { .div = 2, .freq = 750 * MHZ }, 1109 { .div = 3, .freq = 375 * MHZ }, 1110 { .div = 4, .freq = 187500000 }, 1111 { } /* sentinel */ 1112 }; 1113 1114 static const struct mtk_pll_div_table mfgpll_div_table[] = { 1115 { .div = 0, .freq = MT8183_PLL_FMAX }, 1116 { .div = 1, .freq = 1600 * MHZ }, 1117 { .div = 2, .freq = 800 * MHZ }, 1118 { .div = 3, .freq = 400 * MHZ }, 1119 { .div = 4, .freq = 200 * MHZ }, 1120 { } /* sentinel */ 1121 }; 1122 1123 static const struct mtk_pll_data plls[] = { 1124 PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0x00000001, 1125 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0, 1126 0x0204, 0, 0, armpll_div_table), 1127 PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0x00000001, 1128 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0, 1129 0x0214, 0, 0, armpll_div_table), 1130 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0x00000001, 1131 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0, 1132 0x0294, 0, 0), 1133 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0x00000001, 1134 HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0, 1135 0x0224, 0, 0), 1136 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0x00000001, 1137 HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0, 1138 0x0234, 0, 0), 1139 PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000001, 1140 0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0, 1141 mfgpll_div_table), 1142 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000001, 1143 0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0), 1144 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0x00000001, 1145 0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0), 1146 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0x00000001, 1147 HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0, 1148 0x0274, 0, 0), 1149 PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000001, 1150 0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0), 1151 PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0x00000001, 1152 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4), 1153 }; 1154 1155 static int clk_mt8183_apmixed_probe(struct platform_device *pdev) 1156 { 1157 struct clk_onecell_data *clk_data; 1158 struct device_node *node = pdev->dev.of_node; 1159 1160 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 1161 1162 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 1163 1164 mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), 1165 clk_data); 1166 1167 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1168 } 1169 1170 static struct clk_onecell_data *top_clk_data; 1171 1172 static void clk_mt8183_top_init_early(struct device_node *node) 1173 { 1174 int i; 1175 1176 top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 1177 1178 for (i = 0; i < CLK_TOP_NR_CLK; i++) 1179 top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER); 1180 1181 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), 1182 top_clk_data); 1183 1184 of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data); 1185 } 1186 1187 CLK_OF_DECLARE_DRIVER(mt8183_topckgen, "mediatek,mt8183-topckgen", 1188 clk_mt8183_top_init_early); 1189 1190 static int clk_mt8183_top_probe(struct platform_device *pdev) 1191 { 1192 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1193 void __iomem *base; 1194 struct device_node *node = pdev->dev.of_node; 1195 1196 base = devm_ioremap_resource(&pdev->dev, res); 1197 if (IS_ERR(base)) 1198 return PTR_ERR(base); 1199 1200 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), 1201 top_clk_data); 1202 1203 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), 1204 top_clk_data); 1205 1206 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); 1207 1208 mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), 1209 node, &mt8183_clk_lock, top_clk_data); 1210 1211 mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes), 1212 base, &mt8183_clk_lock, top_clk_data); 1213 1214 mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), 1215 base, &mt8183_clk_lock, top_clk_data); 1216 1217 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), 1218 top_clk_data); 1219 1220 return of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data); 1221 } 1222 1223 static int clk_mt8183_infra_probe(struct platform_device *pdev) 1224 { 1225 struct clk_onecell_data *clk_data; 1226 struct device_node *node = pdev->dev.of_node; 1227 int r; 1228 1229 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 1230 1231 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), 1232 clk_data); 1233 1234 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1235 if (r) { 1236 dev_err(&pdev->dev, 1237 "%s(): could not register clock provider: %d\n", 1238 __func__, r); 1239 return r; 1240 } 1241 1242 mtk_register_reset_controller_set_clr(node, 4, INFRA_RST0_SET_OFFSET); 1243 1244 return r; 1245 } 1246 1247 static int clk_mt8183_peri_probe(struct platform_device *pdev) 1248 { 1249 struct clk_onecell_data *clk_data; 1250 struct device_node *node = pdev->dev.of_node; 1251 1252 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); 1253 1254 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), 1255 clk_data); 1256 1257 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1258 } 1259 1260 static int clk_mt8183_mcu_probe(struct platform_device *pdev) 1261 { 1262 struct clk_onecell_data *clk_data; 1263 struct device_node *node = pdev->dev.of_node; 1264 void __iomem *base; 1265 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1266 1267 base = devm_ioremap_resource(&pdev->dev, res); 1268 if (IS_ERR(base)) 1269 return PTR_ERR(base); 1270 1271 clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK); 1272 1273 mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base, 1274 &mt8183_clk_lock, clk_data); 1275 1276 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1277 } 1278 1279 static const struct of_device_id of_match_clk_mt8183[] = { 1280 { 1281 .compatible = "mediatek,mt8183-apmixedsys", 1282 .data = clk_mt8183_apmixed_probe, 1283 }, { 1284 .compatible = "mediatek,mt8183-topckgen", 1285 .data = clk_mt8183_top_probe, 1286 }, { 1287 .compatible = "mediatek,mt8183-infracfg", 1288 .data = clk_mt8183_infra_probe, 1289 }, { 1290 .compatible = "mediatek,mt8183-pericfg", 1291 .data = clk_mt8183_peri_probe, 1292 }, { 1293 .compatible = "mediatek,mt8183-mcucfg", 1294 .data = clk_mt8183_mcu_probe, 1295 }, { 1296 /* sentinel */ 1297 } 1298 }; 1299 1300 static int clk_mt8183_probe(struct platform_device *pdev) 1301 { 1302 int (*clk_probe)(struct platform_device *pdev); 1303 int r; 1304 1305 clk_probe = of_device_get_match_data(&pdev->dev); 1306 if (!clk_probe) 1307 return -EINVAL; 1308 1309 r = clk_probe(pdev); 1310 if (r) 1311 dev_err(&pdev->dev, 1312 "could not register clock provider: %s: %d\n", 1313 pdev->name, r); 1314 1315 return r; 1316 } 1317 1318 static struct platform_driver clk_mt8183_drv = { 1319 .probe = clk_mt8183_probe, 1320 .driver = { 1321 .name = "clk-mt8183", 1322 .of_match_table = of_match_clk_mt8183, 1323 }, 1324 }; 1325 1326 static int __init clk_mt8183_init(void) 1327 { 1328 return platform_driver_register(&clk_mt8183_drv); 1329 } 1330 1331 arch_initcall(clk_mt8183_init); 1332